Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8407782 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63584 |
| auto[1] |
6141782 |
1 |
|
|
T24 |
46366 |
|
T26 |
81 |
|
T27 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12044570 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
92996 |
| auto[1] |
2504994 |
1 |
|
|
T24 |
16954 |
|
T26 |
71 |
|
T27 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8459031 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
66685 |
| auto[1] |
6090533 |
1 |
|
|
T24 |
43265 |
|
T26 |
132 |
|
T27 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1779486 |
1 |
|
|
T24 |
13738 |
|
T26 |
44 |
|
T29 |
117811 |
| auto[1] |
auto[0] |
auto[1] |
1245556 |
1 |
|
|
T24 |
9208 |
|
T26 |
44 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1806053 |
1 |
|
|
T24 |
12573 |
|
T26 |
17 |
|
T29 |
123401 |
| auto[1] |
auto[1] |
auto[1] |
1259438 |
1 |
|
|
T24 |
7746 |
|
T26 |
27 |
|
T27 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |