Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8454538 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63584 |
| auto[1] |
6095026 |
1 |
|
|
T24 |
46366 |
|
T26 |
138 |
|
T27 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13760371 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103920 |
| auto[1] |
789193 |
1 |
|
|
T24 |
6030 |
|
T26 |
12 |
|
T29 |
50958 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456511 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62179 |
| auto[1] |
6093053 |
1 |
|
|
T24 |
47771 |
|
T26 |
155 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2645992 |
1 |
|
|
T24 |
21151 |
|
T26 |
79 |
|
T27 |
9 |
| auto[1] |
auto[0] |
auto[1] |
393024 |
1 |
|
|
T24 |
3057 |
|
T26 |
9 |
|
T29 |
25149 |
| auto[1] |
auto[1] |
auto[0] |
2657868 |
1 |
|
|
T24 |
20590 |
|
T26 |
64 |
|
T27 |
9 |
| auto[1] |
auto[1] |
auto[1] |
396169 |
1 |
|
|
T24 |
2973 |
|
T26 |
3 |
|
T29 |
25809 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |