Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456469 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63622 |
| auto[1] |
6093095 |
1 |
|
|
T24 |
46328 |
|
T26 |
118 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12045475 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
90694 |
| auto[1] |
2504089 |
1 |
|
|
T24 |
19256 |
|
T26 |
47 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8465067 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
59877 |
| auto[1] |
6084497 |
1 |
|
|
T24 |
50073 |
|
T26 |
95 |
|
T27 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1791411 |
1 |
|
|
T24 |
15538 |
|
T26 |
16 |
|
T29 |
121530 |
| auto[1] |
auto[0] |
auto[1] |
1257553 |
1 |
|
|
T24 |
9731 |
|
T26 |
24 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1788997 |
1 |
|
|
T24 |
15279 |
|
T26 |
32 |
|
T29 |
120318 |
| auto[1] |
auto[1] |
auto[1] |
1246536 |
1 |
|
|
T24 |
9525 |
|
T26 |
23 |
|
T29 |
75318 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |