Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8445770 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62373 |
| auto[1] |
6103794 |
1 |
|
|
T24 |
47577 |
|
T26 |
162 |
|
T29 |
378072 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12044960 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
91516 |
| auto[1] |
2504604 |
1 |
|
|
T24 |
18434 |
|
T26 |
57 |
|
T29 |
152079 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8461908 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61807 |
| auto[1] |
6087656 |
1 |
|
|
T24 |
48143 |
|
T26 |
111 |
|
T27 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1786718 |
1 |
|
|
T24 |
15058 |
|
T26 |
7 |
|
T27 |
15 |
| auto[1] |
auto[0] |
auto[1] |
1251947 |
1 |
|
|
T24 |
9435 |
|
T26 |
10 |
|
T29 |
78263 |
| auto[1] |
auto[1] |
auto[0] |
1796334 |
1 |
|
|
T24 |
14651 |
|
T26 |
47 |
|
T29 |
115138 |
| auto[1] |
auto[1] |
auto[1] |
1252657 |
1 |
|
|
T24 |
8999 |
|
T26 |
47 |
|
T29 |
73816 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |