Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8488923 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
60333 |
| auto[1] |
6060641 |
1 |
|
|
T24 |
49617 |
|
T26 |
120 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13760952 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104096 |
| auto[1] |
788612 |
1 |
|
|
T24 |
5854 |
|
T26 |
6 |
|
T29 |
52016 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8460305 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62750 |
| auto[1] |
6089259 |
1 |
|
|
T24 |
47200 |
|
T26 |
103 |
|
T27 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2674841 |
1 |
|
|
T24 |
19628 |
|
T26 |
53 |
|
T27 |
8 |
| auto[1] |
auto[0] |
auto[1] |
397821 |
1 |
|
|
T24 |
2671 |
|
T26 |
3 |
|
T29 |
26747 |
| auto[1] |
auto[1] |
auto[0] |
2625806 |
1 |
|
|
T24 |
21718 |
|
T26 |
44 |
|
T29 |
166708 |
| auto[1] |
auto[1] |
auto[1] |
390791 |
1 |
|
|
T24 |
3183 |
|
T26 |
3 |
|
T29 |
25269 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |