Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8453821 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63734 |
| auto[1] |
6095743 |
1 |
|
|
T24 |
46216 |
|
T26 |
102 |
|
T29 |
386720 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13762165 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103602 |
| auto[1] |
787399 |
1 |
|
|
T24 |
6348 |
|
T26 |
4 |
|
T29 |
50215 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8465555 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
59990 |
| auto[1] |
6084009 |
1 |
|
|
T24 |
49960 |
|
T26 |
94 |
|
T29 |
382040 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2651966 |
1 |
|
|
T24 |
22509 |
|
T26 |
44 |
|
T29 |
167603 |
| auto[1] |
auto[0] |
auto[1] |
392924 |
1 |
|
|
T24 |
3264 |
|
T26 |
2 |
|
T29 |
25291 |
| auto[1] |
auto[1] |
auto[0] |
2644644 |
1 |
|
|
T24 |
21103 |
|
T26 |
46 |
|
T29 |
164222 |
| auto[1] |
auto[1] |
auto[1] |
394475 |
1 |
|
|
T24 |
3084 |
|
T26 |
2 |
|
T29 |
24924 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |