Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8468149 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
60165 |
| auto[1] |
6081415 |
1 |
|
|
T24 |
49785 |
|
T26 |
64 |
|
T27 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13756175 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104134 |
| auto[1] |
793389 |
1 |
|
|
T24 |
5816 |
|
T26 |
10 |
|
T29 |
51732 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8436043 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62924 |
| auto[1] |
6113521 |
1 |
|
|
T24 |
47026 |
|
T26 |
128 |
|
T29 |
388624 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2655985 |
1 |
|
|
T24 |
19836 |
|
T26 |
81 |
|
T29 |
162478 |
| auto[1] |
auto[0] |
auto[1] |
395127 |
1 |
|
|
T24 |
2820 |
|
T26 |
8 |
|
T29 |
24920 |
| auto[1] |
auto[1] |
auto[0] |
2664147 |
1 |
|
|
T24 |
21374 |
|
T26 |
37 |
|
T29 |
174414 |
| auto[1] |
auto[1] |
auto[1] |
398262 |
1 |
|
|
T24 |
2996 |
|
T26 |
2 |
|
T29 |
26812 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |