Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8429653 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63923 |
| auto[1] |
6119911 |
1 |
|
|
T24 |
46027 |
|
T26 |
100 |
|
T27 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13759161 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103929 |
| auto[1] |
790403 |
1 |
|
|
T24 |
6021 |
|
T26 |
7 |
|
T29 |
51530 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8448057 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
61711 |
| auto[1] |
6101507 |
1 |
|
|
T24 |
48239 |
|
T26 |
106 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2652255 |
1 |
|
|
T24 |
22026 |
|
T26 |
54 |
|
T27 |
14 |
| auto[1] |
auto[0] |
auto[1] |
395162 |
1 |
|
|
T24 |
3117 |
|
T26 |
4 |
|
T29 |
25793 |
| auto[1] |
auto[1] |
auto[0] |
2658849 |
1 |
|
|
T24 |
20192 |
|
T26 |
45 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[1] |
395241 |
1 |
|
|
T24 |
2904 |
|
T26 |
3 |
|
T29 |
25737 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |