Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8460811 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
63351 |
| auto[1] |
6088753 |
1 |
|
|
T24 |
46599 |
|
T26 |
163 |
|
T27 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13760398 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
103969 |
| auto[1] |
789166 |
1 |
|
|
T24 |
5981 |
|
T26 |
6 |
|
T29 |
52103 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8457538 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62430 |
| auto[1] |
6092026 |
1 |
|
|
T24 |
47520 |
|
T26 |
120 |
|
T27 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2645750 |
1 |
|
|
T24 |
21186 |
|
T26 |
32 |
|
T27 |
14 |
| auto[1] |
auto[0] |
auto[1] |
393425 |
1 |
|
|
T24 |
3028 |
|
T29 |
26773 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2657110 |
1 |
|
|
T24 |
20353 |
|
T26 |
82 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[1] |
395741 |
1 |
|
|
T24 |
2953 |
|
T26 |
6 |
|
T29 |
25330 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |