Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8466470 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62749 |
| auto[1] |
6083094 |
1 |
|
|
T24 |
47201 |
|
T26 |
94 |
|
T27 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13754609 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
104102 |
| auto[1] |
794955 |
1 |
|
|
T24 |
5848 |
|
T26 |
6 |
|
T29 |
52869 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8419927 |
1 |
|
|
T22 |
1 |
|
T23 |
278 |
|
T24 |
62609 |
| auto[1] |
6129637 |
1 |
|
|
T24 |
47341 |
|
T26 |
104 |
|
T27 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2674570 |
1 |
|
|
T24 |
20748 |
|
T26 |
60 |
|
T27 |
8 |
| auto[1] |
auto[0] |
auto[1] |
398433 |
1 |
|
|
T24 |
2924 |
|
T26 |
3 |
|
T29 |
26001 |
| auto[1] |
auto[1] |
auto[0] |
2660112 |
1 |
|
|
T24 |
20745 |
|
T26 |
38 |
|
T29 |
175751 |
| auto[1] |
auto[1] |
auto[1] |
396522 |
1 |
|
|
T24 |
2924 |
|
T26 |
3 |
|
T29 |
26868 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |