Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T762 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.789157115 Mar 26 12:26:56 PM PDT 24 Mar 26 12:26:58 PM PDT 24 35401572 ps
T763 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3202851988 Mar 26 12:26:40 PM PDT 24 Mar 26 12:26:43 PM PDT 24 126002912 ps
T764 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3617791598 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:44 PM PDT 24 50355424 ps
T89 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1754438752 Mar 26 12:25:44 PM PDT 24 Mar 26 12:25:45 PM PDT 24 47040968 ps
T765 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3238929215 Mar 26 12:26:47 PM PDT 24 Mar 26 12:26:50 PM PDT 24 156807295 ps
T766 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1890773873 Mar 26 12:24:59 PM PDT 24 Mar 26 12:25:00 PM PDT 24 36492846 ps
T767 /workspace/coverage/cover_reg_top/28.gpio_intr_test.165020358 Mar 26 12:24:49 PM PDT 24 Mar 26 12:24:50 PM PDT 24 51461518 ps
T768 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.541570849 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:49 PM PDT 24 54720974 ps
T769 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3817456181 Mar 26 12:26:25 PM PDT 24 Mar 26 12:26:26 PM PDT 24 14827200 ps
T92 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.364609468 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:26 PM PDT 24 22742705 ps
T770 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1045635923 Mar 26 12:26:46 PM PDT 24 Mar 26 12:26:48 PM PDT 24 301956856 ps
T103 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2111101250 Mar 26 12:23:49 PM PDT 24 Mar 26 12:23:52 PM PDT 24 120177828 ps
T771 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2234617468 Mar 26 12:25:55 PM PDT 24 Mar 26 12:25:56 PM PDT 24 128245361 ps
T772 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2507747877 Mar 26 12:24:33 PM PDT 24 Mar 26 12:24:34 PM PDT 24 160381850 ps
T773 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2867328909 Mar 26 12:26:56 PM PDT 24 Mar 26 12:26:57 PM PDT 24 34179483 ps
T774 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1119903269 Mar 26 12:26:28 PM PDT 24 Mar 26 12:26:29 PM PDT 24 25696385 ps
T775 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1311677776 Mar 26 12:24:24 PM PDT 24 Mar 26 12:24:25 PM PDT 24 84902371 ps
T776 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1381080552 Mar 26 12:26:41 PM PDT 24 Mar 26 12:26:43 PM PDT 24 291186612 ps
T777 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2174605516 Mar 26 12:26:53 PM PDT 24 Mar 26 12:26:56 PM PDT 24 45242988 ps
T43 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2419666438 Mar 26 12:24:37 PM PDT 24 Mar 26 12:24:39 PM PDT 24 73043409 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2398407946 Mar 26 12:25:29 PM PDT 24 Mar 26 12:25:30 PM PDT 24 55189685 ps
T779 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.927334893 Mar 26 12:24:34 PM PDT 24 Mar 26 12:24:35 PM PDT 24 44272941 ps
T44 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3240500989 Mar 26 12:24:14 PM PDT 24 Mar 26 12:24:16 PM PDT 24 754175214 ps
T780 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.435343938 Mar 26 12:26:24 PM PDT 24 Mar 26 12:26:25 PM PDT 24 58796413 ps
T781 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2067189046 Mar 26 12:26:46 PM PDT 24 Mar 26 12:26:47 PM PDT 24 111964044 ps
T782 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1479249845 Mar 26 12:25:45 PM PDT 24 Mar 26 12:25:46 PM PDT 24 61565410 ps
T783 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.510846641 Mar 26 12:26:53 PM PDT 24 Mar 26 12:26:54 PM PDT 24 39478858 ps
T784 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2332585987 Mar 26 12:23:56 PM PDT 24 Mar 26 12:23:56 PM PDT 24 13412110 ps
T785 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2345181114 Mar 26 12:26:54 PM PDT 24 Mar 26 12:26:56 PM PDT 24 439491661 ps
T91 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1673107702 Mar 26 12:26:24 PM PDT 24 Mar 26 12:26:25 PM PDT 24 11815388 ps
T786 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1367728515 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:49 PM PDT 24 23945980 ps
T787 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3606345052 Mar 26 12:26:25 PM PDT 24 Mar 26 12:26:26 PM PDT 24 81890168 ps
T788 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2368390332 Mar 26 12:24:16 PM PDT 24 Mar 26 12:24:17 PM PDT 24 25294108 ps
T789 /workspace/coverage/cover_reg_top/35.gpio_intr_test.4120333149 Mar 26 12:26:02 PM PDT 24 Mar 26 12:26:02 PM PDT 24 49801181 ps
T790 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1246010983 Mar 26 12:24:33 PM PDT 24 Mar 26 12:24:33 PM PDT 24 15190288 ps
T791 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1263480600 Mar 26 12:26:11 PM PDT 24 Mar 26 12:26:12 PM PDT 24 16948215 ps
T792 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2956723502 Mar 26 12:24:56 PM PDT 24 Mar 26 12:24:57 PM PDT 24 42201316 ps
T793 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2369013382 Mar 26 12:26:46 PM PDT 24 Mar 26 12:26:47 PM PDT 24 43400359 ps
T794 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2017720356 Mar 26 12:23:49 PM PDT 24 Mar 26 12:23:51 PM PDT 24 84508005 ps
T93 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3420181085 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:26 PM PDT 24 116835674 ps
T795 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.617659579 Mar 26 12:25:37 PM PDT 24 Mar 26 12:25:39 PM PDT 24 38400436 ps
T796 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.692824729 Mar 26 12:26:41 PM PDT 24 Mar 26 12:26:43 PM PDT 24 446711917 ps
T797 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3717480792 Mar 26 12:26:24 PM PDT 24 Mar 26 12:26:26 PM PDT 24 32250339 ps
T798 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1872536448 Mar 26 12:24:40 PM PDT 24 Mar 26 12:24:41 PM PDT 24 29249981 ps
T799 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2731409096 Mar 26 12:25:55 PM PDT 24 Mar 26 12:25:56 PM PDT 24 65189804 ps
T800 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1548188815 Mar 26 12:24:26 PM PDT 24 Mar 26 12:24:27 PM PDT 24 42441297 ps
T801 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4191527900 Mar 26 12:24:33 PM PDT 24 Mar 26 12:24:34 PM PDT 24 94187540 ps
T802 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2268994433 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:25 PM PDT 24 33656158 ps
T90 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.12788529 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:23 PM PDT 24 49949911 ps
T803 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3203781130 Mar 26 12:26:54 PM PDT 24 Mar 26 12:26:55 PM PDT 24 30684568 ps
T804 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.504985892 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:25 PM PDT 24 13500547 ps
T805 /workspace/coverage/cover_reg_top/0.gpio_intr_test.825467694 Mar 26 12:27:10 PM PDT 24 Mar 26 12:27:10 PM PDT 24 28628981 ps
T806 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1495503596 Mar 26 12:26:46 PM PDT 24 Mar 26 12:26:47 PM PDT 24 46605762 ps
T807 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2455616283 Mar 26 12:24:55 PM PDT 24 Mar 26 12:24:57 PM PDT 24 47126489 ps
T808 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.189273661 Mar 26 12:26:53 PM PDT 24 Mar 26 12:26:55 PM PDT 24 52702272 ps
T809 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1020134999 Mar 26 12:24:44 PM PDT 24 Mar 26 12:24:46 PM PDT 24 117556053 ps
T810 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.151779179 Mar 26 12:26:46 PM PDT 24 Mar 26 12:26:47 PM PDT 24 79371462 ps
T811 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3181649129 Mar 26 12:24:54 PM PDT 24 Mar 26 12:24:55 PM PDT 24 15476550 ps
T812 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2573243308 Mar 26 12:24:08 PM PDT 24 Mar 26 12:24:09 PM PDT 24 15566894 ps
T813 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3676130169 Mar 26 12:25:57 PM PDT 24 Mar 26 12:25:58 PM PDT 24 12490019 ps
T814 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2807102614 Mar 26 12:26:55 PM PDT 24 Mar 26 12:26:55 PM PDT 24 13496526 ps
T815 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2302277991 Mar 26 12:25:28 PM PDT 24 Mar 26 12:25:31 PM PDT 24 262479081 ps
T816 /workspace/coverage/cover_reg_top/20.gpio_intr_test.734508367 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:49 PM PDT 24 32433383 ps
T817 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.261868048 Mar 26 12:26:22 PM PDT 24 Mar 26 12:26:24 PM PDT 24 1072546236 ps
T818 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4231701953 Mar 26 12:24:10 PM PDT 24 Mar 26 12:24:11 PM PDT 24 52078732 ps
T819 /workspace/coverage/cover_reg_top/30.gpio_intr_test.859113867 Mar 26 12:25:02 PM PDT 24 Mar 26 12:25:03 PM PDT 24 12918187 ps
T820 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3541012729 Mar 26 12:25:37 PM PDT 24 Mar 26 12:25:38 PM PDT 24 107388822 ps
T821 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2356413408 Mar 26 12:27:20 PM PDT 24 Mar 26 12:27:21 PM PDT 24 26647362 ps
T822 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.969281844 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:49 PM PDT 24 35043699 ps
T94 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3406566529 Mar 26 12:26:54 PM PDT 24 Mar 26 12:26:55 PM PDT 24 42102156 ps
T823 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1309029492 Mar 26 12:25:00 PM PDT 24 Mar 26 12:25:01 PM PDT 24 25543919 ps
T824 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.21817406 Mar 26 12:26:25 PM PDT 24 Mar 26 12:26:26 PM PDT 24 30887314 ps
T95 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2886203417 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:23 PM PDT 24 21634027 ps
T825 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3584656817 Mar 26 12:25:56 PM PDT 24 Mar 26 12:25:57 PM PDT 24 52223408 ps
T826 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.630908003 Mar 26 12:26:53 PM PDT 24 Mar 26 12:26:55 PM PDT 24 44419074 ps
T827 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1919799869 Mar 26 12:24:49 PM PDT 24 Mar 26 12:24:50 PM PDT 24 13043790 ps
T828 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1664308098 Mar 26 12:25:07 PM PDT 24 Mar 26 12:25:09 PM PDT 24 69610399 ps
T829 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.195998010 Mar 26 12:26:13 PM PDT 24 Mar 26 12:26:15 PM PDT 24 77682275 ps
T830 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1516615411 Mar 26 12:26:56 PM PDT 24 Mar 26 12:26:57 PM PDT 24 12480759 ps
T831 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1729554515 Mar 26 12:25:07 PM PDT 24 Mar 26 12:25:10 PM PDT 24 90609717 ps
T832 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.958743140 Mar 26 12:23:30 PM PDT 24 Mar 26 12:23:31 PM PDT 24 36115544 ps
T833 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2335094039 Mar 26 12:26:24 PM PDT 24 Mar 26 12:26:25 PM PDT 24 54299294 ps
T834 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1806199214 Mar 26 12:25:37 PM PDT 24 Mar 26 12:25:38 PM PDT 24 19428203 ps
T835 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1213173031 Mar 26 12:26:02 PM PDT 24 Mar 26 12:26:02 PM PDT 24 26419052 ps
T104 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2193552085 Mar 26 12:26:56 PM PDT 24 Mar 26 12:26:57 PM PDT 24 70171934 ps
T836 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3040417965 Mar 26 12:25:11 PM PDT 24 Mar 26 12:25:13 PM PDT 24 303309559 ps
T837 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4186839999 Mar 26 12:26:41 PM PDT 24 Mar 26 12:26:42 PM PDT 24 32124736 ps
T838 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1846789424 Mar 26 12:26:35 PM PDT 24 Mar 26 12:26:36 PM PDT 24 35994770 ps
T839 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1245413605 Mar 26 12:24:49 PM PDT 24 Mar 26 12:24:50 PM PDT 24 46100922 ps
T840 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1064146983 Mar 26 12:26:53 PM PDT 24 Mar 26 12:26:55 PM PDT 24 108156096 ps
T841 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3068015499 Mar 26 12:24:19 PM PDT 24 Mar 26 12:24:20 PM PDT 24 174688775 ps
T842 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1966905855 Mar 26 12:24:45 PM PDT 24 Mar 26 12:24:45 PM PDT 24 45805733 ps
T843 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3772672158 Mar 26 12:24:48 PM PDT 24 Mar 26 12:24:49 PM PDT 24 14827577 ps
T844 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3671966585 Mar 26 12:25:01 PM PDT 24 Mar 26 12:25:02 PM PDT 24 73841069 ps
T845 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1524140920 Mar 26 12:24:52 PM PDT 24 Mar 26 12:24:53 PM PDT 24 50636758 ps
T846 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1075720426 Mar 26 12:26:37 PM PDT 24 Mar 26 12:26:39 PM PDT 24 41813814 ps
T847 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3288886953 Mar 26 12:25:19 PM PDT 24 Mar 26 12:25:20 PM PDT 24 139258999 ps
T848 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1001996121 Mar 26 12:25:32 PM PDT 24 Mar 26 12:25:33 PM PDT 24 71048332 ps
T849 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3228821634 Mar 26 12:24:57 PM PDT 24 Mar 26 12:24:58 PM PDT 24 99005057 ps
T850 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2227502594 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:45 PM PDT 24 49838079 ps
T851 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3581458651 Mar 26 12:26:11 PM PDT 24 Mar 26 12:26:13 PM PDT 24 170205369 ps
T852 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2405022941 Mar 26 12:26:41 PM PDT 24 Mar 26 12:26:42 PM PDT 24 519689031 ps
T853 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4053323085 Mar 26 12:25:17 PM PDT 24 Mar 26 12:25:17 PM PDT 24 84186726 ps
T854 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1098769865 Mar 26 12:25:20 PM PDT 24 Mar 26 12:25:22 PM PDT 24 66308892 ps
T855 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2213561703 Mar 26 12:25:05 PM PDT 24 Mar 26 12:25:07 PM PDT 24 318569043 ps
T856 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4161935143 Mar 26 12:26:33 PM PDT 24 Mar 26 12:26:34 PM PDT 24 237783812 ps
T857 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2889301493 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:10 PM PDT 24 53579091 ps
T858 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1203222147 Mar 26 12:25:45 PM PDT 24 Mar 26 12:25:46 PM PDT 24 836679326 ps
T859 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2555915308 Mar 26 12:25:01 PM PDT 24 Mar 26 12:25:02 PM PDT 24 78511360 ps
T860 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.81400385 Mar 26 12:26:21 PM PDT 24 Mar 26 12:26:22 PM PDT 24 88406126 ps
T861 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439075250 Mar 26 12:25:53 PM PDT 24 Mar 26 12:25:54 PM PDT 24 51639522 ps
T862 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4267733559 Mar 26 12:25:46 PM PDT 24 Mar 26 12:25:47 PM PDT 24 51133572 ps
T863 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2562259153 Mar 26 12:26:15 PM PDT 24 Mar 26 12:26:16 PM PDT 24 43445311 ps
T864 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3845850640 Mar 26 12:25:18 PM PDT 24 Mar 26 12:25:18 PM PDT 24 27203682 ps
T865 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3911232959 Mar 26 12:26:01 PM PDT 24 Mar 26 12:26:02 PM PDT 24 537404229 ps
T866 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1136894290 Mar 26 12:25:14 PM PDT 24 Mar 26 12:25:15 PM PDT 24 26210612 ps
T867 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1768361783 Mar 26 12:25:45 PM PDT 24 Mar 26 12:25:47 PM PDT 24 53264874 ps
T868 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3126299796 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:11 PM PDT 24 162028370 ps
T869 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.80647793 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:45 PM PDT 24 65891508 ps
T870 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2162466241 Mar 26 12:25:32 PM PDT 24 Mar 26 12:25:34 PM PDT 24 49554697 ps
T871 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3132035593 Mar 26 12:25:35 PM PDT 24 Mar 26 12:25:37 PM PDT 24 194576671 ps
T872 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.73530571 Mar 26 12:26:08 PM PDT 24 Mar 26 12:26:10 PM PDT 24 155421098 ps
T873 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.792706089 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:11 PM PDT 24 311527767 ps
T874 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2886173185 Mar 26 12:25:46 PM PDT 24 Mar 26 12:25:47 PM PDT 24 44518608 ps
T875 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3605007948 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:50 PM PDT 24 41138022 ps
T876 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.16942597 Mar 26 12:24:47 PM PDT 24 Mar 26 12:24:49 PM PDT 24 43565873 ps
T877 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2697755753 Mar 26 12:26:09 PM PDT 24 Mar 26 12:26:10 PM PDT 24 141375932 ps
T878 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1482706832 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:44 PM PDT 24 174995209 ps
T879 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1188142205 Mar 26 12:25:19 PM PDT 24 Mar 26 12:25:20 PM PDT 24 51149530 ps
T880 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3506690309 Mar 26 12:25:06 PM PDT 24 Mar 26 12:25:08 PM PDT 24 178650867 ps
T881 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1964105349 Mar 26 12:26:26 PM PDT 24 Mar 26 12:26:28 PM PDT 24 139205706 ps
T882 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.867481348 Mar 26 12:25:42 PM PDT 24 Mar 26 12:25:43 PM PDT 24 31052772 ps
T883 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.349217742 Mar 26 12:26:05 PM PDT 24 Mar 26 12:26:06 PM PDT 24 56465656 ps
T884 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3667099888 Mar 26 12:25:19 PM PDT 24 Mar 26 12:25:21 PM PDT 24 176255129 ps
T885 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1920198693 Mar 26 12:26:13 PM PDT 24 Mar 26 12:26:14 PM PDT 24 23158280 ps
T886 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1152280015 Mar 26 12:26:25 PM PDT 24 Mar 26 12:26:26 PM PDT 24 202477786 ps
T887 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.473719174 Mar 26 12:26:00 PM PDT 24 Mar 26 12:26:01 PM PDT 24 65434380 ps
T888 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2629505701 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:44 PM PDT 24 70513856 ps
T889 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1227988210 Mar 26 12:24:54 PM PDT 24 Mar 26 12:24:56 PM PDT 24 65799643 ps
T890 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1984751951 Mar 26 12:25:19 PM PDT 24 Mar 26 12:25:21 PM PDT 24 149037122 ps
T891 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3668861734 Mar 26 12:25:02 PM PDT 24 Mar 26 12:25:03 PM PDT 24 118801330 ps
T892 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2859460733 Mar 26 12:26:13 PM PDT 24 Mar 26 12:26:15 PM PDT 24 205727798 ps
T893 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639342223 Mar 26 12:25:03 PM PDT 24 Mar 26 12:25:04 PM PDT 24 91379800 ps
T894 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1063861195 Mar 26 12:26:34 PM PDT 24 Mar 26 12:26:35 PM PDT 24 207288122 ps
T895 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.118757314 Mar 26 12:26:45 PM PDT 24 Mar 26 12:26:46 PM PDT 24 116242261 ps
T896 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2588609685 Mar 26 12:25:45 PM PDT 24 Mar 26 12:25:46 PM PDT 24 60757928 ps
T897 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4163942253 Mar 26 12:25:34 PM PDT 24 Mar 26 12:25:35 PM PDT 24 141402329 ps
T898 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1516537354 Mar 26 12:26:14 PM PDT 24 Mar 26 12:26:14 PM PDT 24 179016881 ps
T899 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.443356954 Mar 26 12:26:37 PM PDT 24 Mar 26 12:26:38 PM PDT 24 194777224 ps
T900 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2792392808 Mar 26 12:26:11 PM PDT 24 Mar 26 12:26:13 PM PDT 24 72281642 ps
T901 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2585899916 Mar 26 12:26:44 PM PDT 24 Mar 26 12:26:46 PM PDT 24 88754458 ps
T902 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2252579237 Mar 26 12:25:35 PM PDT 24 Mar 26 12:25:36 PM PDT 24 129336848 ps
T903 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1535666138 Mar 26 12:25:36 PM PDT 24 Mar 26 12:25:37 PM PDT 24 211595410 ps
T904 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.843764877 Mar 26 12:26:22 PM PDT 24 Mar 26 12:26:23 PM PDT 24 217819421 ps
T905 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2772639313 Mar 26 12:25:34 PM PDT 24 Mar 26 12:25:35 PM PDT 24 86222107 ps
T906 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3800216024 Mar 26 12:25:18 PM PDT 24 Mar 26 12:25:18 PM PDT 24 72721013 ps
T907 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2484468875 Mar 26 12:25:34 PM PDT 24 Mar 26 12:25:36 PM PDT 24 54145127 ps
T908 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1599846460 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:10 PM PDT 24 37607734 ps
T909 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3886132228 Mar 26 12:25:01 PM PDT 24 Mar 26 12:25:03 PM PDT 24 239743276 ps
T910 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.575467398 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:45 PM PDT 24 215930510 ps
T911 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2283323510 Mar 26 12:25:34 PM PDT 24 Mar 26 12:25:35 PM PDT 24 55877207 ps
T912 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1657190146 Mar 26 12:25:20 PM PDT 24 Mar 26 12:25:21 PM PDT 24 180418837 ps
T913 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3786603798 Mar 26 12:25:30 PM PDT 24 Mar 26 12:25:31 PM PDT 24 196368231 ps
T914 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1026347277 Mar 26 12:25:32 PM PDT 24 Mar 26 12:25:33 PM PDT 24 106041771 ps
T915 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2775837107 Mar 26 12:25:32 PM PDT 24 Mar 26 12:25:33 PM PDT 24 193163660 ps
T916 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3770174148 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:22 PM PDT 24 1403426607 ps
T917 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.598011648 Mar 26 12:26:33 PM PDT 24 Mar 26 12:26:34 PM PDT 24 69162254 ps
T918 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2374433302 Mar 26 12:25:05 PM PDT 24 Mar 26 12:25:07 PM PDT 24 198403428 ps
T919 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2185380598 Mar 26 12:25:02 PM PDT 24 Mar 26 12:25:03 PM PDT 24 174381330 ps
T920 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3023172262 Mar 26 12:25:39 PM PDT 24 Mar 26 12:25:41 PM PDT 24 77598646 ps
T921 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3930776867 Mar 26 12:26:22 PM PDT 24 Mar 26 12:26:23 PM PDT 24 346474607 ps
T922 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.114098332 Mar 26 12:25:45 PM PDT 24 Mar 26 12:25:46 PM PDT 24 53360054 ps
T923 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3243357308 Mar 26 12:26:06 PM PDT 24 Mar 26 12:26:07 PM PDT 24 219947700 ps
T924 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2159292873 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:44 PM PDT 24 146753983 ps
T925 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2088398979 Mar 26 12:26:44 PM PDT 24 Mar 26 12:26:46 PM PDT 24 86562879 ps
T926 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2637422275 Mar 26 12:25:30 PM PDT 24 Mar 26 12:25:31 PM PDT 24 137753065 ps
T927 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2974651798 Mar 26 12:26:46 PM PDT 24 Mar 26 12:26:48 PM PDT 24 110857759 ps
T928 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.240090442 Mar 26 12:26:28 PM PDT 24 Mar 26 12:26:29 PM PDT 24 104518681 ps
T929 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3114585493 Mar 26 12:26:09 PM PDT 24 Mar 26 12:26:10 PM PDT 24 191959310 ps
T930 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1020436471 Mar 26 12:25:34 PM PDT 24 Mar 26 12:25:35 PM PDT 24 162003026 ps
T931 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.239502678 Mar 26 12:25:19 PM PDT 24 Mar 26 12:25:20 PM PDT 24 64395279 ps
T932 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.875831649 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:11 PM PDT 24 114069317 ps
T933 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.652302382 Mar 26 12:25:51 PM PDT 24 Mar 26 12:25:52 PM PDT 24 116575903 ps
T934 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1998154526 Mar 26 12:25:08 PM PDT 24 Mar 26 12:25:10 PM PDT 24 206563585 ps
T935 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2869804541 Mar 26 12:25:34 PM PDT 24 Mar 26 12:25:35 PM PDT 24 48343541 ps
T936 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1778959278 Mar 26 12:25:31 PM PDT 24 Mar 26 12:25:32 PM PDT 24 29797945 ps
T937 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.645171044 Mar 26 12:27:03 PM PDT 24 Mar 26 12:27:04 PM PDT 24 53288493 ps
T938 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1146010940 Mar 26 12:25:32 PM PDT 24 Mar 26 12:25:33 PM PDT 24 62468643 ps
T939 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2234084345 Mar 26 12:26:23 PM PDT 24 Mar 26 12:26:24 PM PDT 24 57256756 ps
T940 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1179095901 Mar 26 12:26:54 PM PDT 24 Mar 26 12:26:55 PM PDT 24 167393226 ps
T941 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3072796299 Mar 26 12:25:20 PM PDT 24 Mar 26 12:25:22 PM PDT 24 57692404 ps
T942 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4211727867 Mar 26 12:25:33 PM PDT 24 Mar 26 12:25:34 PM PDT 24 36942566 ps
T943 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3855613749 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:44 PM PDT 24 40145940 ps

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.696827159
Short name T29
Test name
Test status
Simulation time 2113295796082 ps
CPU time 2470.67 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 01:11:17 PM PDT 24
Peak memory 198164 kb
Host smart-99e7658e-ab4e-49f5-8055-a79f9b09ba5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=696827159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.696827159
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3537138550
Short name T105
Test name
Test status
Simulation time 54250202 ps
CPU time 2.14 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 197924 kb
Host smart-68a9477d-6f3a-4e8c-940c-e4cc62554b8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537138550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3537138550
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1796632512
Short name T1
Test name
Test status
Simulation time 369184937 ps
CPU time 4.98 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:55 PM PDT 24
Peak memory 197840 kb
Host smart-0f5aeabd-df0c-44ba-92f8-5e09a786a3b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796632512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1796632512
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2447763149
Short name T77
Test name
Test status
Simulation time 36253856 ps
CPU time 0.9 seconds
Started Mar 26 12:24:44 PM PDT 24
Finished Mar 26 12:24:45 PM PDT 24
Peak memory 195936 kb
Host smart-7428c1dd-be3f-4348-96f9-2b1c2dfda35c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447763149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2447763149
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1519934891
Short name T38
Test name
Test status
Simulation time 524651016 ps
CPU time 0.81 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:26:42 PM PDT 24
Peak memory 196412 kb
Host smart-236f738f-499f-4324-a9f0-4face42c6d7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519934891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1519934891
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1160242984
Short name T118
Test name
Test status
Simulation time 13800124 ps
CPU time 0.56 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 193720 kb
Host smart-e5ccaaac-9d07-4f18-bf19-fcb777774fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160242984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1160242984
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.760703958
Short name T49
Test name
Test status
Simulation time 94964637 ps
CPU time 0.78 seconds
Started Mar 26 12:29:38 PM PDT 24
Finished Mar 26 12:29:40 PM PDT 24
Peak memory 213540 kb
Host smart-bb48b7d2-5958-42cc-ae34-de2cfe68574c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760703958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.760703958
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.261868048
Short name T817
Test name
Test status
Simulation time 1072546236 ps
CPU time 1.34 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:26:24 PM PDT 24
Peak memory 195812 kb
Host smart-704e0819-1d94-469e-bb75-1d6044dd60c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261868048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.261868048
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2981690281
Short name T75
Test name
Test status
Simulation time 114128165 ps
CPU time 0.81 seconds
Started Mar 26 12:27:20 PM PDT 24
Finished Mar 26 12:27:21 PM PDT 24
Peak memory 195984 kb
Host smart-44ee6837-1270-4359-9ca0-e8d369fdc01f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981690281 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2981690281
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3576483894
Short name T79
Test name
Test status
Simulation time 131383117 ps
CPU time 1.68 seconds
Started Mar 26 12:24:12 PM PDT 24
Finished Mar 26 12:24:14 PM PDT 24
Peak memory 197636 kb
Host smart-a44004b1-c300-4244-9f21-1dfdda68caef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576483894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3576483894
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.374736534
Short name T86
Test name
Test status
Simulation time 19168316 ps
CPU time 0.68 seconds
Started Mar 26 12:24:41 PM PDT 24
Finished Mar 26 12:24:42 PM PDT 24
Peak memory 194624 kb
Host smart-738ad89a-9951-4270-9bf4-4ddea0b203ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374736534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.374736534
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1252859039
Short name T742
Test name
Test status
Simulation time 32639425 ps
CPU time 0.68 seconds
Started Mar 26 12:24:33 PM PDT 24
Finished Mar 26 12:24:33 PM PDT 24
Peak memory 196320 kb
Host smart-d3d30527-fefe-4638-9ac8-34b7b3c310f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252859039 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1252859039
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.541570849
Short name T768
Test name
Test status
Simulation time 54720974 ps
CPU time 0.56 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:49 PM PDT 24
Peak memory 192776 kb
Host smart-84473e94-8b33-4f46-b156-3aad75aae29a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541570849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.541570849
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.825467694
Short name T805
Test name
Test status
Simulation time 28628981 ps
CPU time 0.6 seconds
Started Mar 26 12:27:10 PM PDT 24
Finished Mar 26 12:27:10 PM PDT 24
Peak memory 193224 kb
Host smart-6f5193c6-ead5-4f83-8bda-63b50eb99bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825467694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.825467694
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3271087327
Short name T739
Test name
Test status
Simulation time 143826553 ps
CPU time 1.57 seconds
Started Mar 26 12:23:28 PM PDT 24
Finished Mar 26 12:23:30 PM PDT 24
Peak memory 197620 kb
Host smart-caa555cf-1d19-4d40-9067-965415fca7c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271087327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3271087327
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1020134999
Short name T809
Test name
Test status
Simulation time 117556053 ps
CPU time 1.49 seconds
Started Mar 26 12:24:44 PM PDT 24
Finished Mar 26 12:24:46 PM PDT 24
Peak memory 197612 kb
Host smart-3d21b094-d99a-4c05-8e8c-9f6dff504742
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020134999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1020134999
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.958743140
Short name T832
Test name
Test status
Simulation time 36115544 ps
CPU time 0.87 seconds
Started Mar 26 12:23:30 PM PDT 24
Finished Mar 26 12:23:31 PM PDT 24
Peak memory 195688 kb
Host smart-70b9441c-aac3-45d7-8b89-1c42e534c60f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958743140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.958743140
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1729554515
Short name T831
Test name
Test status
Simulation time 90609717 ps
CPU time 1.5 seconds
Started Mar 26 12:25:07 PM PDT 24
Finished Mar 26 12:25:10 PM PDT 24
Peak memory 196084 kb
Host smart-17af7bc3-869b-48b9-a52a-74e1e8323f4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729554515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1729554515
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2886203417
Short name T95
Test name
Test status
Simulation time 21634027 ps
CPU time 0.72 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:23 PM PDT 24
Peak memory 192776 kb
Host smart-d26c00e1-9f67-4478-8aa2-7ca8582c46e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886203417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2886203417
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.969281844
Short name T822
Test name
Test status
Simulation time 35043699 ps
CPU time 0.86 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:49 PM PDT 24
Peak memory 197460 kb
Host smart-b2c97fbd-53ff-4ae6-b6e7-08ec44e0aec5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969281844 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.969281844
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1872536448
Short name T798
Test name
Test status
Simulation time 29249981 ps
CPU time 0.6 seconds
Started Mar 26 12:24:40 PM PDT 24
Finished Mar 26 12:24:41 PM PDT 24
Peak memory 193928 kb
Host smart-0bd42aa7-f074-4e35-81d2-736424b65b81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872536448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1872536448
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1479249845
Short name T782
Test name
Test status
Simulation time 61565410 ps
CPU time 0.58 seconds
Started Mar 26 12:25:45 PM PDT 24
Finished Mar 26 12:25:46 PM PDT 24
Peak memory 193168 kb
Host smart-1f7a573a-f030-46a9-9d0a-ad183e173ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479249845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1479249845
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3986874224
Short name T751
Test name
Test status
Simulation time 18070059 ps
CPU time 0.65 seconds
Started Mar 26 12:24:31 PM PDT 24
Finished Mar 26 12:24:32 PM PDT 24
Peak memory 195068 kb
Host smart-33d25e02-5ded-41ca-b64f-cce5a8e5f720
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986874224 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3986874224
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1432620719
Short name T728
Test name
Test status
Simulation time 258816680 ps
CPU time 2.53 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:51 PM PDT 24
Peak memory 197572 kb
Host smart-34a9dd21-52a9-4059-a583-be38ac568489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432620719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1432620719
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1311830644
Short name T45
Test name
Test status
Simulation time 41742325 ps
CPU time 0.92 seconds
Started Mar 26 12:23:56 PM PDT 24
Finished Mar 26 12:23:57 PM PDT 24
Peak memory 197108 kb
Host smart-7f4dd5d0-58d0-41d3-b321-587626bd9a44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311830644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1311830644
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2234617468
Short name T771
Test name
Test status
Simulation time 128245361 ps
CPU time 0.96 seconds
Started Mar 26 12:25:55 PM PDT 24
Finished Mar 26 12:25:56 PM PDT 24
Peak memory 197480 kb
Host smart-2304eb91-2774-4042-9711-ea3adc7d34ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234617468 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2234617468
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2807102614
Short name T814
Test name
Test status
Simulation time 13496526 ps
CPU time 0.62 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 195092 kb
Host smart-d7c0f22d-3c5f-4297-86e4-cbc2c371a6e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807102614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2807102614
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2573243308
Short name T812
Test name
Test status
Simulation time 15566894 ps
CPU time 0.63 seconds
Started Mar 26 12:24:08 PM PDT 24
Finished Mar 26 12:24:09 PM PDT 24
Peak memory 193296 kb
Host smart-b5fef841-b228-43ae-a96d-90e9d8e4e3f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573243308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2573243308
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3357890524
Short name T80
Test name
Test status
Simulation time 40908120 ps
CPU time 0.68 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 193724 kb
Host smart-1515f6b0-6c46-41a5-86f2-498fabab5d42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357890524 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3357890524
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3056076676
Short name T733
Test name
Test status
Simulation time 186315253 ps
CPU time 1.78 seconds
Started Mar 26 12:24:07 PM PDT 24
Finished Mar 26 12:24:09 PM PDT 24
Peak memory 197600 kb
Host smart-39b3316b-4aa2-4827-877b-17203484bd79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056076676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3056076676
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2641761083
Short name T37
Test name
Test status
Simulation time 285211540 ps
CPU time 1.12 seconds
Started Mar 26 12:26:18 PM PDT 24
Finished Mar 26 12:26:19 PM PDT 24
Peak memory 197568 kb
Host smart-f364247c-535d-427e-9384-f8466679d6a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641761083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2641761083
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.21817406
Short name T824
Test name
Test status
Simulation time 30887314 ps
CPU time 1.29 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 196956 kb
Host smart-77223982-9e63-41e1-9303-ea4da27026cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21817406 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.21817406
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.195998010
Short name T829
Test name
Test status
Simulation time 77682275 ps
CPU time 0.64 seconds
Started Mar 26 12:26:13 PM PDT 24
Finished Mar 26 12:26:15 PM PDT 24
Peak memory 194244 kb
Host smart-e306a97c-b5c4-421b-b90c-0ab7c8bf7bf6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195998010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.195998010
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1246010983
Short name T790
Test name
Test status
Simulation time 15190288 ps
CPU time 0.58 seconds
Started Mar 26 12:24:33 PM PDT 24
Finished Mar 26 12:24:33 PM PDT 24
Peak memory 193896 kb
Host smart-6cdc51f4-cadc-42c1-873f-489d7693a41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246010983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1246010983
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.245797801
Short name T757
Test name
Test status
Simulation time 86721923 ps
CPU time 0.71 seconds
Started Mar 26 12:24:20 PM PDT 24
Finished Mar 26 12:24:21 PM PDT 24
Peak memory 194672 kb
Host smart-0418549a-a0b3-428f-ba8e-77735f85d644
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245797801 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.245797801
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.536579614
Short name T737
Test name
Test status
Simulation time 363261504 ps
CPU time 3.31 seconds
Started Mar 26 12:24:24 PM PDT 24
Finished Mar 26 12:24:27 PM PDT 24
Peak memory 197580 kb
Host smart-7d1ccf2b-1722-4c6a-87f2-cfe8c5564d25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536579614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.536579614
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3240500989
Short name T44
Test name
Test status
Simulation time 754175214 ps
CPU time 1.43 seconds
Started Mar 26 12:24:14 PM PDT 24
Finished Mar 26 12:24:16 PM PDT 24
Peak memory 197588 kb
Host smart-846f1a74-1929-4d26-9316-f25af9b661e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240500989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3240500989
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1311677776
Short name T775
Test name
Test status
Simulation time 84902371 ps
CPU time 0.93 seconds
Started Mar 26 12:24:24 PM PDT 24
Finished Mar 26 12:24:25 PM PDT 24
Peak memory 197520 kb
Host smart-a28bd9c1-6cfb-4abd-bc90-747cd24a2c29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311677776 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1311677776
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3784901604
Short name T85
Test name
Test status
Simulation time 21210295 ps
CPU time 0.55 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:26:57 PM PDT 24
Peak memory 192844 kb
Host smart-70032f4a-e135-431a-88ec-69fdd655cd75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784901604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3784901604
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1516615411
Short name T830
Test name
Test status
Simulation time 12480759 ps
CPU time 0.59 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:26:57 PM PDT 24
Peak memory 192880 kb
Host smart-2d82ff5c-72f3-4feb-8f46-71b1636537c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516615411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1516615411
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.186806110
Short name T96
Test name
Test status
Simulation time 16652820 ps
CPU time 0.68 seconds
Started Mar 26 12:24:42 PM PDT 24
Finished Mar 26 12:24:43 PM PDT 24
Peak memory 194596 kb
Host smart-fce9ad58-c2d9-493d-bcec-e75e28ea8149
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186806110 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.186806110
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1023959365
Short name T726
Test name
Test status
Simulation time 124944238 ps
CPU time 1.38 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:26:43 PM PDT 24
Peak memory 197528 kb
Host smart-ac383f8d-6a32-4393-8c6f-52486c08b40f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023959365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1023959365
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4230457385
Short name T730
Test name
Test status
Simulation time 55068231 ps
CPU time 0.75 seconds
Started Mar 26 12:24:33 PM PDT 24
Finished Mar 26 12:24:33 PM PDT 24
Peak memory 197072 kb
Host smart-b0e607b1-5e87-4d54-b5a4-12383ef452d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230457385 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4230457385
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2356413408
Short name T821
Test name
Test status
Simulation time 26647362 ps
CPU time 0.57 seconds
Started Mar 26 12:27:20 PM PDT 24
Finished Mar 26 12:27:21 PM PDT 24
Peak memory 193456 kb
Host smart-a67fd264-3197-426a-be43-d431fb5008ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356413408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2356413408
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2507747877
Short name T772
Test name
Test status
Simulation time 160381850 ps
CPU time 0.61 seconds
Started Mar 26 12:24:33 PM PDT 24
Finished Mar 26 12:24:34 PM PDT 24
Peak memory 193252 kb
Host smart-87d0661c-b577-42f1-af1f-ae3cd300bb4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507747877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2507747877
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.472836485
Short name T100
Test name
Test status
Simulation time 62692646 ps
CPU time 0.68 seconds
Started Mar 26 12:24:50 PM PDT 24
Finished Mar 26 12:24:50 PM PDT 24
Peak memory 194520 kb
Host smart-9f8e2916-c4e1-4935-a469-608e45203a60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472836485 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.472836485
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1381080552
Short name T776
Test name
Test status
Simulation time 291186612 ps
CPU time 1.71 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:26:43 PM PDT 24
Peak memory 197528 kb
Host smart-0ce0c1ac-3fba-418f-9b01-cfcde80dc05b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381080552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1381080552
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2193552085
Short name T104
Test name
Test status
Simulation time 70171934 ps
CPU time 1.09 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:26:57 PM PDT 24
Peak memory 197260 kb
Host smart-43dd431d-ef1d-4b44-845d-8f2e494e18b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193552085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2193552085
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.692824729
Short name T796
Test name
Test status
Simulation time 446711917 ps
CPU time 1.82 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:26:43 PM PDT 24
Peak memory 197596 kb
Host smart-3857a646-cae2-4bdf-9dda-62e53302ab50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692824729 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.692824729
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1673107702
Short name T91
Test name
Test status
Simulation time 11815388 ps
CPU time 0.63 seconds
Started Mar 26 12:26:24 PM PDT 24
Finished Mar 26 12:26:25 PM PDT 24
Peak memory 193388 kb
Host smart-116b50a7-2741-492d-900d-a308ba9d110d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673107702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1673107702
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2710195957
Short name T729
Test name
Test status
Simulation time 14432858 ps
CPU time 0.59 seconds
Started Mar 26 12:24:33 PM PDT 24
Finished Mar 26 12:24:34 PM PDT 24
Peak memory 193892 kb
Host smart-b5a4899b-6556-405d-b45b-cb8a45ddfd26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710195957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2710195957
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.865235208
Short name T99
Test name
Test status
Simulation time 40670617 ps
CPU time 0.63 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:26:42 PM PDT 24
Peak memory 195036 kb
Host smart-de44b913-84e8-4952-8222-764d670974c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865235208 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.865235208
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2246433919
Short name T740
Test name
Test status
Simulation time 592016913 ps
CPU time 2.86 seconds
Started Mar 26 12:24:27 PM PDT 24
Finished Mar 26 12:24:31 PM PDT 24
Peak memory 197660 kb
Host smart-3736c38c-30e7-4cd7-bcb7-fa487e26f0e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246433919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2246433919
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4191527900
Short name T801
Test name
Test status
Simulation time 94187540 ps
CPU time 0.9 seconds
Started Mar 26 12:24:33 PM PDT 24
Finished Mar 26 12:24:34 PM PDT 24
Peak memory 196776 kb
Host smart-4f9631a1-7208-4221-979d-5031af7c22c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191527900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4191527900
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.481346944
Short name T723
Test name
Test status
Simulation time 33594640 ps
CPU time 0.94 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:26:57 PM PDT 24
Peak memory 196540 kb
Host smart-f1e04f4d-2741-4e52-8314-22b6accb34ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481346944 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.481346944
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.576877953
Short name T83
Test name
Test status
Simulation time 20352568 ps
CPU time 0.6 seconds
Started Mar 26 12:24:26 PM PDT 24
Finished Mar 26 12:24:27 PM PDT 24
Peak memory 195040 kb
Host smart-de5eb5ee-8692-464a-bfa6-00979c526d22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576877953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.576877953
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1548188815
Short name T800
Test name
Test status
Simulation time 42441297 ps
CPU time 0.68 seconds
Started Mar 26 12:24:26 PM PDT 24
Finished Mar 26 12:24:27 PM PDT 24
Peak memory 193360 kb
Host smart-506de45f-cf85-4295-8239-c604f98c5168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548188815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1548188815
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4235277251
Short name T98
Test name
Test status
Simulation time 49022376 ps
CPU time 0.71 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 194256 kb
Host smart-b01338c5-7651-4366-a261-1cac079b2ace
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235277251 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.4235277251
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.789157115
Short name T762
Test name
Test status
Simulation time 35401572 ps
CPU time 1.81 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:26:58 PM PDT 24
Peak memory 196772 kb
Host smart-dfe277f1-705a-46ec-85ca-77c7852bca41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789157115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.789157115
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.435343938
Short name T780
Test name
Test status
Simulation time 58796413 ps
CPU time 0.86 seconds
Started Mar 26 12:26:24 PM PDT 24
Finished Mar 26 12:26:25 PM PDT 24
Peak memory 196244 kb
Host smart-1499d65b-00f1-4719-82b2-a314dc67f228
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435343938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.435343938
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.927334893
Short name T779
Test name
Test status
Simulation time 44272941 ps
CPU time 1.05 seconds
Started Mar 26 12:24:34 PM PDT 24
Finished Mar 26 12:24:35 PM PDT 24
Peak memory 197452 kb
Host smart-7d7c8865-0499-48be-a4e8-7963cb62ecd6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927334893 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.927334893
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4186839999
Short name T837
Test name
Test status
Simulation time 32124736 ps
CPU time 0.56 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:26:42 PM PDT 24
Peak memory 194120 kb
Host smart-14e8a8c9-2319-4463-8ddf-33c905a7bd16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186839999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4186839999
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1367728515
Short name T786
Test name
Test status
Simulation time 23945980 ps
CPU time 0.61 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:49 PM PDT 24
Peak memory 193256 kb
Host smart-2125dbc6-8af9-4fad-a18b-80ed2894883a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367728515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1367728515
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2867328909
Short name T773
Test name
Test status
Simulation time 34179483 ps
CPU time 0.78 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:26:57 PM PDT 24
Peak memory 196196 kb
Host smart-cad23ded-8485-4b45-a2c3-df9186413f9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867328909 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2867328909
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3717480792
Short name T797
Test name
Test status
Simulation time 32250339 ps
CPU time 1.57 seconds
Started Mar 26 12:26:24 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 196724 kb
Host smart-6e95c548-d842-4aaa-9d10-191b2e070d3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717480792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3717480792
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1368867146
Short name T36
Test name
Test status
Simulation time 71931439 ps
CPU time 0.83 seconds
Started Mar 26 12:24:48 PM PDT 24
Finished Mar 26 12:24:49 PM PDT 24
Peak memory 196576 kb
Host smart-8d28653e-8ef5-4e6f-b561-5b94751b553e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368867146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1368867146
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3408838914
Short name T741
Test name
Test status
Simulation time 20737090 ps
CPU time 0.79 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 197416 kb
Host smart-ec9ad169-ebdd-4107-8488-1c5e976c199d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408838914 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3408838914
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3406566529
Short name T94
Test name
Test status
Simulation time 42102156 ps
CPU time 0.63 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 192840 kb
Host smart-da73b8ba-5e45-4b1f-9df5-186148b0ed11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406566529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3406566529
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1331568848
Short name T720
Test name
Test status
Simulation time 12463824 ps
CPU time 0.55 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:47 PM PDT 24
Peak memory 193816 kb
Host smart-1c434a03-181f-489d-b182-bcbbf31aaefb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331568848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1331568848
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1966905855
Short name T842
Test name
Test status
Simulation time 45805733 ps
CPU time 0.62 seconds
Started Mar 26 12:24:45 PM PDT 24
Finished Mar 26 12:24:45 PM PDT 24
Peak memory 194296 kb
Host smart-2aca9967-f3d6-4fd1-bfa4-54f6a0f7b8cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966905855 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1966905855
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.189273661
Short name T808
Test name
Test status
Simulation time 52702272 ps
CPU time 1.17 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 197568 kb
Host smart-7a3f66d2-f5f4-43d0-b674-221e7b7c3729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189273661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.189273661
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2369013382
Short name T793
Test name
Test status
Simulation time 43400359 ps
CPU time 0.81 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:47 PM PDT 24
Peak memory 196512 kb
Host smart-0b8cf020-0ccf-4a81-804f-6338d014b646
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369013382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2369013382
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2158522436
Short name T746
Test name
Test status
Simulation time 84625651 ps
CPU time 0.67 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 197304 kb
Host smart-3294d147-ab37-4613-b1f9-9d2aae69ede9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158522436 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2158522436
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1846789424
Short name T838
Test name
Test status
Simulation time 35994770 ps
CPU time 0.58 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:36 PM PDT 24
Peak memory 192064 kb
Host smart-d3b09b06-75a4-4b6f-9ac5-cc6c49e4c355
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846789424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1846789424
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3617791598
Short name T764
Test name
Test status
Simulation time 50355424 ps
CPU time 0.58 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 193284 kb
Host smart-16f07c90-6a4b-4370-9e56-e652b80168ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617791598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3617791598
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2067189046
Short name T781
Test name
Test status
Simulation time 111964044 ps
CPU time 0.71 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:47 PM PDT 24
Peak memory 196304 kb
Host smart-af64e09f-10e9-4744-a929-28e5f33bacd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067189046 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2067189046
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2174605516
Short name T777
Test name
Test status
Simulation time 45242988 ps
CPU time 2.2 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:26:56 PM PDT 24
Peak memory 197600 kb
Host smart-8c3f70f2-32fe-406e-9bba-35639375ac75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174605516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2174605516
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2419666438
Short name T43
Test name
Test status
Simulation time 73043409 ps
CPU time 1.25 seconds
Started Mar 26 12:24:37 PM PDT 24
Finished Mar 26 12:24:39 PM PDT 24
Peak memory 197944 kb
Host smart-d5aaea71-f661-4927-88cd-b5a168ac0603
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419666438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2419666438
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.151779179
Short name T810
Test name
Test status
Simulation time 79371462 ps
CPU time 0.71 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:47 PM PDT 24
Peak memory 197464 kb
Host smart-9c6d54a8-4492-48c6-8b7b-0a4b07da1ebb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151779179 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.151779179
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4067330703
Short name T761
Test name
Test status
Simulation time 45270203 ps
CPU time 0.63 seconds
Started Mar 26 12:24:35 PM PDT 24
Finished Mar 26 12:24:36 PM PDT 24
Peak memory 194448 kb
Host smart-7a83025e-8c0e-40ff-b8cd-61bafb871b7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067330703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4067330703
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1541194530
Short name T734
Test name
Test status
Simulation time 25188456 ps
CPU time 0.57 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:49 PM PDT 24
Peak memory 193884 kb
Host smart-cc1dace8-b411-4be7-b353-dff5e6ac948d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541194530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1541194530
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.568372718
Short name T101
Test name
Test status
Simulation time 33700132 ps
CPU time 0.85 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 195908 kb
Host smart-6f039549-89ae-414b-831f-0503232cd8a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568372718 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.568372718
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3238929215
Short name T765
Test name
Test status
Simulation time 156807295 ps
CPU time 1.8 seconds
Started Mar 26 12:26:47 PM PDT 24
Finished Mar 26 12:26:50 PM PDT 24
Peak memory 197516 kb
Host smart-e429ec10-b70d-4cbb-836e-ee59601919cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238929215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3238929215
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1045635923
Short name T770
Test name
Test status
Simulation time 301956856 ps
CPU time 1.07 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:48 PM PDT 24
Peak memory 197188 kb
Host smart-0d9ed154-a53e-4821-857c-8a4b584423d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045635923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1045635923
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3506676224
Short name T732
Test name
Test status
Simulation time 12982257 ps
CPU time 0.7 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:23 PM PDT 24
Peak memory 192556 kb
Host smart-ba101770-5780-4780-8a83-da64b382e6a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506676224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3506676224
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3420181085
Short name T93
Test name
Test status
Simulation time 116835674 ps
CPU time 1.48 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:26 PM PDT 24
Peak memory 197524 kb
Host smart-afd2ba3a-dbd2-410b-b022-407b79bbf697
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420181085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3420181085
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1664308098
Short name T828
Test name
Test status
Simulation time 69610399 ps
CPU time 0.69 seconds
Started Mar 26 12:25:07 PM PDT 24
Finished Mar 26 12:25:09 PM PDT 24
Peak memory 193132 kb
Host smart-126c5753-67c0-49ec-88f7-adde0034441b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664308098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1664308098
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.504985892
Short name T804
Test name
Test status
Simulation time 13500547 ps
CPU time 0.62 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:25 PM PDT 24
Peak memory 195952 kb
Host smart-c5b2f4fb-e8c4-46b1-afff-00de1bf2fa76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504985892 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.504985892
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.12788529
Short name T90
Test name
Test status
Simulation time 49949911 ps
CPU time 0.67 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:23 PM PDT 24
Peak memory 192976 kb
Host smart-b3a51d95-b358-45e1-b79c-11738b8cbc45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12788529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_c
sr_rw.12788529
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3941911892
Short name T738
Test name
Test status
Simulation time 30070646 ps
CPU time 0.57 seconds
Started Mar 26 12:25:25 PM PDT 24
Finished Mar 26 12:25:26 PM PDT 24
Peak memory 193096 kb
Host smart-b6cc74db-46ca-4e56-9737-7875b1267de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941911892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3941911892
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3133341591
Short name T76
Test name
Test status
Simulation time 32810273 ps
CPU time 0.64 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:26 PM PDT 24
Peak memory 195040 kb
Host smart-ccb1a0d6-22fa-4b75-9a0b-e3481ab7a6ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133341591 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3133341591
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.596870864
Short name T735
Test name
Test status
Simulation time 223880699 ps
CPU time 2.37 seconds
Started Mar 26 12:25:08 PM PDT 24
Finished Mar 26 12:25:11 PM PDT 24
Peak memory 196352 kb
Host smart-ed37e7d0-e664-4241-8583-e5d707bd17db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596870864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.596870864
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3464517367
Short name T35
Test name
Test status
Simulation time 384495267 ps
CPU time 0.94 seconds
Started Mar 26 12:25:38 PM PDT 24
Finished Mar 26 12:25:39 PM PDT 24
Peak memory 197312 kb
Host smart-04b1294c-1a87-46d2-b0cb-c4653902c82e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464517367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3464517367
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.734508367
Short name T816
Test name
Test status
Simulation time 32433383 ps
CPU time 0.55 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:49 PM PDT 24
Peak memory 193208 kb
Host smart-9771efc1-3d51-4799-8bb0-c4dfd7519d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734508367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.734508367
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.405249054
Short name T725
Test name
Test status
Simulation time 18435162 ps
CPU time 0.59 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:47 PM PDT 24
Peak memory 193148 kb
Host smart-fce12289-121d-4647-83b2-617bf574ef59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405249054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.405249054
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1257169645
Short name T719
Test name
Test status
Simulation time 87879658 ps
CPU time 0.65 seconds
Started Mar 26 12:26:29 PM PDT 24
Finished Mar 26 12:26:31 PM PDT 24
Peak memory 192452 kb
Host smart-366e75b1-6887-41d1-b989-4cc6c0e5e54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257169645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1257169645
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1064146983
Short name T840
Test name
Test status
Simulation time 108156096 ps
CPU time 0.65 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 192920 kb
Host smart-a1f0d236-e609-4b2b-b067-f638f15262e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064146983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1064146983
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1495503596
Short name T806
Test name
Test status
Simulation time 46605762 ps
CPU time 0.56 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:47 PM PDT 24
Peak memory 193076 kb
Host smart-9caf7562-5756-468f-ae3a-79af4bda085d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495503596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1495503596
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1589528148
Short name T745
Test name
Test status
Simulation time 23901235 ps
CPU time 0.6 seconds
Started Mar 26 12:26:32 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 192532 kb
Host smart-4305ff4e-6157-48fb-b5eb-62a6c06aa1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589528148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1589528148
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.441480196
Short name T753
Test name
Test status
Simulation time 13684626 ps
CPU time 0.56 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:47 PM PDT 24
Peak memory 193864 kb
Host smart-062f9106-b058-4f96-9a39-591ce7bf7478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441480196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.441480196
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1398073440
Short name T758
Test name
Test status
Simulation time 17244417 ps
CPU time 0.63 seconds
Started Mar 26 12:24:52 PM PDT 24
Finished Mar 26 12:24:53 PM PDT 24
Peak memory 193296 kb
Host smart-8456d998-74e5-4a20-bd80-2a75900aed03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398073440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1398073440
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.165020358
Short name T767
Test name
Test status
Simulation time 51461518 ps
CPU time 0.6 seconds
Started Mar 26 12:24:49 PM PDT 24
Finished Mar 26 12:24:50 PM PDT 24
Peak memory 193264 kb
Host smart-4e8f3d49-1b2c-4622-b6b1-f6e341cf91d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165020358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.165020358
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.950566778
Short name T722
Test name
Test status
Simulation time 33678511 ps
CPU time 0.59 seconds
Started Mar 26 12:24:57 PM PDT 24
Finished Mar 26 12:24:58 PM PDT 24
Peak memory 193576 kb
Host smart-c38709a2-f49b-49be-b55f-abbecc606b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950566778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.950566778
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3689376631
Short name T88
Test name
Test status
Simulation time 21093387 ps
CPU time 0.79 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:26:23 PM PDT 24
Peak memory 193840 kb
Host smart-4331846d-98ac-4512-8e8e-2410ed1228f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689376631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3689376631
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2302277991
Short name T815
Test name
Test status
Simulation time 262479081 ps
CPU time 2.4 seconds
Started Mar 26 12:25:28 PM PDT 24
Finished Mar 26 12:25:31 PM PDT 24
Peak memory 196616 kb
Host smart-86dc0740-8899-4098-9bc5-cbd783775c68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302277991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2302277991
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3357682699
Short name T102
Test name
Test status
Simulation time 18543685 ps
CPU time 0.59 seconds
Started Mar 26 12:26:23 PM PDT 24
Finished Mar 26 12:26:23 PM PDT 24
Peak memory 193968 kb
Host smart-c4abf5c6-a759-4160-8f93-440d406bbbb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357682699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3357682699
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2268994433
Short name T802
Test name
Test status
Simulation time 33656158 ps
CPU time 0.92 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:25 PM PDT 24
Peak memory 196444 kb
Host smart-57282fdf-af33-4bef-8ac8-a14d62fa6803
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268994433 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2268994433
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.364609468
Short name T92
Test name
Test status
Simulation time 22742705 ps
CPU time 0.63 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:26 PM PDT 24
Peak memory 194312 kb
Host smart-3a664922-1e4a-4e3f-ad6f-417b5099c591
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364609468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.364609468
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2332585987
Short name T784
Test name
Test status
Simulation time 13412110 ps
CPU time 0.59 seconds
Started Mar 26 12:23:56 PM PDT 24
Finished Mar 26 12:23:56 PM PDT 24
Peak memory 193324 kb
Host smart-76084d07-4608-4bf7-903b-a31e51f97b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332585987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2332585987
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3853462087
Short name T97
Test name
Test status
Simulation time 20198479 ps
CPU time 0.79 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:25 PM PDT 24
Peak memory 195768 kb
Host smart-8030e63b-72f1-43ff-aacb-4f6e7fe69000
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853462087 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3853462087
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2017720356
Short name T794
Test name
Test status
Simulation time 84508005 ps
CPU time 1.89 seconds
Started Mar 26 12:23:49 PM PDT 24
Finished Mar 26 12:23:51 PM PDT 24
Peak memory 197660 kb
Host smart-2be975a7-b75a-4035-98fa-8617ba32e284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017720356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2017720356
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.859113867
Short name T819
Test name
Test status
Simulation time 12918187 ps
CPU time 0.63 seconds
Started Mar 26 12:25:02 PM PDT 24
Finished Mar 26 12:25:03 PM PDT 24
Peak memory 193216 kb
Host smart-9fcca303-7e98-41ff-beec-a1e6f4c4a6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859113867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.859113867
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3772672158
Short name T843
Test name
Test status
Simulation time 14827577 ps
CPU time 0.6 seconds
Started Mar 26 12:24:48 PM PDT 24
Finished Mar 26 12:24:49 PM PDT 24
Peak memory 193240 kb
Host smart-5231b91f-68e2-40d2-ad0f-a0ab9fe493b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772672158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3772672158
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1071379473
Short name T743
Test name
Test status
Simulation time 14712686 ps
CPU time 0.56 seconds
Started Mar 26 12:24:46 PM PDT 24
Finished Mar 26 12:24:46 PM PDT 24
Peak memory 193584 kb
Host smart-52252f30-7c72-403a-b4ef-6c9e5dd3fb48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071379473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1071379473
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1919799869
Short name T827
Test name
Test status
Simulation time 13043790 ps
CPU time 0.6 seconds
Started Mar 26 12:24:49 PM PDT 24
Finished Mar 26 12:24:50 PM PDT 24
Peak memory 193300 kb
Host smart-d4666e0c-c4a5-43a0-ada7-aaf140338e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919799869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1919799869
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1213173031
Short name T835
Test name
Test status
Simulation time 26419052 ps
CPU time 0.63 seconds
Started Mar 26 12:26:02 PM PDT 24
Finished Mar 26 12:26:02 PM PDT 24
Peak memory 193844 kb
Host smart-b043c4f1-14b4-45c2-9c91-5d171eaa9a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213173031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1213173031
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.4120333149
Short name T789
Test name
Test status
Simulation time 49801181 ps
CPU time 0.64 seconds
Started Mar 26 12:26:02 PM PDT 24
Finished Mar 26 12:26:02 PM PDT 24
Peak memory 193876 kb
Host smart-9a4d54b3-1546-4fee-909c-8223feeed465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120333149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.4120333149
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3181649129
Short name T811
Test name
Test status
Simulation time 15476550 ps
CPU time 0.57 seconds
Started Mar 26 12:24:54 PM PDT 24
Finished Mar 26 12:24:55 PM PDT 24
Peak memory 193308 kb
Host smart-052a6496-c89a-48e2-b363-9871d8869531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181649129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3181649129
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2956723502
Short name T792
Test name
Test status
Simulation time 42201316 ps
CPU time 0.61 seconds
Started Mar 26 12:24:56 PM PDT 24
Finished Mar 26 12:24:57 PM PDT 24
Peak memory 193644 kb
Host smart-a5cc432c-191e-4d50-b377-20e883d7ee9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956723502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2956723502
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1263480600
Short name T791
Test name
Test status
Simulation time 16948215 ps
CPU time 0.6 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:26:12 PM PDT 24
Peak memory 193688 kb
Host smart-671d2719-3a83-486f-910b-dd4f955029a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263480600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1263480600
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1416457901
Short name T752
Test name
Test status
Simulation time 41220200 ps
CPU time 0.61 seconds
Started Mar 26 12:24:54 PM PDT 24
Finished Mar 26 12:24:55 PM PDT 24
Peak memory 193288 kb
Host smart-e9d2ac76-4c65-4df1-a0a6-5141e1c73063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416457901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1416457901
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2034477704
Short name T81
Test name
Test status
Simulation time 31509213 ps
CPU time 0.9 seconds
Started Mar 26 12:25:38 PM PDT 24
Finished Mar 26 12:25:39 PM PDT 24
Peak memory 196280 kb
Host smart-d72bbbc0-1a0a-48eb-b63b-c93e69547d92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034477704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2034477704
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.617659579
Short name T795
Test name
Test status
Simulation time 38400436 ps
CPU time 1.32 seconds
Started Mar 26 12:25:37 PM PDT 24
Finished Mar 26 12:25:39 PM PDT 24
Peak memory 196228 kb
Host smart-691bde97-7052-481a-aeb2-0383070fef7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617659579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.617659579
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3949602410
Short name T84
Test name
Test status
Simulation time 40622648 ps
CPU time 0.62 seconds
Started Mar 26 12:25:45 PM PDT 24
Finished Mar 26 12:25:46 PM PDT 24
Peak memory 194280 kb
Host smart-f1a756c2-87b9-4816-8663-43c53ac7567b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949602410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3949602410
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3541012729
Short name T820
Test name
Test status
Simulation time 107388822 ps
CPU time 0.87 seconds
Started Mar 26 12:25:37 PM PDT 24
Finished Mar 26 12:25:38 PM PDT 24
Peak memory 197436 kb
Host smart-d4864693-1e46-4f89-8f38-5a26b0c9eb40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541012729 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3541012729
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1754438752
Short name T89
Test name
Test status
Simulation time 47040968 ps
CPU time 0.62 seconds
Started Mar 26 12:25:44 PM PDT 24
Finished Mar 26 12:25:45 PM PDT 24
Peak memory 195116 kb
Host smart-89209f1e-aa74-40b7-b83d-eeb128cbaf93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754438752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1754438752
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4141496258
Short name T759
Test name
Test status
Simulation time 17536604 ps
CPU time 0.61 seconds
Started Mar 26 12:25:38 PM PDT 24
Finished Mar 26 12:25:38 PM PDT 24
Peak memory 193160 kb
Host smart-05cf92d5-c394-4efb-bcab-12548fe04fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141496258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4141496258
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2335094039
Short name T833
Test name
Test status
Simulation time 54299294 ps
CPU time 0.85 seconds
Started Mar 26 12:26:24 PM PDT 24
Finished Mar 26 12:26:25 PM PDT 24
Peak memory 196592 kb
Host smart-1e6723e7-4638-4a25-8c83-fa99df767406
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335094039 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2335094039
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2398407946
Short name T778
Test name
Test status
Simulation time 55189685 ps
CPU time 1.36 seconds
Started Mar 26 12:25:29 PM PDT 24
Finished Mar 26 12:25:30 PM PDT 24
Peak memory 197552 kb
Host smart-cc3a1fb9-e8f8-4fe8-bcbe-a4df931e0ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398407946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2398407946
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3040417965
Short name T836
Test name
Test status
Simulation time 303309559 ps
CPU time 0.87 seconds
Started Mar 26 12:25:11 PM PDT 24
Finished Mar 26 12:25:13 PM PDT 24
Peak memory 195448 kb
Host smart-cb9f4a14-8840-4795-8ebe-098fbc777502
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040417965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3040417965
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1245413605
Short name T839
Test name
Test status
Simulation time 46100922 ps
CPU time 0.59 seconds
Started Mar 26 12:24:49 PM PDT 24
Finished Mar 26 12:24:50 PM PDT 24
Peak memory 193252 kb
Host smart-0a0809ef-9452-409e-a291-a51d40d8dea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245413605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1245413605
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1119903269
Short name T774
Test name
Test status
Simulation time 25696385 ps
CPU time 0.59 seconds
Started Mar 26 12:26:28 PM PDT 24
Finished Mar 26 12:26:29 PM PDT 24
Peak memory 193268 kb
Host smart-d9d4a7cf-98ce-4494-a589-8ec5e4fb4e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119903269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1119903269
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3723779520
Short name T749
Test name
Test status
Simulation time 56107502 ps
CPU time 0.61 seconds
Started Mar 26 12:24:49 PM PDT 24
Finished Mar 26 12:24:50 PM PDT 24
Peak memory 193324 kb
Host smart-74f9299f-9484-4e96-b08c-5d5efc353acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723779520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3723779520
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3584656817
Short name T825
Test name
Test status
Simulation time 52223408 ps
CPU time 0.61 seconds
Started Mar 26 12:25:56 PM PDT 24
Finished Mar 26 12:25:57 PM PDT 24
Peak memory 194324 kb
Host smart-7d917be7-8420-46ab-a2e7-a2082fc19c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584656817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3584656817
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1890773873
Short name T766
Test name
Test status
Simulation time 36492846 ps
CPU time 0.63 seconds
Started Mar 26 12:24:59 PM PDT 24
Finished Mar 26 12:25:00 PM PDT 24
Peak memory 193684 kb
Host smart-186a6d76-36ba-4967-80ff-9d11e0c4a49a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890773873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1890773873
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3676130169
Short name T813
Test name
Test status
Simulation time 12490019 ps
CPU time 0.59 seconds
Started Mar 26 12:25:57 PM PDT 24
Finished Mar 26 12:25:58 PM PDT 24
Peak memory 193352 kb
Host smart-1a769776-dd50-410b-a686-d67747e457b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676130169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3676130169
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1309029492
Short name T823
Test name
Test status
Simulation time 25543919 ps
CPU time 0.58 seconds
Started Mar 26 12:25:00 PM PDT 24
Finished Mar 26 12:25:01 PM PDT 24
Peak memory 193244 kb
Host smart-2aeb9a6b-89c4-44b6-b19c-3662c738c7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309029492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1309029492
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2552572985
Short name T724
Test name
Test status
Simulation time 14635270 ps
CPU time 0.62 seconds
Started Mar 26 12:24:47 PM PDT 24
Finished Mar 26 12:24:48 PM PDT 24
Peak memory 193688 kb
Host smart-9cf9437b-874e-4abe-9dd6-937caa021652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552572985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2552572985
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3676334649
Short name T731
Test name
Test status
Simulation time 15642548 ps
CPU time 0.63 seconds
Started Mar 26 12:26:02 PM PDT 24
Finished Mar 26 12:26:02 PM PDT 24
Peak memory 193272 kb
Host smart-3171d292-55bc-4166-9b32-dc86316285f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676334649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3676334649
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2455616283
Short name T807
Test name
Test status
Simulation time 47126489 ps
CPU time 0.6 seconds
Started Mar 26 12:24:55 PM PDT 24
Finished Mar 26 12:24:57 PM PDT 24
Peak memory 193452 kb
Host smart-b7f87a29-f7a8-4998-b347-3e35911bf539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455616283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2455616283
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2086504948
Short name T721
Test name
Test status
Simulation time 30387921 ps
CPU time 0.89 seconds
Started Mar 26 12:25:11 PM PDT 24
Finished Mar 26 12:25:13 PM PDT 24
Peak memory 196252 kb
Host smart-e042a75e-cdc9-4302-af49-969963389acc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086504948 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2086504948
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2297111643
Short name T744
Test name
Test status
Simulation time 41522102 ps
CPU time 0.6 seconds
Started Mar 26 12:23:46 PM PDT 24
Finished Mar 26 12:23:48 PM PDT 24
Peak memory 194808 kb
Host smart-3285da05-7356-498d-a56f-eebff50cc5a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297111643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2297111643
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2368390332
Short name T788
Test name
Test status
Simulation time 25294108 ps
CPU time 0.61 seconds
Started Mar 26 12:24:16 PM PDT 24
Finished Mar 26 12:24:17 PM PDT 24
Peak memory 193228 kb
Host smart-8deabd31-cc56-4b98-8b0f-3ab12e9b248f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368390332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2368390332
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1806199214
Short name T834
Test name
Test status
Simulation time 19428203 ps
CPU time 0.67 seconds
Started Mar 26 12:25:37 PM PDT 24
Finished Mar 26 12:25:38 PM PDT 24
Peak memory 194128 kb
Host smart-d5db468b-a954-44e9-9b09-dccafa43206b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806199214 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1806199214
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3202851988
Short name T763
Test name
Test status
Simulation time 126002912 ps
CPU time 2.77 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:26:43 PM PDT 24
Peak memory 197932 kb
Host smart-78c6cf92-2b20-44da-8433-cb56eed4ddee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202851988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3202851988
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2111101250
Short name T103
Test name
Test status
Simulation time 120177828 ps
CPU time 1.61 seconds
Started Mar 26 12:23:49 PM PDT 24
Finished Mar 26 12:23:52 PM PDT 24
Peak memory 197616 kb
Host smart-f2e412d3-8b97-4b7c-ab77-e165cec15982
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111101250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2111101250
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.449481152
Short name T756
Test name
Test status
Simulation time 113508694 ps
CPU time 0.91 seconds
Started Mar 26 12:26:19 PM PDT 24
Finished Mar 26 12:26:20 PM PDT 24
Peak memory 197488 kb
Host smart-f59bc299-f107-4b3a-84bc-1fc8129ada5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449481152 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.449481152
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.510846641
Short name T783
Test name
Test status
Simulation time 39478858 ps
CPU time 0.59 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:26:54 PM PDT 24
Peak memory 194232 kb
Host smart-1943dc67-4f61-45c0-bd03-6151ef6baac0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510846641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.510846641
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3817456181
Short name T769
Test name
Test status
Simulation time 14827200 ps
CPU time 0.66 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 192772 kb
Host smart-9b44386e-1a72-4aa1-9a50-953aa006b3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817456181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3817456181
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.630908003
Short name T826
Test name
Test status
Simulation time 44419074 ps
CPU time 0.76 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 196092 kb
Host smart-29b17346-cae7-487d-9932-6fa5afe97b33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630908003 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.630908003
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2910079777
Short name T748
Test name
Test status
Simulation time 54962024 ps
CPU time 1.3 seconds
Started Mar 26 12:24:07 PM PDT 24
Finished Mar 26 12:24:08 PM PDT 24
Peak memory 197628 kb
Host smart-58272341-ecdc-411b-b6a6-b32a868ae3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910079777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2910079777
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.508369461
Short name T755
Test name
Test status
Simulation time 347650159 ps
CPU time 0.92 seconds
Started Mar 26 12:25:57 PM PDT 24
Finished Mar 26 12:25:58 PM PDT 24
Peak memory 196532 kb
Host smart-3298cf4b-7566-420a-9608-16d642170e6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508369461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.508369461
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4095276430
Short name T747
Test name
Test status
Simulation time 43844523 ps
CPU time 1.28 seconds
Started Mar 26 12:24:19 PM PDT 24
Finished Mar 26 12:24:20 PM PDT 24
Peak memory 197592 kb
Host smart-8e506010-758e-4549-a2f7-c06463b21ef3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095276430 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4095276430
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2156324810
Short name T87
Test name
Test status
Simulation time 198693548 ps
CPU time 0.57 seconds
Started Mar 26 12:25:37 PM PDT 24
Finished Mar 26 12:25:38 PM PDT 24
Peak memory 192032 kb
Host smart-19fefab6-20d4-4984-a7d1-7b39ecad5fc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156324810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2156324810
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2672875926
Short name T750
Test name
Test status
Simulation time 14059446 ps
CPU time 0.6 seconds
Started Mar 26 12:24:16 PM PDT 24
Finished Mar 26 12:24:17 PM PDT 24
Peak memory 193184 kb
Host smart-7a5c6d98-6ae0-48d7-b9fc-4a63580b9c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672875926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2672875926
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4231701953
Short name T818
Test name
Test status
Simulation time 52078732 ps
CPU time 0.65 seconds
Started Mar 26 12:24:10 PM PDT 24
Finished Mar 26 12:24:11 PM PDT 24
Peak memory 194316 kb
Host smart-2cf3e619-a337-49a6-9f16-66a928fc0c5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231701953 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.4231701953
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2345181114
Short name T785
Test name
Test status
Simulation time 439491661 ps
CPU time 2.2 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:26:56 PM PDT 24
Peak memory 197552 kb
Host smart-1f7b7e71-38e3-4a8f-9e99-a700ec9f6cea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345181114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2345181114
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.485587687
Short name T47
Test name
Test status
Simulation time 74844468 ps
CPU time 0.86 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 197196 kb
Host smart-9f2ac658-c0bc-4b61-854d-9286506064e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485587687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.485587687
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3068015499
Short name T841
Test name
Test status
Simulation time 174688775 ps
CPU time 1.35 seconds
Started Mar 26 12:24:19 PM PDT 24
Finished Mar 26 12:24:20 PM PDT 24
Peak memory 197648 kb
Host smart-a0ff0ac6-ce51-41c6-ac70-8b2735a05df1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068015499 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3068015499
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3203781130
Short name T803
Test name
Test status
Simulation time 30684568 ps
CPU time 0.56 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 193572 kb
Host smart-e41569c8-33f0-4223-8e6d-9c56c622bab9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203781130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3203781130
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.672262344
Short name T727
Test name
Test status
Simulation time 32569912 ps
CPU time 0.62 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 193928 kb
Host smart-980c0b8c-f2f8-48e5-8aa3-71ac155f2951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672262344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.672262344
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3800559002
Short name T78
Test name
Test status
Simulation time 14746440 ps
CPU time 0.64 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 193532 kb
Host smart-5d2f9721-9a9c-419f-bd2a-871b7b9ac333
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800559002 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3800559002
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2812166225
Short name T760
Test name
Test status
Simulation time 38783031 ps
CPU time 1.04 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 197200 kb
Host smart-0a82cc86-ca46-4efd-89a4-49b88a84c9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812166225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2812166225
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3634789200
Short name T46
Test name
Test status
Simulation time 136270237 ps
CPU time 1.04 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:33 PM PDT 24
Peak memory 197592 kb
Host smart-69cbe8b9-19ff-4930-ae58-8a4eec33dc4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634789200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3634789200
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3606345052
Short name T787
Test name
Test status
Simulation time 81890168 ps
CPU time 0.75 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 196636 kb
Host smart-df03ef17-0dee-45ee-95fa-f6d39ce3afb0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606345052 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3606345052
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3479941727
Short name T82
Test name
Test status
Simulation time 43682547 ps
CPU time 0.58 seconds
Started Mar 26 12:25:55 PM PDT 24
Finished Mar 26 12:25:55 PM PDT 24
Peak memory 194796 kb
Host smart-2ca6ac3f-1901-4f99-9ebd-7b226bc92fac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479941727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3479941727
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2731409096
Short name T799
Test name
Test status
Simulation time 65189804 ps
CPU time 0.59 seconds
Started Mar 26 12:25:55 PM PDT 24
Finished Mar 26 12:25:56 PM PDT 24
Peak memory 193284 kb
Host smart-0fbdd663-ae27-48c8-9f77-8d59c6a55efa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731409096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2731409096
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2162191780
Short name T754
Test name
Test status
Simulation time 12468009 ps
CPU time 0.61 seconds
Started Mar 26 12:25:54 PM PDT 24
Finished Mar 26 12:25:55 PM PDT 24
Peak memory 194500 kb
Host smart-bd2a5cb1-fede-40e3-9b0f-0ba0479b7006
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162191780 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2162191780
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2528739099
Short name T736
Test name
Test status
Simulation time 251677201 ps
CPU time 1.37 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:26:38 PM PDT 24
Peak memory 196832 kb
Host smart-a40f4f26-9a73-4a50-9e9f-ac143576e396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528739099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2528739099
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.121345685
Short name T42
Test name
Test status
Simulation time 230046428 ps
CPU time 1.37 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 197564 kb
Host smart-51c003f9-b3c7-4ca5-8af3-a8779e7ba4bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121345685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.121345685
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3590146359
Short name T388
Test name
Test status
Simulation time 12216719 ps
CPU time 0.56 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 193752 kb
Host smart-1e60451a-b7ca-46e0-b944-51ca1e773a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590146359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3590146359
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3810070022
Short name T454
Test name
Test status
Simulation time 26846706 ps
CPU time 0.77 seconds
Started Mar 26 12:29:23 PM PDT 24
Finished Mar 26 12:29:24 PM PDT 24
Peak memory 194828 kb
Host smart-fb096322-30d6-4884-9b54-9d61d2a3e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810070022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3810070022
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2637053368
Short name T394
Test name
Test status
Simulation time 3417375227 ps
CPU time 21.53 seconds
Started Mar 26 12:29:23 PM PDT 24
Finished Mar 26 12:29:45 PM PDT 24
Peak memory 196740 kb
Host smart-cf2ad218-b0e8-4952-85bb-92581551fb98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637053368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2637053368
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1274536112
Short name T687
Test name
Test status
Simulation time 194108689 ps
CPU time 0.8 seconds
Started Mar 26 12:29:22 PM PDT 24
Finished Mar 26 12:29:23 PM PDT 24
Peak memory 196840 kb
Host smart-be77a88b-9dc7-4163-a124-a87d7099fc2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274536112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1274536112
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1773101597
Short name T223
Test name
Test status
Simulation time 216854962 ps
CPU time 1.35 seconds
Started Mar 26 12:29:26 PM PDT 24
Finished Mar 26 12:29:27 PM PDT 24
Peak memory 196952 kb
Host smart-e96fd571-dc38-4d94-ad74-9794f68f30a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773101597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1773101597
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3168616745
Short name T493
Test name
Test status
Simulation time 178426912 ps
CPU time 3.2 seconds
Started Mar 26 12:29:23 PM PDT 24
Finished Mar 26 12:29:26 PM PDT 24
Peak memory 197884 kb
Host smart-2ce0c723-f8d0-4484-bd54-1461b01d54e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168616745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3168616745
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.952255500
Short name T434
Test name
Test status
Simulation time 55077847 ps
CPU time 1.63 seconds
Started Mar 26 12:29:27 PM PDT 24
Finished Mar 26 12:29:29 PM PDT 24
Peak memory 196576 kb
Host smart-a261b405-d77e-476b-bbe8-dd25e5b77189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952255500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.952255500
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1610768483
Short name T573
Test name
Test status
Simulation time 65302101 ps
CPU time 1.08 seconds
Started Mar 26 12:29:23 PM PDT 24
Finished Mar 26 12:29:24 PM PDT 24
Peak memory 196000 kb
Host smart-01b4a7d5-2a88-479c-b98a-c4f8ccd50c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610768483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1610768483
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3126988850
Short name T616
Test name
Test status
Simulation time 38888714 ps
CPU time 0.7 seconds
Started Mar 26 12:29:25 PM PDT 24
Finished Mar 26 12:29:26 PM PDT 24
Peak memory 195948 kb
Host smart-2f900133-5116-458a-bde9-7d655b3c1e31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126988850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3126988850
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1416952785
Short name T676
Test name
Test status
Simulation time 32414416 ps
CPU time 1.37 seconds
Started Mar 26 12:29:30 PM PDT 24
Finished Mar 26 12:29:32 PM PDT 24
Peak memory 197824 kb
Host smart-12175cd0-c618-4a49-a6c3-c01bedf6af64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416952785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1416952785
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.2008920515
Short name T288
Test name
Test status
Simulation time 79799875 ps
CPU time 0.85 seconds
Started Mar 26 12:29:25 PM PDT 24
Finished Mar 26 12:29:26 PM PDT 24
Peak memory 196916 kb
Host smart-89d4f244-ad93-42dc-9a1e-d9e72988161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008920515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2008920515
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2765942119
Short name T71
Test name
Test status
Simulation time 29169549 ps
CPU time 1.01 seconds
Started Mar 26 12:29:23 PM PDT 24
Finished Mar 26 12:29:25 PM PDT 24
Peak memory 196188 kb
Host smart-e78cb5f0-0495-4b9e-8e16-52ee73140bc6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765942119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2765942119
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3450854568
Short name T411
Test name
Test status
Simulation time 5049476457 ps
CPU time 69.34 seconds
Started Mar 26 12:29:32 PM PDT 24
Finished Mar 26 12:30:42 PM PDT 24
Peak memory 198080 kb
Host smart-5c21aa7a-7288-4c20-8482-544eae259948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450854568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3450854568
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2334278173
Short name T290
Test name
Test status
Simulation time 24338518 ps
CPU time 0.57 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 194508 kb
Host smart-e32a5171-4ee4-417f-9cc0-fd481a4d8282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334278173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2334278173
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3150562425
Short name T403
Test name
Test status
Simulation time 183197545 ps
CPU time 0.89 seconds
Started Mar 26 12:29:37 PM PDT 24
Finished Mar 26 12:29:39 PM PDT 24
Peak memory 196504 kb
Host smart-8682a483-a2f0-4a38-b1bb-7bff63d0d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150562425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3150562425
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3515070632
Short name T266
Test name
Test status
Simulation time 112760557 ps
CPU time 3.32 seconds
Started Mar 26 12:29:39 PM PDT 24
Finished Mar 26 12:29:43 PM PDT 24
Peak memory 195396 kb
Host smart-00191c39-75c5-4e2a-b30b-bcfb9580d7b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515070632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3515070632
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1075387555
Short name T391
Test name
Test status
Simulation time 205416750 ps
CPU time 0.83 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 196508 kb
Host smart-24927e23-45de-4cdd-bc7b-60c27ceb3500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075387555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1075387555
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3806138331
Short name T176
Test name
Test status
Simulation time 41251811 ps
CPU time 1.09 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:35 PM PDT 24
Peak memory 196708 kb
Host smart-fa3450d1-af08-425f-bd82-d3cdec37f8b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806138331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3806138331
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.129719891
Short name T74
Test name
Test status
Simulation time 63648645 ps
CPU time 2.23 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:37 PM PDT 24
Peak memory 197136 kb
Host smart-81a0652c-794c-45f2-9e1f-2a4ef3541cf3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129719891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.129719891
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2672113870
Short name T219
Test name
Test status
Simulation time 578028103 ps
CPU time 2.77 seconds
Started Mar 26 12:29:33 PM PDT 24
Finished Mar 26 12:29:35 PM PDT 24
Peak memory 196840 kb
Host smart-b23d93d5-410e-4bc1-a5da-393711984183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672113870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2672113870
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2648317913
Short name T222
Test name
Test status
Simulation time 24085726 ps
CPU time 0.85 seconds
Started Mar 26 12:29:32 PM PDT 24
Finished Mar 26 12:29:34 PM PDT 24
Peak memory 195868 kb
Host smart-f9f9df8f-93d0-4d3c-92f8-b3aa592580d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648317913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2648317913
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3052237670
Short name T389
Test name
Test status
Simulation time 24432401 ps
CPU time 0.95 seconds
Started Mar 26 12:29:33 PM PDT 24
Finished Mar 26 12:29:34 PM PDT 24
Peak memory 195804 kb
Host smart-f7406726-c5bc-424e-8bad-3f86f4eee5fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052237670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3052237670
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1430870197
Short name T210
Test name
Test status
Simulation time 1738499282 ps
CPU time 4.62 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:29:41 PM PDT 24
Peak memory 197804 kb
Host smart-586dd29e-5fd5-42e6-baf1-95d9ace8f000
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430870197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1430870197
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.821352770
Short name T48
Test name
Test status
Simulation time 175472442 ps
CPU time 0.98 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 214820 kb
Host smart-e8fb6e3c-5cf0-4f89-a060-73f1eb8ef50d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821352770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.821352770
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.576795333
Short name T457
Test name
Test status
Simulation time 341874499 ps
CPU time 1 seconds
Started Mar 26 12:29:36 PM PDT 24
Finished Mar 26 12:29:38 PM PDT 24
Peak memory 195520 kb
Host smart-478dd81e-aaa5-47ba-b04c-946adfd1742f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576795333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.576795333
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1517588352
Short name T139
Test name
Test status
Simulation time 40269950 ps
CPU time 0.95 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 195576 kb
Host smart-3d58ea90-7bcc-48c1-ac29-065f67915611
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517588352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1517588352
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3051297754
Short name T418
Test name
Test status
Simulation time 34024691380 ps
CPU time 87.11 seconds
Started Mar 26 12:29:33 PM PDT 24
Finished Mar 26 12:31:01 PM PDT 24
Peak memory 197928 kb
Host smart-6b8018b0-228d-4c90-9891-b3e0b3edc77d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051297754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3051297754
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2051044151
Short name T569
Test name
Test status
Simulation time 20112427 ps
CPU time 0.61 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:57 PM PDT 24
Peak memory 194516 kb
Host smart-eff2ff7f-c2ef-40e7-98b9-9dff5ccb07fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051044151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2051044151
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1280525254
Short name T568
Test name
Test status
Simulation time 377569661 ps
CPU time 18.59 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:30:13 PM PDT 24
Peak memory 196744 kb
Host smart-d627edf1-5b78-4768-a1ff-8987f4375652
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280525254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1280525254
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2892423183
Short name T350
Test name
Test status
Simulation time 65741778 ps
CPU time 0.89 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 196104 kb
Host smart-0a42e09d-8f07-493f-b008-1f99df04e677
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892423183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2892423183
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3212833784
Short name T700
Test name
Test status
Simulation time 39169820 ps
CPU time 1.07 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 196736 kb
Host smart-0c8d349f-e964-4cbc-98a0-58baee3fb796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212833784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3212833784
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.466597287
Short name T58
Test name
Test status
Simulation time 485184210 ps
CPU time 2.21 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:29:59 PM PDT 24
Peak memory 197132 kb
Host smart-266b744a-1d9e-49c7-836b-b64e63465143
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466597287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.466597287
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1623935944
Short name T442
Test name
Test status
Simulation time 433200786 ps
CPU time 3.12 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 197936 kb
Host smart-e833207c-7258-48e3-8575-159b34618859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623935944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1623935944
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.457698863
Short name T318
Test name
Test status
Simulation time 128836424 ps
CPU time 1.33 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:57 PM PDT 24
Peak memory 196816 kb
Host smart-65d00004-3ddc-4606-8901-ec07147255ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457698863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.457698863
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1488548685
Short name T458
Test name
Test status
Simulation time 121959027 ps
CPU time 1.09 seconds
Started Mar 26 12:29:55 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 197124 kb
Host smart-1277337d-a664-41a9-845c-a3d3965641d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488548685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1488548685
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1972839423
Short name T57
Test name
Test status
Simulation time 33077902 ps
CPU time 1.61 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 197848 kb
Host smart-2b9a533e-4d6f-4bc5-8e27-1d6e323239a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972839423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1972839423
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2942651316
Short name T702
Test name
Test status
Simulation time 149273547 ps
CPU time 0.93 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 196020 kb
Host smart-a05cdeb6-18d4-4df6-81e5-2fe6f9886eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942651316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2942651316
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1593748790
Short name T240
Test name
Test status
Simulation time 138581255 ps
CPU time 0.85 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:57 PM PDT 24
Peak memory 195288 kb
Host smart-aa43d1de-f629-4fe6-89fb-964a61c50906
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593748790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1593748790
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1801879637
Short name T627
Test name
Test status
Simulation time 24182070294 ps
CPU time 137.25 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:32:13 PM PDT 24
Peak memory 198028 kb
Host smart-27c281c7-980e-4a14-942b-ac23b640415e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801879637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1801879637
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3882059501
Short name T506
Test name
Test status
Simulation time 174720224770 ps
CPU time 756.79 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:42:31 PM PDT 24
Peak memory 197992 kb
Host smart-406c8dff-991e-4858-b68d-7283bca23fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3882059501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3882059501
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3148530546
Short name T643
Test name
Test status
Simulation time 12729354 ps
CPU time 0.61 seconds
Started Mar 26 12:30:07 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 193944 kb
Host smart-32f19c2e-8590-4fe8-8028-f0e70a2eceea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148530546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3148530546
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2335441393
Short name T55
Test name
Test status
Simulation time 199805724 ps
CPU time 0.86 seconds
Started Mar 26 12:30:08 PM PDT 24
Finished Mar 26 12:30:09 PM PDT 24
Peak memory 195816 kb
Host smart-90908664-685c-456c-a3fb-d58e3ec08385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335441393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2335441393
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2046054926
Short name T637
Test name
Test status
Simulation time 1975990584 ps
CPU time 24.2 seconds
Started Mar 26 12:30:04 PM PDT 24
Finished Mar 26 12:30:29 PM PDT 24
Peak memory 196776 kb
Host smart-de265870-5cbf-490a-8829-40fcccd045ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046054926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2046054926
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.174819405
Short name T393
Test name
Test status
Simulation time 80437697 ps
CPU time 0.94 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 196284 kb
Host smart-1eec26c0-de37-4721-a196-3cc04aeab10c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174819405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.174819405
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.4242370770
Short name T386
Test name
Test status
Simulation time 198918283 ps
CPU time 0.96 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 195980 kb
Host smart-2ff1cab1-f7ae-4e5a-8a0e-998ec7025149
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242370770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.4242370770
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.277653348
Short name T642
Test name
Test status
Simulation time 56931720 ps
CPU time 1.52 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 196048 kb
Host smart-be119828-b596-43eb-864f-56c033e53e98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277653348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
277653348
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1089324921
Short name T408
Test name
Test status
Simulation time 967444333 ps
CPU time 1.04 seconds
Started Mar 26 12:30:01 PM PDT 24
Finished Mar 26 12:30:03 PM PDT 24
Peak memory 195616 kb
Host smart-8a2beb69-909d-4a0c-bee6-a27a319d1b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089324921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1089324921
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2244760493
Short name T243
Test name
Test status
Simulation time 26384891 ps
CPU time 0.63 seconds
Started Mar 26 12:29:53 PM PDT 24
Finished Mar 26 12:29:54 PM PDT 24
Peak memory 194932 kb
Host smart-63121b9e-7126-476f-be0b-995c57c332a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244760493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2244760493
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2318128035
Short name T165
Test name
Test status
Simulation time 139839610 ps
CPU time 1.28 seconds
Started Mar 26 12:30:04 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 197960 kb
Host smart-05aff1d2-668f-45d3-b707-6380e0eb7982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318128035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2318128035
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.178449513
Short name T308
Test name
Test status
Simulation time 348555817 ps
CPU time 1.41 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 197808 kb
Host smart-1a864b01-b11c-4696-9b01-5154d7c8051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178449513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.178449513
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2255665144
Short name T190
Test name
Test status
Simulation time 238226525 ps
CPU time 1.15 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 196704 kb
Host smart-dcd3f68c-fb10-4c56-ba75-cfd8016777c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255665144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2255665144
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1928640925
Short name T675
Test name
Test status
Simulation time 14032994350 ps
CPU time 50.77 seconds
Started Mar 26 12:30:08 PM PDT 24
Finished Mar 26 12:30:59 PM PDT 24
Peak memory 198024 kb
Host smart-66d0029e-96cc-4334-8e36-4e63e278599a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928640925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1928640925
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1857629997
Short name T615
Test name
Test status
Simulation time 23533902 ps
CPU time 0.56 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 194508 kb
Host smart-75ebe8e2-c5b2-4442-a945-ea23dc8be309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857629997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1857629997
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2948086666
Short name T174
Test name
Test status
Simulation time 70625810 ps
CPU time 0.94 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 196468 kb
Host smart-dc2712fc-07e3-4acf-907e-e2cd60e26d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948086666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2948086666
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.833884458
Short name T591
Test name
Test status
Simulation time 541870270 ps
CPU time 15.89 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 197812 kb
Host smart-a8a73df8-6d0d-47be-aafc-0e62968f55c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833884458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.833884458
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2488363907
Short name T156
Test name
Test status
Simulation time 96649497 ps
CPU time 0.79 seconds
Started Mar 26 12:30:08 PM PDT 24
Finished Mar 26 12:30:09 PM PDT 24
Peak memory 195852 kb
Host smart-71b77c2e-b5e0-4116-bc93-f2622d167f68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488363907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2488363907
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3933637499
Short name T546
Test name
Test status
Simulation time 714659315 ps
CPU time 1.35 seconds
Started Mar 26 12:30:07 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 197908 kb
Host smart-651f6695-d3fe-4903-8158-e6fc4ce9d60d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933637499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3933637499
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.329238976
Short name T598
Test name
Test status
Simulation time 63186815 ps
CPU time 2.35 seconds
Started Mar 26 12:30:04 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 197976 kb
Host smart-04cc7b2e-5cd1-4b96-8749-1697f7fe5dc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329238976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.329238976
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2797736799
Short name T683
Test name
Test status
Simulation time 150906593 ps
CPU time 3.14 seconds
Started Mar 26 12:30:08 PM PDT 24
Finished Mar 26 12:30:11 PM PDT 24
Peak memory 196900 kb
Host smart-71124968-b082-4bc7-abeb-b9a8c913a89d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797736799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2797736799
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.578419827
Short name T359
Test name
Test status
Simulation time 83918305 ps
CPU time 1.25 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 196792 kb
Host smart-5e6fdd7e-9ce7-4f78-ae84-aec0bc37b68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578419827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.578419827
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.137805869
Short name T594
Test name
Test status
Simulation time 101129686 ps
CPU time 0.99 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 195852 kb
Host smart-ccbdf5b1-9e7c-481f-9178-e97b7136d3a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137805869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.137805869
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.408609116
Short name T304
Test name
Test status
Simulation time 66996434 ps
CPU time 2.96 seconds
Started Mar 26 12:30:09 PM PDT 24
Finished Mar 26 12:30:12 PM PDT 24
Peak memory 197816 kb
Host smart-2f587d5c-04b6-4fc0-9267-1c509e5bb62d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408609116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.408609116
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.4289011706
Short name T379
Test name
Test status
Simulation time 79045437 ps
CPU time 1.38 seconds
Started Mar 26 12:30:08 PM PDT 24
Finished Mar 26 12:30:10 PM PDT 24
Peak memory 197772 kb
Host smart-0de10e18-62bd-4edc-b819-83f6618316e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289011706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.4289011706
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.278673033
Short name T246
Test name
Test status
Simulation time 100822821 ps
CPU time 1.34 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 196708 kb
Host smart-433eaedf-91d8-4227-bbfd-777b02fd2c4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278673033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.278673033
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2520799681
Short name T456
Test name
Test status
Simulation time 79376003784 ps
CPU time 123.4 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:32:09 PM PDT 24
Peak memory 198132 kb
Host smart-10a984af-9115-4ace-8ace-4665d5dca35f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520799681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2520799681
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.216928489
Short name T428
Test name
Test status
Simulation time 22187982 ps
CPU time 0.54 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 194472 kb
Host smart-6a2ac86a-3eb6-418e-8375-c0ca8960f2f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216928489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.216928489
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3139215979
Short name T291
Test name
Test status
Simulation time 29776001 ps
CPU time 0.77 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 195240 kb
Host smart-c5a2ddf4-8e3d-43f1-a52c-50cca0f29fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139215979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3139215979
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1079858492
Short name T497
Test name
Test status
Simulation time 2212912178 ps
CPU time 20.14 seconds
Started Mar 26 12:30:09 PM PDT 24
Finished Mar 26 12:30:29 PM PDT 24
Peak memory 196732 kb
Host smart-a2ea014a-6476-430a-866d-be5cedca42ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079858492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1079858492
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.87931374
Short name T20
Test name
Test status
Simulation time 84076824 ps
CPU time 0.88 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 197016 kb
Host smart-91ffb896-8b0a-497b-95f9-3045c40768b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87931374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.87931374
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1360769140
Short name T289
Test name
Test status
Simulation time 104894484 ps
CPU time 1.44 seconds
Started Mar 26 12:30:07 PM PDT 24
Finished Mar 26 12:30:09 PM PDT 24
Peak memory 197044 kb
Host smart-cae6f2dd-6774-44ee-ae5a-de5298ba2ef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360769140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1360769140
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.139771652
Short name T265
Test name
Test status
Simulation time 94485454 ps
CPU time 3.46 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 197928 kb
Host smart-2447eaf8-9a7e-41e6-873a-2b0e989688fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139771652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.139771652
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2944521456
Short name T421
Test name
Test status
Simulation time 59157674 ps
CPU time 1.81 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 196008 kb
Host smart-89a1470d-37a6-48dd-9ecb-8ea06e506b0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944521456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2944521456
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1711339964
Short name T272
Test name
Test status
Simulation time 164167658 ps
CPU time 1.07 seconds
Started Mar 26 12:30:07 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 195772 kb
Host smart-3eeab09f-6b19-4eec-9b76-7766b7add2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711339964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1711339964
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.448314584
Short name T451
Test name
Test status
Simulation time 58198802 ps
CPU time 1.14 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 195756 kb
Host smart-ca24264c-3811-403c-af95-1ff26c6ba6a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448314584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.448314584
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2637584731
Short name T396
Test name
Test status
Simulation time 2384248183 ps
CPU time 5.43 seconds
Started Mar 26 12:30:08 PM PDT 24
Finished Mar 26 12:30:14 PM PDT 24
Peak memory 197972 kb
Host smart-06e92c7f-f09a-47ab-8c13-22c568345ab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637584731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2637584731
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1803282194
Short name T520
Test name
Test status
Simulation time 506170231 ps
CPU time 1.16 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 196572 kb
Host smart-49886d4c-24e7-4f6b-a55e-399235716a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803282194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1803282194
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3860658942
Short name T527
Test name
Test status
Simulation time 23668485 ps
CPU time 0.79 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 195328 kb
Host smart-dbf6a2ff-2ac5-4e1e-9191-0109a5f8569d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860658942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3860658942
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2586704419
Short name T10
Test name
Test status
Simulation time 14169121446 ps
CPU time 149.24 seconds
Started Mar 26 12:30:08 PM PDT 24
Finished Mar 26 12:32:37 PM PDT 24
Peak memory 198056 kb
Host smart-59bcf0b3-38ab-48f7-8862-651a726a3414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586704419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2586704419
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2450011275
Short name T639
Test name
Test status
Simulation time 23201732010 ps
CPU time 475.34 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:38:01 PM PDT 24
Peak memory 198120 kb
Host smart-0e74a613-fc27-48aa-8d15-d8dc6541d82d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2450011275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2450011275
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2963499752
Short name T305
Test name
Test status
Simulation time 10382955 ps
CPU time 0.55 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 194348 kb
Host smart-b92601fd-6216-4091-b00a-ada2059bcd4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963499752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2963499752
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1664826536
Short name T482
Test name
Test status
Simulation time 39279616 ps
CPU time 0.69 seconds
Started Mar 26 12:30:09 PM PDT 24
Finished Mar 26 12:30:10 PM PDT 24
Peak memory 193912 kb
Host smart-01555ff0-2200-4d6f-908d-ca66407a2d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664826536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1664826536
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2740300289
Short name T444
Test name
Test status
Simulation time 3601443212 ps
CPU time 25.27 seconds
Started Mar 26 12:30:07 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 197940 kb
Host smart-860ecd1a-6ca5-4e5b-abf7-1025bcd8158e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740300289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2740300289
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1117268502
Short name T465
Test name
Test status
Simulation time 62522808 ps
CPU time 0.9 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 196340 kb
Host smart-37cd593b-002f-40d8-b9b8-2ce6ef182215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117268502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1117268502
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2228962296
Short name T292
Test name
Test status
Simulation time 84262488 ps
CPU time 1.24 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 195972 kb
Host smart-8c18e333-9d90-4570-9206-1527654bcb32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228962296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2228962296
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2692604847
Short name T694
Test name
Test status
Simulation time 706938875 ps
CPU time 3.26 seconds
Started Mar 26 12:30:07 PM PDT 24
Finished Mar 26 12:30:10 PM PDT 24
Peak memory 197952 kb
Host smart-034288dc-ee3b-46c1-91b2-abcc7180d98a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692604847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2692604847
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2983755129
Short name T392
Test name
Test status
Simulation time 419077303 ps
CPU time 2.09 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:09 PM PDT 24
Peak memory 196804 kb
Host smart-93be939b-f470-4c88-bc37-29d422d8ef40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983755129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2983755129
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1812360227
Short name T327
Test name
Test status
Simulation time 44449341 ps
CPU time 0.95 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 196500 kb
Host smart-77e48673-f18e-4425-9aab-8b65bd9911c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812360227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1812360227
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1575812752
Short name T580
Test name
Test status
Simulation time 28819544 ps
CPU time 0.79 seconds
Started Mar 26 12:30:04 PM PDT 24
Finished Mar 26 12:30:05 PM PDT 24
Peak memory 197268 kb
Host smart-f5599381-73f7-48a9-aa3a-b143fb196204
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575812752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1575812752
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1717618942
Short name T215
Test name
Test status
Simulation time 744989425 ps
CPU time 3.12 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:30:09 PM PDT 24
Peak memory 197892 kb
Host smart-53f558a3-0990-4913-a82c-77ef9428456f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717618942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1717618942
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.602913638
Short name T526
Test name
Test status
Simulation time 207028789 ps
CPU time 0.82 seconds
Started Mar 26 12:30:08 PM PDT 24
Finished Mar 26 12:30:09 PM PDT 24
Peak memory 195264 kb
Host smart-5b2be2b5-9405-415d-8edb-667b6c991665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602913638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.602913638
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1748156528
Short name T531
Test name
Test status
Simulation time 33950492 ps
CPU time 0.82 seconds
Started Mar 26 12:30:07 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 195056 kb
Host smart-a3482721-6724-47ee-bb80-878cfd2e9f3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748156528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1748156528
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2830181219
Short name T213
Test name
Test status
Simulation time 5167294112 ps
CPU time 65.82 seconds
Started Mar 26 12:30:05 PM PDT 24
Finished Mar 26 12:31:11 PM PDT 24
Peak memory 198000 kb
Host smart-5ccf4289-7a39-4af0-9d94-3e67a8c18e9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830181219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2830181219
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1242003109
Short name T60
Test name
Test status
Simulation time 39801439047 ps
CPU time 593.35 seconds
Started Mar 26 12:30:06 PM PDT 24
Finished Mar 26 12:40:00 PM PDT 24
Peak memory 198056 kb
Host smart-86ddaa91-1c92-4f7c-882b-86444a3d0880
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1242003109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1242003109
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2252547455
Short name T525
Test name
Test status
Simulation time 41279778 ps
CPU time 0.54 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 194468 kb
Host smart-353e35d0-78b9-4e28-a766-48c4b2df9f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252547455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2252547455
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2703799577
Short name T715
Test name
Test status
Simulation time 17338390 ps
CPU time 0.67 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 194016 kb
Host smart-98a2cb1a-6fd6-4185-80c8-3a5da088ea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703799577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2703799577
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3005197058
Short name T226
Test name
Test status
Simulation time 469617792 ps
CPU time 7.53 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:29 PM PDT 24
Peak memory 195344 kb
Host smart-b953438a-c520-40f0-b72b-af27e332afce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005197058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3005197058
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3764251199
Short name T301
Test name
Test status
Simulation time 21264911 ps
CPU time 0.62 seconds
Started Mar 26 12:30:17 PM PDT 24
Finished Mar 26 12:30:18 PM PDT 24
Peak memory 195172 kb
Host smart-a96ee5d0-9351-4363-bd00-9932a4f17cca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764251199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3764251199
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.106886798
Short name T206
Test name
Test status
Simulation time 53490232 ps
CPU time 0.94 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 196032 kb
Host smart-aff7e9cb-fb68-4207-96a4-9538fe029cb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106886798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.106886798
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1718152962
Short name T558
Test name
Test status
Simulation time 107442265 ps
CPU time 2.06 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 197944 kb
Host smart-dca5a6bf-2f9d-4c95-82d7-e9669a4d9ebb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718152962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1718152962
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2966092887
Short name T443
Test name
Test status
Simulation time 79443497 ps
CPU time 1.7 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 196504 kb
Host smart-adcd7a8e-1929-443a-b4d7-a1d578d3e669
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966092887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2966092887
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3352962566
Short name T486
Test name
Test status
Simulation time 28852437 ps
CPU time 0.83 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 196360 kb
Host smart-0aec0de7-6dc6-468e-a6d8-48ff8147f4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352962566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3352962566
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2449038340
Short name T146
Test name
Test status
Simulation time 49960252 ps
CPU time 1.04 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 195584 kb
Host smart-ac2deca4-2317-4067-830e-15ce6a5a25ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449038340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2449038340
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3383102972
Short name T275
Test name
Test status
Simulation time 152996614 ps
CPU time 1.51 seconds
Started Mar 26 12:30:17 PM PDT 24
Finished Mar 26 12:30:19 PM PDT 24
Peak memory 197712 kb
Host smart-710080b2-e63e-46e6-b3d3-24d358d34df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383102972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3383102972
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4118585237
Short name T604
Test name
Test status
Simulation time 54628288 ps
CPU time 0.96 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 196372 kb
Host smart-c3f80596-472f-4996-97ed-79748cc32041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118585237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4118585237
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1049749527
Short name T585
Test name
Test status
Simulation time 114639365 ps
CPU time 1.08 seconds
Started Mar 26 12:30:22 PM PDT 24
Finished Mar 26 12:30:23 PM PDT 24
Peak memory 195532 kb
Host smart-bc4fe1de-0052-45fd-9b1f-e69e1793cca1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049749527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1049749527
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3673829622
Short name T432
Test name
Test status
Simulation time 6721653980 ps
CPU time 85.99 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:31:47 PM PDT 24
Peak memory 198052 kb
Host smart-d4d8c8e2-ce19-47c9-9977-4de9be652cb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673829622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3673829622
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.769367921
Short name T515
Test name
Test status
Simulation time 102230853 ps
CPU time 0.57 seconds
Started Mar 26 12:30:22 PM PDT 24
Finished Mar 26 12:30:23 PM PDT 24
Peak memory 194000 kb
Host smart-b24004f3-019b-44b9-b740-1a0c50bd1923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769367921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.769367921
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2858797048
Short name T674
Test name
Test status
Simulation time 22500053 ps
CPU time 0.69 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 193952 kb
Host smart-563c2fa6-6a59-4e42-852a-bb7d2b02e1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858797048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2858797048
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.266397359
Short name T285
Test name
Test status
Simulation time 1318586493 ps
CPU time 26.38 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:45 PM PDT 24
Peak memory 195368 kb
Host smart-4ac7d715-4304-4e24-bc0b-79f4b1cec55e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266397359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.266397359
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3132389155
Short name T634
Test name
Test status
Simulation time 230743722 ps
CPU time 0.96 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 196192 kb
Host smart-bcf4d122-501e-46c2-a5b2-1054f5aac99b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132389155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3132389155
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2450625983
Short name T357
Test name
Test status
Simulation time 30664034 ps
CPU time 0.9 seconds
Started Mar 26 12:30:17 PM PDT 24
Finished Mar 26 12:30:18 PM PDT 24
Peak memory 195852 kb
Host smart-1e458974-6b4c-4f59-b9d2-e5d16097e504
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450625983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2450625983
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.756936155
Short name T373
Test name
Test status
Simulation time 58909329 ps
CPU time 2.35 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:24 PM PDT 24
Peak memory 197892 kb
Host smart-ca9ae7e3-2ce4-4547-b669-a1c6eb6289b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756936155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.756936155
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.438994885
Short name T162
Test name
Test status
Simulation time 104046365 ps
CPU time 1.42 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 196004 kb
Host smart-89b85b2b-53cb-4b57-890a-48d732d7a5d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438994885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
438994885
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3227966610
Short name T161
Test name
Test status
Simulation time 72042509 ps
CPU time 0.81 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:19 PM PDT 24
Peak memory 196500 kb
Host smart-7911685d-aa02-4c97-b974-fa4a52fb638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227966610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3227966610
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1654435995
Short name T479
Test name
Test status
Simulation time 19837371 ps
CPU time 0.63 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:19 PM PDT 24
Peak memory 194240 kb
Host smart-6dcbd55b-746e-4617-b172-264d0c2236e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654435995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1654435995
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.872842958
Short name T15
Test name
Test status
Simulation time 301948860 ps
CPU time 1.34 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 197796 kb
Host smart-675b46d0-44b5-4ce3-bba1-36cfb3583b1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872842958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.872842958
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.933262887
Short name T108
Test name
Test status
Simulation time 65417131 ps
CPU time 0.72 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:19 PM PDT 24
Peak memory 195020 kb
Host smart-351d9829-61b6-4a48-9ae1-7db4aef9511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933262887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.933262887
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.414336649
Short name T342
Test name
Test status
Simulation time 73143688 ps
CPU time 1.16 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 195336 kb
Host smart-a28f8a73-c013-49e7-8a11-20e4429695ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414336649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.414336649
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.727296157
Short name T677
Test name
Test status
Simulation time 32227290853 ps
CPU time 112.17 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:32:11 PM PDT 24
Peak memory 198016 kb
Host smart-c758e2ca-014c-470d-a0c6-4e7591b70308
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727296157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.727296157
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.438983823
Short name T401
Test name
Test status
Simulation time 12228896 ps
CPU time 0.56 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 193796 kb
Host smart-65898376-1541-4f10-bf47-9d1e7092d342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438983823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.438983823
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2102466176
Short name T131
Test name
Test status
Simulation time 16566110 ps
CPU time 0.59 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 193796 kb
Host smart-26735974-f36d-4af8-8f04-2f7906fbf2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102466176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2102466176
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4161771430
Short name T13
Test name
Test status
Simulation time 690169849 ps
CPU time 23.73 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:42 PM PDT 24
Peak memory 196944 kb
Host smart-06ca5bee-0885-4dc1-bef2-442677fd2dd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161771430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4161771430
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4207797425
Short name T121
Test name
Test status
Simulation time 30214723 ps
CPU time 0.67 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 195244 kb
Host smart-304b9af2-25a1-485e-8ea5-cd7d739536e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207797425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4207797425
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3056071606
Short name T621
Test name
Test status
Simulation time 62538581 ps
CPU time 1.14 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 196536 kb
Host smart-337aa3cf-70b6-4f7b-906d-7e85586d8a03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056071606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3056071606
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1263173689
Short name T260
Test name
Test status
Simulation time 37602092 ps
CPU time 1.01 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:19 PM PDT 24
Peak memory 196008 kb
Host smart-c2b8c1fd-bb61-4fce-b7d3-1d5c67b21a41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263173689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1263173689
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.406539956
Short name T245
Test name
Test status
Simulation time 59722850 ps
CPU time 1.86 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 196028 kb
Host smart-e2ae278f-1cac-49bd-b7cd-00dbcd567be4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406539956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
406539956
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2625413925
Short name T477
Test name
Test status
Simulation time 24774521 ps
CPU time 0.63 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 194000 kb
Host smart-a80f8215-8815-4918-9dde-9bd39df21087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625413925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2625413925
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2617765908
Short name T424
Test name
Test status
Simulation time 52018483 ps
CPU time 0.69 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:19 PM PDT 24
Peak memory 195360 kb
Host smart-12f7181e-9414-4478-b9be-fc8a15b63dd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617765908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2617765908
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2676171962
Short name T410
Test name
Test status
Simulation time 139887953 ps
CPU time 3.18 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:23 PM PDT 24
Peak memory 197872 kb
Host smart-8d00510e-da4a-4436-9a6c-54082c675122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676171962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2676171962
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.4193457023
Short name T208
Test name
Test status
Simulation time 408230617 ps
CPU time 1.42 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 196672 kb
Host smart-ae01b040-9ef3-45e8-85d4-644490d6e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193457023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.4193457023
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3538758575
Short name T329
Test name
Test status
Simulation time 488684699 ps
CPU time 1.34 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:23 PM PDT 24
Peak memory 195324 kb
Host smart-dd225a19-41c4-408f-8e3d-497d110c6768
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538758575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3538758575
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2579747312
Short name T273
Test name
Test status
Simulation time 18651940723 ps
CPU time 105.04 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:32:03 PM PDT 24
Peak memory 198048 kb
Host smart-ddb288f1-5a58-44f0-835f-095be26b0977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579747312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2579747312
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3005881993
Short name T133
Test name
Test status
Simulation time 15297463 ps
CPU time 0.59 seconds
Started Mar 26 12:30:31 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 194496 kb
Host smart-253d9225-8222-43f8-b487-3671fcce43a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005881993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3005881993
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2071497312
Short name T150
Test name
Test status
Simulation time 91997012 ps
CPU time 0.7 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 195176 kb
Host smart-88339f89-fe99-429d-b0e7-d9460de77598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071497312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2071497312
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.702488859
Short name T435
Test name
Test status
Simulation time 1442266971 ps
CPU time 24.97 seconds
Started Mar 26 12:30:31 PM PDT 24
Finished Mar 26 12:30:56 PM PDT 24
Peak memory 197840 kb
Host smart-d9e23601-ea03-438b-9041-b432fe6c956d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702488859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.702488859
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.860710538
Short name T407
Test name
Test status
Simulation time 66174463 ps
CPU time 0.9 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 197788 kb
Host smart-e0dbbde4-be08-4e99-a18f-d82e8ecfe2e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860710538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.860710538
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.181707679
Short name T205
Test name
Test status
Simulation time 240446559 ps
CPU time 0.7 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 195224 kb
Host smart-ee508925-0443-42df-bc53-ab57da0937da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181707679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.181707679
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1278311280
Short name T469
Test name
Test status
Simulation time 35558445 ps
CPU time 1.33 seconds
Started Mar 26 12:30:31 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 196432 kb
Host smart-1645147e-3b39-4335-bc35-552c23373b46
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278311280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1278311280
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.107675714
Short name T648
Test name
Test status
Simulation time 296774241 ps
CPU time 1.62 seconds
Started Mar 26 12:30:20 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 195660 kb
Host smart-d12b25d3-d359-4a11-8f4d-4bc03ed1e511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107675714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
107675714
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1505383474
Short name T423
Test name
Test status
Simulation time 82707942 ps
CPU time 0.79 seconds
Started Mar 26 12:30:21 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 196080 kb
Host smart-2f872d0b-2c48-4ccd-8e9f-1e329de857bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505383474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1505383474
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3163552854
Short name T334
Test name
Test status
Simulation time 17045089 ps
CPU time 0.72 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:20 PM PDT 24
Peak memory 195276 kb
Host smart-f284ca99-b4fa-4d67-838f-bc20cef4748a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163552854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3163552854
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3173658875
Short name T331
Test name
Test status
Simulation time 616119741 ps
CPU time 4.63 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:38 PM PDT 24
Peak memory 197788 kb
Host smart-3f3a94cc-bde9-44ba-b1e6-654c9d237a24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173658875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3173658875
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3364030373
Short name T311
Test name
Test status
Simulation time 199113115 ps
CPU time 1.49 seconds
Started Mar 26 12:30:19 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 197804 kb
Host smart-7558b014-c610-440b-8a11-8b739ba27703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364030373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3364030373
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1627739220
Short name T126
Test name
Test status
Simulation time 58194964 ps
CPU time 0.78 seconds
Started Mar 26 12:30:18 PM PDT 24
Finished Mar 26 12:30:19 PM PDT 24
Peak memory 195736 kb
Host smart-3712d964-c9fc-4ae6-ab81-cd8731482758
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627739220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1627739220
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3510815785
Short name T665
Test name
Test status
Simulation time 7998122734 ps
CPU time 190.29 seconds
Started Mar 26 12:30:35 PM PDT 24
Finished Mar 26 12:33:46 PM PDT 24
Peak memory 197892 kb
Host smart-3dbd0100-345a-4307-a0b9-797a279dd5c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510815785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3510815785
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.4280884159
Short name T52
Test name
Test status
Simulation time 99748190856 ps
CPU time 2632.76 seconds
Started Mar 26 12:30:32 PM PDT 24
Finished Mar 26 01:14:25 PM PDT 24
Peak memory 198084 kb
Host smart-6b11e345-29f6-48c1-b0ca-8ea9f7156380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4280884159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.4280884159
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2262580257
Short name T125
Test name
Test status
Simulation time 23562432 ps
CPU time 0.54 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:33 PM PDT 24
Peak memory 193736 kb
Host smart-c0f1c0ac-402c-4b29-b357-da07b939057f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262580257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2262580257
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.490751803
Short name T502
Test name
Test status
Simulation time 146008520 ps
CPU time 0.82 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 196208 kb
Host smart-e7643ebd-2009-43ec-95fe-1d384de842c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490751803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.490751803
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2602072358
Short name T699
Test name
Test status
Simulation time 345544853 ps
CPU time 9.75 seconds
Started Mar 26 12:30:30 PM PDT 24
Finished Mar 26 12:30:40 PM PDT 24
Peak memory 196800 kb
Host smart-addcf080-6444-4d36-acdb-4808a4a97b78
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602072358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2602072358
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.371952854
Short name T427
Test name
Test status
Simulation time 74770209 ps
CPU time 0.77 seconds
Started Mar 26 12:30:39 PM PDT 24
Finished Mar 26 12:30:41 PM PDT 24
Peak memory 195816 kb
Host smart-bc7d298f-c10a-44e8-99f5-ca3bffb6a3eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371952854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.371952854
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1132391231
Short name T503
Test name
Test status
Simulation time 195763832 ps
CPU time 1.17 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 195640 kb
Host smart-e9e5cb78-accc-4b05-9499-4cbae599c0c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132391231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1132391231
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3140703133
Short name T589
Test name
Test status
Simulation time 79414974 ps
CPU time 1.02 seconds
Started Mar 26 12:30:35 PM PDT 24
Finished Mar 26 12:30:36 PM PDT 24
Peak memory 196032 kb
Host smart-b5fc946f-f7ae-4420-8f1a-4cb6b474ac86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140703133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3140703133
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2027637648
Short name T538
Test name
Test status
Simulation time 274708393 ps
CPU time 3.01 seconds
Started Mar 26 12:30:31 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 196840 kb
Host smart-cbb3abd8-b064-4788-8b11-9be10ec18d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027637648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2027637648
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1203431267
Short name T112
Test name
Test status
Simulation time 78179747 ps
CPU time 1.3 seconds
Started Mar 26 12:30:30 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 196704 kb
Host smart-fd530625-9abd-4b91-9312-52a2ee465d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203431267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1203431267
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2316276635
Short name T23
Test name
Test status
Simulation time 272298947 ps
CPU time 1.02 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 195844 kb
Host smart-d9d566a3-0aec-481a-9d1c-fe35a9720bce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316276635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2316276635
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3454365919
Short name T618
Test name
Test status
Simulation time 532773305 ps
CPU time 1.88 seconds
Started Mar 26 12:30:30 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 197964 kb
Host smart-196209f2-9d1d-4c5a-abd6-e1c013be4fda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454365919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3454365919
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2353385914
Short name T338
Test name
Test status
Simulation time 119629488 ps
CPU time 0.72 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 195132 kb
Host smart-799e3a53-c618-435c-b294-1f4fad746876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353385914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2353385914
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.613269164
Short name T471
Test name
Test status
Simulation time 49947833 ps
CPU time 1.09 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 196212 kb
Host smart-892fc22c-8c8d-4257-9791-1c5c28606f4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613269164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.613269164
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.631867350
Short name T575
Test name
Test status
Simulation time 7198995357 ps
CPU time 96.94 seconds
Started Mar 26 12:30:32 PM PDT 24
Finished Mar 26 12:32:09 PM PDT 24
Peak memory 197892 kb
Host smart-e12e4166-ad1e-4443-97a4-cb2bd4d96a17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631867350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.631867350
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2182902658
Short name T645
Test name
Test status
Simulation time 39359423 ps
CPU time 0.54 seconds
Started Mar 26 12:29:39 PM PDT 24
Finished Mar 26 12:29:39 PM PDT 24
Peak memory 193740 kb
Host smart-6ba5362e-9047-4286-a5ab-2a3fee1812f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182902658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2182902658
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3376550267
Short name T579
Test name
Test status
Simulation time 52207399 ps
CPU time 0.66 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:34 PM PDT 24
Peak memory 194096 kb
Host smart-11a5160e-32c1-44ae-9d28-1025790a5277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376550267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3376550267
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1382435562
Short name T611
Test name
Test status
Simulation time 516652877 ps
CPU time 26.08 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:30:01 PM PDT 24
Peak memory 196956 kb
Host smart-7888bee1-b492-4b1d-aa1e-9a7eea56f8fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382435562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1382435562
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4084800611
Short name T533
Test name
Test status
Simulation time 55347227 ps
CPU time 0.75 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 195864 kb
Host smart-ed81b7ca-2390-41b0-bded-08e8e6a75857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084800611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4084800611
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1828093210
Short name T186
Test name
Test status
Simulation time 66306778 ps
CPU time 1.1 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:29:38 PM PDT 24
Peak memory 195952 kb
Host smart-c9180275-dbf5-4ea2-9260-2c6017287622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828093210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1828093210
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2409073926
Short name T593
Test name
Test status
Simulation time 56481251 ps
CPU time 2.03 seconds
Started Mar 26 12:29:36 PM PDT 24
Finished Mar 26 12:29:39 PM PDT 24
Peak memory 196196 kb
Host smart-32391159-45b8-4d6f-82b5-205cb9abd25b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409073926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2409073926
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2647850791
Short name T631
Test name
Test status
Simulation time 67075334 ps
CPU time 1.48 seconds
Started Mar 26 12:29:37 PM PDT 24
Finished Mar 26 12:29:39 PM PDT 24
Peak memory 195976 kb
Host smart-37bd0a93-8178-4465-ade2-1a33f7171940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647850791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2647850791
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3832744774
Short name T635
Test name
Test status
Simulation time 100326424 ps
CPU time 0.92 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 195848 kb
Host smart-2d701444-b4c2-4ca3-826f-0db0946490a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832744774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3832744774
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.903513710
Short name T505
Test name
Test status
Simulation time 220235088 ps
CPU time 0.69 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:29:37 PM PDT 24
Peak memory 195328 kb
Host smart-685b2b83-036d-489d-ab30-2fb6a067fd9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903513710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.903513710
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1583877861
Short name T11
Test name
Test status
Simulation time 337392861 ps
CPU time 3.67 seconds
Started Mar 26 12:29:32 PM PDT 24
Finished Mar 26 12:29:35 PM PDT 24
Peak memory 197828 kb
Host smart-a9eaca4a-6883-4aa8-8799-53584aa2d8a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583877861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1583877861
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2106649898
Short name T40
Test name
Test status
Simulation time 116370071 ps
CPU time 0.9 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 214776 kb
Host smart-a8e96814-127f-456a-bca5-edb702398d60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106649898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2106649898
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2990260214
Short name T322
Test name
Test status
Simulation time 147017763 ps
CPU time 0.84 seconds
Started Mar 26 12:29:39 PM PDT 24
Finished Mar 26 12:29:40 PM PDT 24
Peak memory 195320 kb
Host smart-5c752024-56d4-4de6-88e4-53b0016773e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990260214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2990260214
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2519376536
Short name T224
Test name
Test status
Simulation time 188207529 ps
CPU time 1.35 seconds
Started Mar 26 12:29:40 PM PDT 24
Finished Mar 26 12:29:42 PM PDT 24
Peak memory 197812 kb
Host smart-d76a81f6-fa9a-4b04-9052-13f56a0d4993
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519376536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2519376536
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.928572007
Short name T314
Test name
Test status
Simulation time 25103176155 ps
CPU time 149.57 seconds
Started Mar 26 12:29:36 PM PDT 24
Finished Mar 26 12:32:06 PM PDT 24
Peak memory 198016 kb
Host smart-ae66006c-090b-42b4-80a8-be843b81620d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928572007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.928572007
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.4015171554
Short name T230
Test name
Test status
Simulation time 26547299 ps
CPU time 0.56 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 194668 kb
Host smart-cd122c3b-3321-4925-96b1-bbf59c932a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015171554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.4015171554
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.312986726
Short name T229
Test name
Test status
Simulation time 19578019 ps
CPU time 0.62 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 194008 kb
Host smart-59d57dfc-02c2-44f8-b74f-914cdbb603fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312986726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.312986726
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2563332947
Short name T66
Test name
Test status
Simulation time 6667671105 ps
CPU time 26.71 seconds
Started Mar 26 12:30:40 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 196948 kb
Host smart-1176386e-e374-4230-a66c-bb55f0063c37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563332947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2563332947
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.892324911
Short name T480
Test name
Test status
Simulation time 59137574 ps
CPU time 0.88 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 196332 kb
Host smart-0e4dcce7-6b5e-4576-8b68-878484552966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892324911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.892324911
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.37830540
Short name T556
Test name
Test status
Simulation time 87189688 ps
CPU time 0.78 seconds
Started Mar 26 12:30:35 PM PDT 24
Finished Mar 26 12:30:36 PM PDT 24
Peak memory 195576 kb
Host smart-39e771fd-d98b-4c47-b66d-20be84ddc1f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37830540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.37830540
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.135878096
Short name T387
Test name
Test status
Simulation time 113461574 ps
CPU time 1.28 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 197968 kb
Host smart-b5158900-11e0-4f84-8329-03943e8540a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135878096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.135878096
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2514250260
Short name T578
Test name
Test status
Simulation time 453643489 ps
CPU time 2.13 seconds
Started Mar 26 12:30:39 PM PDT 24
Finished Mar 26 12:30:42 PM PDT 24
Peak memory 196980 kb
Host smart-40bee487-afa8-4cb2-a0aa-ba04c24c3597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514250260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2514250260
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.611649660
Short name T264
Test name
Test status
Simulation time 31534381 ps
CPU time 0.72 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 195372 kb
Host smart-97d816fd-32c9-4803-abd1-af31486c305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611649660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.611649660
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.639576
Short name T172
Test name
Test status
Simulation time 379382679 ps
CPU time 1.19 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 196964 kb
Host smart-ef71d228-b34e-413d-ab02-522236c8334c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup_pu
lldown.639576
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3875348487
Short name T7
Test name
Test status
Simulation time 340509189 ps
CPU time 2.08 seconds
Started Mar 26 12:30:30 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 197800 kb
Host smart-313ec4c1-124b-4c9f-9098-dff566b793d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875348487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3875348487
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2042497971
Short name T261
Test name
Test status
Simulation time 80328162 ps
CPU time 0.87 seconds
Started Mar 26 12:30:31 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 197116 kb
Host smart-a4f154b6-fc34-4ee4-a9af-7889f382e320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042497971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2042497971
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3819825384
Short name T12
Test name
Test status
Simulation time 59903196 ps
CPU time 1.2 seconds
Started Mar 26 12:30:30 PM PDT 24
Finished Mar 26 12:30:31 PM PDT 24
Peak memory 195656 kb
Host smart-bd94597b-e5ae-46e4-87c0-0b27eeaf3fd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819825384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3819825384
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1806182603
Short name T286
Test name
Test status
Simulation time 20132439849 ps
CPU time 110.78 seconds
Started Mar 26 12:30:32 PM PDT 24
Finished Mar 26 12:32:24 PM PDT 24
Peak memory 197964 kb
Host smart-9f0c5050-2b0e-4c5c-8d7f-6fd03a81073b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806182603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1806182603
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.945061820
Short name T449
Test name
Test status
Simulation time 13103941 ps
CPU time 0.55 seconds
Started Mar 26 12:30:31 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 193972 kb
Host smart-b97d18f7-795f-4747-8488-4c4481bebd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945061820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.945061820
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1666945108
Short name T709
Test name
Test status
Simulation time 77948795 ps
CPU time 0.69 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 194868 kb
Host smart-59c2f5a5-02c7-45e5-bedc-5f5a301ab349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666945108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1666945108
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3400381779
Short name T202
Test name
Test status
Simulation time 583157194 ps
CPU time 15.25 seconds
Started Mar 26 12:30:35 PM PDT 24
Finished Mar 26 12:30:50 PM PDT 24
Peak memory 196464 kb
Host smart-0d9356e8-894f-4064-9880-a197269898e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400381779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3400381779
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2289674558
Short name T250
Test name
Test status
Simulation time 38080348 ps
CPU time 0.72 seconds
Started Mar 26 12:30:32 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 195664 kb
Host smart-9b2c370d-fe20-4a27-921f-66186779aabf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289674558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2289674558
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2682980907
Short name T274
Test name
Test status
Simulation time 63718340 ps
CPU time 0.7 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 195216 kb
Host smart-7c3e1c35-1e1a-4635-8e90-b82c8f0f76d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682980907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2682980907
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.134749740
Short name T220
Test name
Test status
Simulation time 198604048 ps
CPU time 1.43 seconds
Started Mar 26 12:30:35 PM PDT 24
Finished Mar 26 12:30:37 PM PDT 24
Peak memory 197856 kb
Host smart-7baea267-104b-4582-a7c3-a516aad19409
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134749740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.134749740
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1604349842
Short name T343
Test name
Test status
Simulation time 102250420 ps
CPU time 2.07 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:36 PM PDT 24
Peak memory 197768 kb
Host smart-33636aec-fe2e-4aa3-8432-9486ac90e487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604349842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1604349842
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3884061598
Short name T177
Test name
Test status
Simulation time 72410070 ps
CPU time 0.67 seconds
Started Mar 26 12:30:35 PM PDT 24
Finished Mar 26 12:30:36 PM PDT 24
Peak memory 195244 kb
Host smart-fc2d041b-733d-4120-9390-279f66186420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884061598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3884061598
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1293163578
Short name T191
Test name
Test status
Simulation time 85872804 ps
CPU time 1.11 seconds
Started Mar 26 12:30:32 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 197940 kb
Host smart-ba7cb560-ecc1-46b7-b207-d189f026220b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293163578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1293163578
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1043451613
Short name T302
Test name
Test status
Simulation time 73650943 ps
CPU time 1.69 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:36 PM PDT 24
Peak memory 197804 kb
Host smart-44f57ab6-7900-4fda-a35e-316ce71387e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043451613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1043451613
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.557048415
Short name T298
Test name
Test status
Simulation time 88709145 ps
CPU time 1.18 seconds
Started Mar 26 12:30:32 PM PDT 24
Finished Mar 26 12:30:33 PM PDT 24
Peak memory 195644 kb
Host smart-d4e5fe5e-70e3-485d-83b3-d135c2c31200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557048415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.557048415
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2830307421
Short name T384
Test name
Test status
Simulation time 110897459 ps
CPU time 0.89 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 196376 kb
Host smart-4dc95d0e-cbce-427f-8b7a-08ba24537aff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830307421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2830307421
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1306178589
Short name T4
Test name
Test status
Simulation time 3169696293 ps
CPU time 36.05 seconds
Started Mar 26 12:30:32 PM PDT 24
Finished Mar 26 12:31:09 PM PDT 24
Peak memory 198096 kb
Host smart-f9aea06e-50cd-4e6a-ae81-499463b2e29d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306178589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1306178589
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4265947235
Short name T185
Test name
Test status
Simulation time 76216913 ps
CPU time 0.54 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 193776 kb
Host smart-ea605a25-066f-4eaa-b491-e6c4eb3f45a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265947235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4265947235
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3424183743
Short name T287
Test name
Test status
Simulation time 36494834 ps
CPU time 0.6 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 193940 kb
Host smart-70602cde-3ede-4187-93b1-ce064f9f7752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424183743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3424183743
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3012602630
Short name T236
Test name
Test status
Simulation time 494416917 ps
CPU time 14.24 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:47 PM PDT 24
Peak memory 197844 kb
Host smart-8e03ca01-a2c9-492e-b7cd-078f1d288a8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012602630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3012602630
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2606833506
Short name T317
Test name
Test status
Simulation time 292119719 ps
CPU time 0.88 seconds
Started Mar 26 12:30:58 PM PDT 24
Finished Mar 26 12:30:59 PM PDT 24
Peak memory 197184 kb
Host smart-71f4530b-5188-4933-83f1-1242e5758504
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606833506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2606833506
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3716683091
Short name T30
Test name
Test status
Simulation time 19665495 ps
CPU time 0.66 seconds
Started Mar 26 12:30:35 PM PDT 24
Finished Mar 26 12:30:36 PM PDT 24
Peak memory 194908 kb
Host smart-7bfd5338-d977-4afb-9e1e-e962b3ae87dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716683091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3716683091
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3142117714
Short name T574
Test name
Test status
Simulation time 373041409 ps
CPU time 3.4 seconds
Started Mar 26 12:30:31 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 197908 kb
Host smart-d45def41-7172-4c57-9688-5df3e124f893
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142117714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3142117714
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2817203403
Short name T325
Test name
Test status
Simulation time 411142857 ps
CPU time 2.94 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:37 PM PDT 24
Peak memory 197096 kb
Host smart-17e7289c-1f55-421e-a3f6-df3cd3f21274
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817203403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2817203403
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1690926696
Short name T363
Test name
Test status
Simulation time 34343112 ps
CPU time 1.14 seconds
Started Mar 26 12:30:35 PM PDT 24
Finished Mar 26 12:30:37 PM PDT 24
Peak memory 196876 kb
Host smart-4d799260-1d08-4593-a174-4820d4d8a721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690926696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1690926696
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.31351579
Short name T251
Test name
Test status
Simulation time 49358550 ps
CPU time 0.94 seconds
Started Mar 26 12:30:37 PM PDT 24
Finished Mar 26 12:30:38 PM PDT 24
Peak memory 195724 kb
Host smart-2a72d7e3-eb44-4b7f-ad7f-9167d416e031
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31351579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup_
pulldown.31351579
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_smoke.1955524305
Short name T337
Test name
Test status
Simulation time 188934976 ps
CPU time 0.92 seconds
Started Mar 26 12:30:33 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 196264 kb
Host smart-a1a8931f-e372-46dc-af65-a591ab225e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955524305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1955524305
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.850542507
Short name T461
Test name
Test status
Simulation time 59011338 ps
CPU time 1 seconds
Started Mar 26 12:30:34 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 195412 kb
Host smart-f4b6f1d9-725b-44fe-b750-a9b72f85346e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850542507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.850542507
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2779992526
Short name T194
Test name
Test status
Simulation time 31404137927 ps
CPU time 190.37 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:34:01 PM PDT 24
Peak memory 198000 kb
Host smart-8487421c-4432-4467-9ed5-c50d797b3e3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779992526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2779992526
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2693052920
Short name T398
Test name
Test status
Simulation time 12851610 ps
CPU time 0.56 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 193820 kb
Host smart-de171c02-ff9f-4e71-9434-e485d9d1dee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693052920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2693052920
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2374498821
Short name T628
Test name
Test status
Simulation time 26841098 ps
CPU time 0.7 seconds
Started Mar 26 12:30:56 PM PDT 24
Finished Mar 26 12:30:57 PM PDT 24
Peak memory 195192 kb
Host smart-a7fd56aa-4f25-438d-9376-4fd720302c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374498821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2374498821
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2811190239
Short name T233
Test name
Test status
Simulation time 923907734 ps
CPU time 13.66 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 196504 kb
Host smart-33b1d79f-a8ac-4c95-b6a2-9c8aeb488b2f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811190239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2811190239
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1600901654
Short name T54
Test name
Test status
Simulation time 61931890 ps
CPU time 0.92 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 197596 kb
Host smart-e99ccdb9-910e-457a-bbd8-08319f8c7be2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600901654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1600901654
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.954143094
Short name T610
Test name
Test status
Simulation time 63403280 ps
CPU time 0.74 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 195420 kb
Host smart-61348ad2-77f2-4412-98e2-b041ed788ba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954143094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.954143094
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1427151514
Short name T706
Test name
Test status
Simulation time 85467498 ps
CPU time 1.68 seconds
Started Mar 26 12:30:54 PM PDT 24
Finished Mar 26 12:30:58 PM PDT 24
Peak memory 197976 kb
Host smart-b2d5c26e-1a2b-4e68-b00b-f485383e8698
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427151514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1427151514
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2958514682
Short name T450
Test name
Test status
Simulation time 523581898 ps
CPU time 2.97 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:55 PM PDT 24
Peak memory 197152 kb
Host smart-cd724c36-72fa-4560-9e94-b60b53429c3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958514682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2958514682
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.4093015208
Short name T658
Test name
Test status
Simulation time 79171510 ps
CPU time 1.25 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 196764 kb
Host smart-3a814a3b-2abe-4d53-8ac1-a6fa6320c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093015208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.4093015208
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1866520777
Short name T455
Test name
Test status
Simulation time 116439527 ps
CPU time 1.22 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 195712 kb
Host smart-ee398dc2-f08f-4495-b353-2696e8941af4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866520777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1866520777
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.922672541
Short name T239
Test name
Test status
Simulation time 939381012 ps
CPU time 4.61 seconds
Started Mar 26 12:30:55 PM PDT 24
Finished Mar 26 12:31:01 PM PDT 24
Peak memory 197844 kb
Host smart-9d685c54-2da9-4f2d-8ae6-0eacc327b910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922672541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.922672541
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.601425904
Short name T258
Test name
Test status
Simulation time 62333509 ps
CPU time 1.17 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 196452 kb
Host smart-8f55bff4-f626-47af-bdc9-dbbd970ebbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601425904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.601425904
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.239917159
Short name T234
Test name
Test status
Simulation time 71207743 ps
CPU time 1.04 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 195508 kb
Host smart-230a20ef-a9e2-49bb-8ae9-4c9a90e2835f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239917159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.239917159
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.4171767045
Short name T460
Test name
Test status
Simulation time 16437373645 ps
CPU time 162.37 seconds
Started Mar 26 12:30:55 PM PDT 24
Finished Mar 26 12:33:38 PM PDT 24
Peak memory 198044 kb
Host smart-b7282945-665e-41a1-a89f-f915bbb923ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171767045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.4171767045
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1421713072
Short name T607
Test name
Test status
Simulation time 14894701 ps
CPU time 0.59 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 194440 kb
Host smart-4c0896c2-0098-4b71-ae0f-cfcb395e63a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421713072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1421713072
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2098627769
Short name T625
Test name
Test status
Simulation time 141510346 ps
CPU time 0.84 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 197272 kb
Host smart-fe1489b5-bd63-4c81-afd6-51ca0732fd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098627769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2098627769
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1847251824
Short name T170
Test name
Test status
Simulation time 913253252 ps
CPU time 22.06 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 196108 kb
Host smart-1e78ef73-b452-4149-82b6-738d68623aa6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847251824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1847251824
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1577315189
Short name T111
Test name
Test status
Simulation time 34225362 ps
CPU time 0.64 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 194600 kb
Host smart-8a1c0fde-f9d8-4f2e-9a2c-e5dd3538267c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577315189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1577315189
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1681232177
Short name T26
Test name
Test status
Simulation time 71840383 ps
CPU time 1.01 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 195620 kb
Host smart-82f582ea-754a-4463-ba2d-5ea313a808fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681232177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1681232177
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1236577930
Short name T107
Test name
Test status
Simulation time 777703842 ps
CPU time 1.98 seconds
Started Mar 26 12:30:55 PM PDT 24
Finished Mar 26 12:30:58 PM PDT 24
Peak memory 197940 kb
Host smart-1f2254e7-c998-4a38-92e1-33d06e8ef1e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236577930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1236577930
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.752464720
Short name T198
Test name
Test status
Simulation time 42709127 ps
CPU time 1.3 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 195640 kb
Host smart-67760122-6994-45c3-a34a-aee157d35b46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752464720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
752464720
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2894273928
Short name T652
Test name
Test status
Simulation time 58973441 ps
CPU time 1.2 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 197044 kb
Host smart-d6e366fb-a7ec-4e56-8d7f-bd20da8c9f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894273928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2894273928
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.313464084
Short name T16
Test name
Test status
Simulation time 132133869 ps
CPU time 0.97 seconds
Started Mar 26 12:30:53 PM PDT 24
Finished Mar 26 12:30:56 PM PDT 24
Peak memory 195780 kb
Host smart-cfa00ed2-bf8e-471e-bc6d-b05768b86352
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313464084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.313464084
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.875800502
Short name T9
Test name
Test status
Simulation time 267286972 ps
CPU time 3.19 seconds
Started Mar 26 12:30:53 PM PDT 24
Finished Mar 26 12:30:56 PM PDT 24
Peak memory 197864 kb
Host smart-e1fde067-f241-479d-8b5e-a67330206b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875800502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.875800502
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2526863364
Short name T425
Test name
Test status
Simulation time 25410377 ps
CPU time 0.83 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 196268 kb
Host smart-450df96d-0711-4037-bda3-dccdb949b132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526863364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2526863364
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3397467350
Short name T521
Test name
Test status
Simulation time 143893221 ps
CPU time 1.46 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 198120 kb
Host smart-cc4407a9-28ed-4f49-bd9e-6d63a626f721
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397467350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3397467350
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1316151562
Short name T18
Test name
Test status
Simulation time 32511513940 ps
CPU time 187.44 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:33:59 PM PDT 24
Peak memory 198080 kb
Host smart-76805beb-51a7-44e2-ab8d-2dd5eeb6b0a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316151562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1316151562
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3690092678
Short name T542
Test name
Test status
Simulation time 27118831 ps
CPU time 0.57 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 195588 kb
Host smart-dbe87685-7203-4a88-8168-478bfb071079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690092678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3690092678
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3453298559
Short name T333
Test name
Test status
Simulation time 20698513 ps
CPU time 0.66 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 194636 kb
Host smart-67b2b1d4-aaae-4191-8863-5aa66eb395b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453298559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3453298559
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3515598217
Short name T17
Test name
Test status
Simulation time 6368402621 ps
CPU time 20.88 seconds
Started Mar 26 12:30:57 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 198048 kb
Host smart-6a1cc6a2-2b59-4f55-b616-c358d6b657c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515598217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3515598217
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1983256834
Short name T187
Test name
Test status
Simulation time 17122468 ps
CPU time 0.61 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 194248 kb
Host smart-64672187-6a30-4e8c-9e1d-46a6bf4a99c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983256834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1983256834
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.994128966
Short name T622
Test name
Test status
Simulation time 31690569 ps
CPU time 0.79 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 195552 kb
Host smart-27cb39e2-8c00-44c6-841c-6f021f6eee09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994128966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.994128966
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3464004947
Short name T476
Test name
Test status
Simulation time 62495774 ps
CPU time 2.24 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:54 PM PDT 24
Peak memory 197848 kb
Host smart-74855905-a3b3-4928-9aec-be48266ad692
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464004947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3464004947
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3733175270
Short name T259
Test name
Test status
Simulation time 79691646 ps
CPU time 1.67 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 195672 kb
Host smart-19e82ea7-bab0-437a-adcb-3c02e870ab6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733175270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3733175270
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3090923171
Short name T672
Test name
Test status
Simulation time 44319309 ps
CPU time 0.68 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 194200 kb
Host smart-088b1e26-17ce-4235-829e-11a2f7a86ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090923171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3090923171
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3957084667
Short name T602
Test name
Test status
Simulation time 116438079 ps
CPU time 0.91 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 195824 kb
Host smart-0a5fc3c5-1322-47e8-af34-b6a8bdecf7e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957084667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3957084667
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2840391620
Short name T151
Test name
Test status
Simulation time 920770869 ps
CPU time 2.12 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 197796 kb
Host smart-79a31080-3b58-41f9-8faf-85cd5db9f891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840391620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2840391620
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2486630185
Short name T356
Test name
Test status
Simulation time 395797508 ps
CPU time 0.83 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 196040 kb
Host smart-3faa8a49-afa0-4e68-a481-ddb151645f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486630185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2486630185
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1100683185
Short name T664
Test name
Test status
Simulation time 39975800 ps
CPU time 1.1 seconds
Started Mar 26 12:30:56 PM PDT 24
Finished Mar 26 12:30:57 PM PDT 24
Peak memory 195636 kb
Host smart-399f79bf-18ac-44eb-8761-36a026b1bde8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100683185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1100683185
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.595528263
Short name T5
Test name
Test status
Simulation time 80228640832 ps
CPU time 84.77 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:32:15 PM PDT 24
Peak memory 197988 kb
Host smart-cb1ade49-d9e4-4dfb-87be-72dbc3bb253a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595528263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.595528263
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2776320375
Short name T64
Test name
Test status
Simulation time 40853431232 ps
CPU time 314.22 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:36:05 PM PDT 24
Peak memory 198140 kb
Host smart-79caff90-a605-4067-b947-c7eecbba1bfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2776320375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2776320375
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.26674143
Short name T662
Test name
Test status
Simulation time 16439834 ps
CPU time 0.55 seconds
Started Mar 26 12:30:53 PM PDT 24
Finished Mar 26 12:30:54 PM PDT 24
Peak memory 193948 kb
Host smart-8b21c978-6296-4867-aa46-d8731d9e2960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26674143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.26674143
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2151755546
Short name T152
Test name
Test status
Simulation time 62777810 ps
CPU time 0.89 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 196320 kb
Host smart-a342f4c7-de15-49b1-9b4f-a7eba281734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151755546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2151755546
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1141095013
Short name T173
Test name
Test status
Simulation time 773172714 ps
CPU time 20.4 seconds
Started Mar 26 12:30:49 PM PDT 24
Finished Mar 26 12:31:10 PM PDT 24
Peak memory 197800 kb
Host smart-664c38ba-dfcd-49b1-97d6-a689630fb7a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141095013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1141095013
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2666987685
Short name T609
Test name
Test status
Simulation time 20003702 ps
CPU time 0.58 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 195232 kb
Host smart-4f385e95-c68d-4636-b162-385ef1a7529c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666987685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2666987685
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2272043313
Short name T614
Test name
Test status
Simulation time 177717295 ps
CPU time 1.01 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 196468 kb
Host smart-763bfa51-603e-4b62-8024-a84fa58777d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272043313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2272043313
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2803713637
Short name T445
Test name
Test status
Simulation time 25475668 ps
CPU time 1.06 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 196160 kb
Host smart-4df587f4-ccca-44b5-8941-fcc762de541a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803713637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2803713637
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2231855678
Short name T282
Test name
Test status
Simulation time 69434795 ps
CPU time 1.61 seconds
Started Mar 26 12:30:56 PM PDT 24
Finished Mar 26 12:30:58 PM PDT 24
Peak memory 195588 kb
Host smart-1c438161-4c3b-4f62-8b3c-e536b6f20fbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231855678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2231855678
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.555186266
Short name T358
Test name
Test status
Simulation time 110232925 ps
CPU time 1.01 seconds
Started Mar 26 12:30:54 PM PDT 24
Finished Mar 26 12:30:57 PM PDT 24
Peak memory 196352 kb
Host smart-b59d4a41-66f8-4f04-a4d4-13ceaab175ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555186266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.555186266
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1947422071
Short name T547
Test name
Test status
Simulation time 52895148 ps
CPU time 1.1 seconds
Started Mar 26 12:30:54 PM PDT 24
Finished Mar 26 12:30:56 PM PDT 24
Peak memory 195784 kb
Host smart-086478c5-7aec-4216-a0e3-318f45ea52c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947422071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1947422071
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1272878829
Short name T354
Test name
Test status
Simulation time 1169832331 ps
CPU time 3.83 seconds
Started Mar 26 12:30:51 PM PDT 24
Finished Mar 26 12:30:55 PM PDT 24
Peak memory 197844 kb
Host smart-34d6334a-6d5a-4d5c-8abe-5fb10476834b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272878829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1272878829
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2255573030
Short name T490
Test name
Test status
Simulation time 40534399 ps
CPU time 1.02 seconds
Started Mar 26 12:30:53 PM PDT 24
Finished Mar 26 12:30:55 PM PDT 24
Peak memory 195620 kb
Host smart-f9300527-0214-477f-8784-4e5120a0a73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255573030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2255573030
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2325213528
Short name T188
Test name
Test status
Simulation time 174567523 ps
CPU time 1.21 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 196584 kb
Host smart-ad2ddb4e-8253-4948-a123-63ce2b48b497
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325213528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2325213528
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2296095097
Short name T668
Test name
Test status
Simulation time 61930273911 ps
CPU time 173.43 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:33:45 PM PDT 24
Peak memory 198060 kb
Host smart-5a1cd93f-2fb7-43d0-9baf-3c363ee342b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296095097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2296095097
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3200125116
Short name T500
Test name
Test status
Simulation time 113948731442 ps
CPU time 844.4 seconds
Started Mar 26 12:30:54 PM PDT 24
Finished Mar 26 12:45:00 PM PDT 24
Peak memory 206288 kb
Host smart-b761615a-26ca-4331-9b45-beb71b1b4fb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3200125116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3200125116
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2267864007
Short name T307
Test name
Test status
Simulation time 37480395 ps
CPU time 0.57 seconds
Started Mar 26 12:30:53 PM PDT 24
Finished Mar 26 12:30:54 PM PDT 24
Peak memory 193808 kb
Host smart-cbac6a4e-1e6c-4f1c-9ba3-71b6d7c47371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267864007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2267864007
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.810594625
Short name T253
Test name
Test status
Simulation time 99034446 ps
CPU time 0.7 seconds
Started Mar 26 12:30:54 PM PDT 24
Finished Mar 26 12:30:57 PM PDT 24
Peak memory 194128 kb
Host smart-c877fd59-f832-4649-80ae-3584ae9e0e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810594625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.810594625
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.130838082
Short name T109
Test name
Test status
Simulation time 186109229 ps
CPU time 5.03 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:58 PM PDT 24
Peak memory 196760 kb
Host smart-0ebc386c-0ad2-4a5a-a86c-6bd89370792f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130838082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.130838082
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3112182344
Short name T679
Test name
Test status
Simulation time 304485451 ps
CPU time 0.98 seconds
Started Mar 26 12:30:58 PM PDT 24
Finished Mar 26 12:30:59 PM PDT 24
Peak memory 196284 kb
Host smart-e9cd5f29-d0e2-4529-bb81-eaab55212c3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112182344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3112182344
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.230544307
Short name T134
Test name
Test status
Simulation time 208503070 ps
CPU time 1.07 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 196376 kb
Host smart-4434271b-51a4-472e-a0d3-eb4f099307ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230544307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.230544307
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2784101798
Short name T708
Test name
Test status
Simulation time 22565136 ps
CPU time 1.08 seconds
Started Mar 26 12:30:50 PM PDT 24
Finished Mar 26 12:30:51 PM PDT 24
Peak memory 196240 kb
Host smart-fd1ad7d9-cc8b-4fae-a7bd-62d5b9cf7a15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784101798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2784101798
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2851484020
Short name T571
Test name
Test status
Simulation time 64206843 ps
CPU time 1.55 seconds
Started Mar 26 12:30:54 PM PDT 24
Finished Mar 26 12:30:57 PM PDT 24
Peak memory 195764 kb
Host smart-f723d43c-bf37-4c56-a1e0-49df77a65422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851484020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2851484020
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.504354237
Short name T431
Test name
Test status
Simulation time 63827571 ps
CPU time 0.8 seconds
Started Mar 26 12:30:54 PM PDT 24
Finished Mar 26 12:30:57 PM PDT 24
Peak memory 196384 kb
Host smart-c1398150-9ac7-4ce5-a670-47cceb6565d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504354237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.504354237
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3793611688
Short name T692
Test name
Test status
Simulation time 61912576 ps
CPU time 1.17 seconds
Started Mar 26 12:30:53 PM PDT 24
Finished Mar 26 12:30:54 PM PDT 24
Peak memory 196764 kb
Host smart-6d1fbf42-78ad-4a72-bc08-ad28dc504421
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793611688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3793611688
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1145734726
Short name T473
Test name
Test status
Simulation time 125797168 ps
CPU time 5.56 seconds
Started Mar 26 12:30:59 PM PDT 24
Finished Mar 26 12:31:04 PM PDT 24
Peak memory 197808 kb
Host smart-da155e70-712a-4096-a82b-d025333ec425
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145734726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1145734726
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.19254742
Short name T617
Test name
Test status
Simulation time 278274270 ps
CPU time 0.9 seconds
Started Mar 26 12:30:54 PM PDT 24
Finished Mar 26 12:30:57 PM PDT 24
Peak memory 196352 kb
Host smart-ee3e3a71-64bf-444e-b2a1-dd98565b96ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19254742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.19254742
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.678798199
Short name T681
Test name
Test status
Simulation time 384557767 ps
CPU time 1.08 seconds
Started Mar 26 12:30:53 PM PDT 24
Finished Mar 26 12:30:55 PM PDT 24
Peak memory 195620 kb
Host smart-79a7e7be-1649-42c7-95a3-2cfcdf989f1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678798199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.678798199
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3494900771
Short name T270
Test name
Test status
Simulation time 19689440364 ps
CPU time 135.37 seconds
Started Mar 26 12:30:52 PM PDT 24
Finished Mar 26 12:33:07 PM PDT 24
Peak memory 198020 kb
Host smart-12a02242-b445-4a94-89a0-2ef94a050502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494900771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3494900771
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.4142714013
Short name T447
Test name
Test status
Simulation time 51056152473 ps
CPU time 710.73 seconds
Started Mar 26 12:30:58 PM PDT 24
Finished Mar 26 12:42:49 PM PDT 24
Peak memory 198152 kb
Host smart-8940c64a-6ade-4499-8957-2003476a3df0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4142714013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.4142714013
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3393951223
Short name T472
Test name
Test status
Simulation time 35861972 ps
CPU time 0.58 seconds
Started Mar 26 12:31:02 PM PDT 24
Finished Mar 26 12:31:03 PM PDT 24
Peak memory 193836 kb
Host smart-392a4fb5-3e73-4e68-9388-f71baed51195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393951223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3393951223
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3539029974
Short name T348
Test name
Test status
Simulation time 33957182 ps
CPU time 0.88 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 195760 kb
Host smart-f18eb412-ae76-4393-a79a-7499d3a88b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539029974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3539029974
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.910334242
Short name T529
Test name
Test status
Simulation time 2812295337 ps
CPU time 23.28 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 196884 kb
Host smart-0ce0003e-c842-498c-8c04-9c930735cb24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910334242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.910334242
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2073164453
Short name T613
Test name
Test status
Simulation time 57078268 ps
CPU time 0.6 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 194608 kb
Host smart-733c3af4-1604-4a67-97da-420befebd5df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073164453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2073164453
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.98335636
Short name T397
Test name
Test status
Simulation time 360983892 ps
CPU time 0.87 seconds
Started Mar 26 12:31:01 PM PDT 24
Finished Mar 26 12:31:02 PM PDT 24
Peak memory 196476 kb
Host smart-3baeb692-2fa9-4cb4-90be-f457fbb2c18f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98335636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.98335636
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1028649493
Short name T237
Test name
Test status
Simulation time 182114264 ps
CPU time 2.51 seconds
Started Mar 26 12:31:05 PM PDT 24
Finished Mar 26 12:31:08 PM PDT 24
Peak memory 197372 kb
Host smart-1469cb87-d9a1-4704-9589-40c56b915564
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028649493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1028649493
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4287484460
Short name T361
Test name
Test status
Simulation time 102602249 ps
CPU time 1.01 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:15 PM PDT 24
Peak memory 196404 kb
Host smart-582aa68e-7a7d-46fe-94d3-17c8972b81a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287484460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4287484460
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1868418190
Short name T128
Test name
Test status
Simulation time 30538406 ps
CPU time 1.21 seconds
Started Mar 26 12:31:00 PM PDT 24
Finished Mar 26 12:31:03 PM PDT 24
Peak memory 197116 kb
Host smart-a0804b38-9819-465d-9217-028d4e507c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868418190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1868418190
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2851847061
Short name T14
Test name
Test status
Simulation time 21691513 ps
CPU time 0.68 seconds
Started Mar 26 12:30:58 PM PDT 24
Finished Mar 26 12:30:59 PM PDT 24
Peak memory 194776 kb
Host smart-addad65e-6430-4eac-8d24-e5436f3ab752
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851847061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2851847061
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3010086511
Short name T180
Test name
Test status
Simulation time 118407727 ps
CPU time 1.38 seconds
Started Mar 26 12:31:04 PM PDT 24
Finished Mar 26 12:31:05 PM PDT 24
Peak memory 197820 kb
Host smart-733f1658-921d-4e59-907a-28b018d756b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010086511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3010086511
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.908812131
Short name T470
Test name
Test status
Simulation time 388024396 ps
CPU time 0.91 seconds
Started Mar 26 12:30:57 PM PDT 24
Finished Mar 26 12:30:58 PM PDT 24
Peak memory 196108 kb
Host smart-f8555468-2a34-4bc6-b993-924ea50932cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908812131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.908812131
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.625008360
Short name T372
Test name
Test status
Simulation time 68178277 ps
CPU time 0.81 seconds
Started Mar 26 12:30:59 PM PDT 24
Finished Mar 26 12:31:01 PM PDT 24
Peak memory 195092 kb
Host smart-4495faec-cfc0-4377-83f2-865d7aaa5cd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625008360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.625008360
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3973890253
Short name T6
Test name
Test status
Simulation time 7278908294 ps
CPU time 81.58 seconds
Started Mar 26 12:31:02 PM PDT 24
Finished Mar 26 12:32:24 PM PDT 24
Peak memory 198088 kb
Host smart-711736fa-233c-4bf0-8cc7-bc9c95c18ad7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973890253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3973890253
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.606082983
Short name T252
Test name
Test status
Simulation time 16679883 ps
CPU time 0.58 seconds
Started Mar 26 12:31:01 PM PDT 24
Finished Mar 26 12:31:02 PM PDT 24
Peak memory 194728 kb
Host smart-08d469c7-ee5e-41b7-9425-4f47d104fa26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606082983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.606082983
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.635067381
Short name T630
Test name
Test status
Simulation time 22868918 ps
CPU time 0.72 seconds
Started Mar 26 12:31:00 PM PDT 24
Finished Mar 26 12:31:02 PM PDT 24
Peak memory 195204 kb
Host smart-fc242124-451f-4ece-8d84-c852af4ccc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635067381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.635067381
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.651224832
Short name T312
Test name
Test status
Simulation time 1022891966 ps
CPU time 18.23 seconds
Started Mar 26 12:31:05 PM PDT 24
Finished Mar 26 12:31:23 PM PDT 24
Peak memory 195360 kb
Host smart-1012915f-0353-4f17-8f1c-c7c67d428e17
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651224832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.651224832
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.710015754
Short name T117
Test name
Test status
Simulation time 106801172 ps
CPU time 0.6 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:05 PM PDT 24
Peak memory 194428 kb
Host smart-70b2954b-5ede-4482-a047-80d88ee4e6b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710015754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.710015754
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2256920108
Short name T689
Test name
Test status
Simulation time 117309439 ps
CPU time 0.65 seconds
Started Mar 26 12:31:05 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 195040 kb
Host smart-74e8ff9d-f051-4fa8-a974-17a0bd5d9877
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256920108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2256920108
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2651602997
Short name T277
Test name
Test status
Simulation time 55205004 ps
CPU time 1.23 seconds
Started Mar 26 12:31:02 PM PDT 24
Finished Mar 26 12:31:03 PM PDT 24
Peak memory 197724 kb
Host smart-a42e1953-a097-41f3-85f2-08c09c52b491
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651602997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2651602997
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.266772873
Short name T508
Test name
Test status
Simulation time 180506123 ps
CPU time 2.1 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 196464 kb
Host smart-0f8b1e09-1086-484f-ad4e-9abb6707de59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266772873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
266772873
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.780170043
Short name T346
Test name
Test status
Simulation time 292826892 ps
CPU time 0.64 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:05 PM PDT 24
Peak memory 194204 kb
Host smart-321b9dd1-fe8f-41a0-9166-04fb9417a8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780170043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.780170043
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1699572767
Short name T647
Test name
Test status
Simulation time 76414843 ps
CPU time 0.82 seconds
Started Mar 26 12:31:05 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 195300 kb
Host smart-5fe70df4-ae2b-4cde-a094-69e418a93264
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699572767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1699572767
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3865763021
Short name T68
Test name
Test status
Simulation time 624375279 ps
CPU time 3.51 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 197796 kb
Host smart-9229feb6-f816-4827-b571-9086a275398f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865763021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3865763021
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1135353790
Short name T440
Test name
Test status
Simulation time 64497934 ps
CPU time 1.3 seconds
Started Mar 26 12:31:01 PM PDT 24
Finished Mar 26 12:31:03 PM PDT 24
Peak memory 197004 kb
Host smart-a16ccc71-a428-40ce-90b0-6cd207933b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135353790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1135353790
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3032404250
Short name T565
Test name
Test status
Simulation time 721539764 ps
CPU time 1.29 seconds
Started Mar 26 12:31:01 PM PDT 24
Finished Mar 26 12:31:03 PM PDT 24
Peak memory 196504 kb
Host smart-89971fa6-2525-491d-b67e-4c25a3d811c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032404250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3032404250
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1196249479
Short name T345
Test name
Test status
Simulation time 106689627157 ps
CPU time 84.79 seconds
Started Mar 26 12:31:02 PM PDT 24
Finished Mar 26 12:32:27 PM PDT 24
Peak memory 198052 kb
Host smart-4b7fb61d-2487-43fc-9bf6-1b311aa7232b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196249479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1196249479
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3847010
Short name T267
Test name
Test status
Simulation time 14830704 ps
CPU time 0.58 seconds
Started Mar 26 12:29:43 PM PDT 24
Finished Mar 26 12:29:43 PM PDT 24
Peak memory 193980 kb
Host smart-6b1a9a10-7d71-47ee-883b-6f24c23cdb9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3847010
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1506751927
Short name T582
Test name
Test status
Simulation time 66480909 ps
CPU time 0.64 seconds
Started Mar 26 12:29:36 PM PDT 24
Finished Mar 26 12:29:37 PM PDT 24
Peak memory 194020 kb
Host smart-235c2e09-2b7c-4e5c-8207-45ff30292fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506751927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1506751927
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.635486159
Short name T511
Test name
Test status
Simulation time 1862158643 ps
CPU time 9.89 seconds
Started Mar 26 12:29:44 PM PDT 24
Finished Mar 26 12:29:54 PM PDT 24
Peak memory 198252 kb
Host smart-675d4ffb-5a3c-453b-b7ce-7c552efb23fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635486159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.635486159
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1523611765
Short name T262
Test name
Test status
Simulation time 75439893 ps
CPU time 0.62 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:47 PM PDT 24
Peak memory 195248 kb
Host smart-af96d7c9-4729-4be9-97b0-99c938883ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523611765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1523611765
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.56947571
Short name T713
Test name
Test status
Simulation time 103032452 ps
CPU time 0.73 seconds
Started Mar 26 12:29:44 PM PDT 24
Finished Mar 26 12:29:45 PM PDT 24
Peak memory 195992 kb
Host smart-491519b9-ca76-4e10-b46e-484863b45ed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56947571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.56947571
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1943794155
Short name T459
Test name
Test status
Simulation time 40295449 ps
CPU time 1.56 seconds
Started Mar 26 12:29:42 PM PDT 24
Finished Mar 26 12:29:44 PM PDT 24
Peak memory 196168 kb
Host smart-e5005de2-385b-4b09-a365-028fc9b2d80a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943794155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1943794155
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3514338556
Short name T257
Test name
Test status
Simulation time 143308470 ps
CPU time 3.13 seconds
Started Mar 26 12:29:46 PM PDT 24
Finished Mar 26 12:29:50 PM PDT 24
Peak memory 197240 kb
Host smart-2aca8ca8-f5e7-4dd1-bbf5-ba591cf21d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514338556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3514338556
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.554691657
Short name T682
Test name
Test status
Simulation time 16041301 ps
CPU time 0.64 seconds
Started Mar 26 12:29:34 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 194204 kb
Host smart-e2a55329-4a01-47d2-8eb2-61ef8aff6273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554691657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.554691657
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3054280110
Short name T142
Test name
Test status
Simulation time 51662700 ps
CPU time 1.03 seconds
Started Mar 26 12:29:33 PM PDT 24
Finished Mar 26 12:29:34 PM PDT 24
Peak memory 195768 kb
Host smart-7254f6cf-4b67-4da1-8207-6ab8a3979122
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054280110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3054280110
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4283298464
Short name T2
Test name
Test status
Simulation time 369263494 ps
CPU time 4.54 seconds
Started Mar 26 12:29:43 PM PDT 24
Finished Mar 26 12:29:47 PM PDT 24
Peak memory 197816 kb
Host smart-f6e0a803-c45e-42e6-9c08-8b7d68a00366
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283298464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4283298464
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1092923731
Short name T39
Test name
Test status
Simulation time 250660904 ps
CPU time 0.85 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 213556 kb
Host smart-731ad75e-940f-4a6e-9572-4d3759760bda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092923731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1092923731
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1906273568
Short name T489
Test name
Test status
Simulation time 271256709 ps
CPU time 0.91 seconds
Started Mar 26 12:29:33 PM PDT 24
Finished Mar 26 12:29:35 PM PDT 24
Peak memory 195336 kb
Host smart-569ff973-bb57-4817-9ac2-fb811a627982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906273568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1906273568
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1826274141
Short name T178
Test name
Test status
Simulation time 55123456 ps
CPU time 1.11 seconds
Started Mar 26 12:29:33 PM PDT 24
Finished Mar 26 12:29:35 PM PDT 24
Peak memory 195448 kb
Host smart-ff5700d8-a2f0-494c-a344-641cf0c7eb68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826274141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1826274141
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3900057515
Short name T707
Test name
Test status
Simulation time 4612311694 ps
CPU time 104.6 seconds
Started Mar 26 12:29:45 PM PDT 24
Finished Mar 26 12:31:30 PM PDT 24
Peak memory 198096 kb
Host smart-5a7f751c-9f80-4dc5-be9f-e6045956bf0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900057515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3900057515
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3001890264
Short name T65
Test name
Test status
Simulation time 19357941149 ps
CPU time 649.79 seconds
Started Mar 26 12:29:43 PM PDT 24
Finished Mar 26 12:40:33 PM PDT 24
Peak memory 198068 kb
Host smart-d71a4415-e764-4d8f-b87d-622ab96df8fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3001890264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3001890264
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1086301895
Short name T540
Test name
Test status
Simulation time 23570359 ps
CPU time 0.66 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:04 PM PDT 24
Peak memory 193916 kb
Host smart-cfd8ba3d-f9ce-475e-8a93-02cfeae91ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086301895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1086301895
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2846386722
Short name T127
Test name
Test status
Simulation time 43821781 ps
CPU time 0.59 seconds
Started Mar 26 12:31:04 PM PDT 24
Finished Mar 26 12:31:05 PM PDT 24
Peak memory 193680 kb
Host smart-bbbda76e-df3e-4560-a3e7-2f0a44ebae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846386722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2846386722
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1279901069
Short name T328
Test name
Test status
Simulation time 624047133 ps
CPU time 20.1 seconds
Started Mar 26 12:31:01 PM PDT 24
Finished Mar 26 12:31:22 PM PDT 24
Peak memory 195376 kb
Host smart-13b496f3-0a8c-4021-9593-464a0fefaec3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279901069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1279901069
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2654297432
Short name T523
Test name
Test status
Simulation time 125789701 ps
CPU time 0.61 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 194416 kb
Host smart-288b06bb-0793-48d7-9abd-0bb4893d4ca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654297432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2654297432
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2753583184
Short name T249
Test name
Test status
Simulation time 107695280 ps
CPU time 1.09 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:05 PM PDT 24
Peak memory 196680 kb
Host smart-04702c50-b01e-4603-87e7-ccda01bb4570
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753583184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2753583184
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.432565735
Short name T362
Test name
Test status
Simulation time 94115253 ps
CPU time 3.56 seconds
Started Mar 26 12:31:02 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 197972 kb
Host smart-36a1580a-7367-4398-8fc6-aaf07c67680d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432565735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.432565735
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1155207109
Short name T255
Test name
Test status
Simulation time 347228364 ps
CPU time 2.62 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:09 PM PDT 24
Peak memory 197952 kb
Host smart-67b7e80f-5133-4fa6-8802-be1534ef3195
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155207109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1155207109
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.822764644
Short name T200
Test name
Test status
Simulation time 167957251 ps
CPU time 1.12 seconds
Started Mar 26 12:31:05 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 197836 kb
Host smart-683e4249-205c-4d37-8bc2-78b0f650e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822764644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.822764644
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2418344517
Short name T145
Test name
Test status
Simulation time 64825032 ps
CPU time 0.83 seconds
Started Mar 26 12:31:02 PM PDT 24
Finished Mar 26 12:31:03 PM PDT 24
Peak memory 196356 kb
Host smart-12cd762c-529b-48a3-8cbf-7f93fe486d1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418344517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2418344517
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1325277281
Short name T179
Test name
Test status
Simulation time 624901377 ps
CPU time 3.52 seconds
Started Mar 26 12:31:04 PM PDT 24
Finished Mar 26 12:31:08 PM PDT 24
Peak memory 197888 kb
Host smart-d77af29a-1f17-4e00-aaea-6a5d049274e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325277281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1325277281
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2190727904
Short name T369
Test name
Test status
Simulation time 43547992 ps
CPU time 1.03 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 195608 kb
Host smart-a18f59c1-5eaa-45fc-91ca-ed5b87fa9085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190727904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2190727904
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3793937949
Short name T562
Test name
Test status
Simulation time 120088257 ps
CPU time 1.11 seconds
Started Mar 26 12:31:00 PM PDT 24
Finished Mar 26 12:31:03 PM PDT 24
Peak memory 195312 kb
Host smart-a62b80fe-e3bc-43b1-98a7-2e8ca113640e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793937949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3793937949
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1245940286
Short name T530
Test name
Test status
Simulation time 17148082086 ps
CPU time 111.27 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:32:57 PM PDT 24
Peak memory 198000 kb
Host smart-1407660d-1928-4a36-b083-0ec612b692d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245940286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1245940286
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1991178080
Short name T59
Test name
Test status
Simulation time 21035906024 ps
CPU time 611.77 seconds
Started Mar 26 12:31:02 PM PDT 24
Finished Mar 26 12:41:15 PM PDT 24
Peak memory 198104 kb
Host smart-c32ef00f-0498-4227-91d8-257eb7d91013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1991178080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1991178080
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2207529827
Short name T623
Test name
Test status
Simulation time 12611715 ps
CPU time 0.53 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 192644 kb
Host smart-8d8a3580-a5df-423a-ae9c-11d1409442f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207529827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2207529827
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1256165104
Short name T299
Test name
Test status
Simulation time 36939928 ps
CPU time 0.87 seconds
Started Mar 26 12:31:05 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 195776 kb
Host smart-54398341-7a11-42a8-a632-4ecc8a152724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256165104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1256165104
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.595945137
Short name T453
Test name
Test status
Simulation time 806471758 ps
CPU time 12.29 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:19 PM PDT 24
Peak memory 196140 kb
Host smart-9c5c61ce-f158-4260-940f-72bdef18675d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595945137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.595945137
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.352175173
Short name T601
Test name
Test status
Simulation time 76892140 ps
CPU time 0.68 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 194732 kb
Host smart-e1a6fd98-d442-4c86-9515-e4cd7b2df993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352175173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.352175173
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4024934225
Short name T466
Test name
Test status
Simulation time 123794684 ps
CPU time 1.08 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:31:08 PM PDT 24
Peak memory 195640 kb
Host smart-ae11d564-6b4e-4a9a-8a06-5692868895f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024934225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4024934225
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2570819422
Short name T158
Test name
Test status
Simulation time 234846878 ps
CPU time 2.35 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 197936 kb
Host smart-5613683a-e948-4989-9101-daf9ba276f22
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570819422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2570819422
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1717896192
Short name T138
Test name
Test status
Simulation time 253575572 ps
CPU time 2.29 seconds
Started Mar 26 12:31:01 PM PDT 24
Finished Mar 26 12:31:04 PM PDT 24
Peak memory 195652 kb
Host smart-b29f2d38-6d52-49cc-9510-d8059b8f1cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717896192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1717896192
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3361357321
Short name T56
Test name
Test status
Simulation time 72481978 ps
CPU time 1 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:05 PM PDT 24
Peak memory 196536 kb
Host smart-a8dfbc03-f272-459b-bb29-07248838c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361357321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3361357321
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4158691359
Short name T535
Test name
Test status
Simulation time 80841065 ps
CPU time 0.65 seconds
Started Mar 26 12:31:01 PM PDT 24
Finished Mar 26 12:31:02 PM PDT 24
Peak memory 194236 kb
Host smart-eda44a82-f6f9-49ae-bd30-746ec2022e18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158691359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4158691359
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3099333054
Short name T654
Test name
Test status
Simulation time 405324965 ps
CPU time 1.87 seconds
Started Mar 26 12:31:03 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 196704 kb
Host smart-c272cd62-62e9-4445-92cc-faaa0c0204fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099333054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3099333054
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2677968554
Short name T649
Test name
Test status
Simulation time 33341003 ps
CPU time 0.97 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 195584 kb
Host smart-135aa581-49ea-4804-970e-267f36bbb53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677968554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2677968554
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3177549231
Short name T678
Test name
Test status
Simulation time 55441242 ps
CPU time 0.91 seconds
Started Mar 26 12:31:10 PM PDT 24
Finished Mar 26 12:31:12 PM PDT 24
Peak memory 195604 kb
Host smart-b55dee21-5bb9-4ee9-9557-b6c214cd6df4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177549231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3177549231
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3499150597
Short name T513
Test name
Test status
Simulation time 24281836645 ps
CPU time 112.27 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:32:58 PM PDT 24
Peak memory 198040 kb
Host smart-e667424d-e212-45f2-92a4-e1c538314486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499150597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3499150597
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1115208868
Short name T711
Test name
Test status
Simulation time 176825589604 ps
CPU time 1409.82 seconds
Started Mar 26 12:31:10 PM PDT 24
Finished Mar 26 12:54:40 PM PDT 24
Peak memory 198096 kb
Host smart-39430706-48e1-469e-9a78-2601f7b36bc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1115208868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1115208868
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3311491637
Short name T193
Test name
Test status
Simulation time 10669967 ps
CPU time 0.55 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:31:08 PM PDT 24
Peak memory 193816 kb
Host smart-512662cb-96ed-4586-95ff-6bf8e3420401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311491637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3311491637
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1752045185
Short name T467
Test name
Test status
Simulation time 20359223 ps
CPU time 0.69 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 195072 kb
Host smart-d4d4563f-2d24-4559-a4fc-bece8571a9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752045185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1752045185
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2716115995
Short name T446
Test name
Test status
Simulation time 1075041511 ps
CPU time 16.04 seconds
Started Mar 26 12:31:02 PM PDT 24
Finished Mar 26 12:31:19 PM PDT 24
Peak memory 197864 kb
Host smart-83158456-ef0c-4e01-aa96-cc66aad43543
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716115995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2716115995
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2671078891
Short name T336
Test name
Test status
Simulation time 43862060 ps
CPU time 0.71 seconds
Started Mar 26 12:31:11 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 194784 kb
Host smart-f8f7c41e-2ec8-46a6-bc56-a49e1fad4bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671078891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2671078891
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1589193483
Short name T164
Test name
Test status
Simulation time 102422644 ps
CPU time 1.48 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:31:10 PM PDT 24
Peak memory 197956 kb
Host smart-a8222113-48a6-4311-8fdc-dc8c6e4e04c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589193483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1589193483
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1259160024
Short name T323
Test name
Test status
Simulation time 58464285 ps
CPU time 1.21 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:15 PM PDT 24
Peak memory 196824 kb
Host smart-864bf56e-5331-4675-99a7-fda64358203e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259160024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1259160024
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.826567227
Short name T641
Test name
Test status
Simulation time 1168208291 ps
CPU time 3.25 seconds
Started Mar 26 12:31:11 PM PDT 24
Finished Mar 26 12:31:16 PM PDT 24
Peak memory 196900 kb
Host smart-b7defef7-65af-4886-972a-833610e5cb3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826567227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
826567227
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3587617539
Short name T212
Test name
Test status
Simulation time 59493418 ps
CPU time 1.06 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:31:08 PM PDT 24
Peak memory 195880 kb
Host smart-fcb6808a-05fb-407e-b6d9-1d52df5da74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587617539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3587617539
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.290077532
Short name T192
Test name
Test status
Simulation time 64833093 ps
CPU time 1.19 seconds
Started Mar 26 12:31:10 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 196928 kb
Host smart-83a23eed-ab4b-45d8-aef7-8abafbce4a46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290077532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.290077532
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.73342880
Short name T463
Test name
Test status
Simulation time 108126707 ps
CPU time 4.6 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:11 PM PDT 24
Peak memory 197804 kb
Host smart-2b987d73-fc5f-4610-9f3d-763eab124394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73342880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand
om_long_reg_writes_reg_reads.73342880
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1455555604
Short name T485
Test name
Test status
Simulation time 47254317 ps
CPU time 1.19 seconds
Started Mar 26 12:31:11 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 196652 kb
Host smart-76d487ba-ff77-4eb2-9e13-648cd0cc35f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455555604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1455555604
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1222364708
Short name T166
Test name
Test status
Simulation time 80800611 ps
CPU time 0.7 seconds
Started Mar 26 12:31:11 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 195012 kb
Host smart-06f976b4-fd94-4efa-a544-7d8fbd3fc9fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222364708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1222364708
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1532298704
Short name T543
Test name
Test status
Simulation time 2361036001 ps
CPU time 29.42 seconds
Started Mar 26 12:31:08 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 198072 kb
Host smart-d5bb0c90-2ce5-4d0b-a92e-25f52fd35496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532298704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1532298704
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2742739927
Short name T371
Test name
Test status
Simulation time 64697879949 ps
CPU time 1452.21 seconds
Started Mar 26 12:31:11 PM PDT 24
Finished Mar 26 12:55:25 PM PDT 24
Peak memory 198176 kb
Host smart-1e941fdc-fd36-4f34-b83e-07ae671df4c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2742739927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2742739927
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1510627776
Short name T412
Test name
Test status
Simulation time 52417808 ps
CPU time 0.56 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:06 PM PDT 24
Peak memory 193980 kb
Host smart-80a58eb7-cd62-45ae-a785-364a4517b89b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510627776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1510627776
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.793695423
Short name T203
Test name
Test status
Simulation time 37499683 ps
CPU time 0.66 seconds
Started Mar 26 12:31:04 PM PDT 24
Finished Mar 26 12:31:05 PM PDT 24
Peak memory 193896 kb
Host smart-2f037230-bcfc-47f5-9b26-3fa8660c9ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793695423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.793695423
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1869247498
Short name T390
Test name
Test status
Simulation time 186082091 ps
CPU time 7.58 seconds
Started Mar 26 12:31:05 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 196108 kb
Host smart-9ac989e1-25c7-4541-bf9a-59a95e034e1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869247498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1869247498
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1285106412
Short name T517
Test name
Test status
Simulation time 59622795 ps
CPU time 0.87 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 195932 kb
Host smart-463dedfe-7dd1-4194-97e3-b08ff623d483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285106412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1285106412
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.201961507
Short name T320
Test name
Test status
Simulation time 141997581 ps
CPU time 0.64 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:14 PM PDT 24
Peak memory 194236 kb
Host smart-45731ad8-7b4c-45af-a46d-c2654ad56280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201961507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.201961507
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.791732665
Short name T366
Test name
Test status
Simulation time 370270770 ps
CPU time 3.23 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:17 PM PDT 24
Peak memory 197976 kb
Host smart-56934b75-a67c-4b97-a0fc-f6d9e3139807
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791732665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.791732665
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.143090914
Short name T209
Test name
Test status
Simulation time 337228115 ps
CPU time 2.93 seconds
Started Mar 26 12:31:09 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 197924 kb
Host smart-58e51e5e-9128-4195-a751-0ed90c8f61d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143090914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
143090914
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2220162860
Short name T430
Test name
Test status
Simulation time 37932660 ps
CPU time 0.91 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:14 PM PDT 24
Peak memory 196420 kb
Host smart-88786c90-b756-4996-a86e-5bbe1ad67c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220162860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2220162860
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4072841011
Short name T114
Test name
Test status
Simulation time 293712146 ps
CPU time 1.24 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:31:08 PM PDT 24
Peak memory 196872 kb
Host smart-fb4598e9-92f8-48ce-a93c-49f642344877
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072841011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4072841011
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1017359056
Short name T464
Test name
Test status
Simulation time 206332482 ps
CPU time 4.64 seconds
Started Mar 26 12:31:04 PM PDT 24
Finished Mar 26 12:31:09 PM PDT 24
Peak memory 197844 kb
Host smart-30cbc5e0-d70c-4930-a771-45df40450b04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017359056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1017359056
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.209710766
Short name T254
Test name
Test status
Simulation time 183839141 ps
CPU time 1.24 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:14 PM PDT 24
Peak memory 197824 kb
Host smart-9c29e4df-de5d-453f-b683-d4ab7d705d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209710766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.209710766
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3464943327
Short name T673
Test name
Test status
Simulation time 220078174 ps
CPU time 0.94 seconds
Started Mar 26 12:31:11 PM PDT 24
Finished Mar 26 12:31:14 PM PDT 24
Peak memory 196200 kb
Host smart-6cdf53d2-5746-483c-817d-bee9d64a70a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464943327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3464943327
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.553246499
Short name T374
Test name
Test status
Simulation time 3756571695 ps
CPU time 94.97 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:32:43 PM PDT 24
Peak memory 198104 kb
Host smart-48a6b8f6-7289-444e-8c11-e388ab97145d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553246499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.553246499
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2743921385
Short name T495
Test name
Test status
Simulation time 58889387 ps
CPU time 0.54 seconds
Started Mar 26 12:31:15 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 193748 kb
Host smart-f6535554-a84a-4af2-a051-0b89962720e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743921385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2743921385
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2063132815
Short name T539
Test name
Test status
Simulation time 57979118 ps
CPU time 0.91 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 196624 kb
Host smart-872806a8-461c-4310-9a38-5af3270627aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063132815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2063132815
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.873408347
Short name T341
Test name
Test status
Simulation time 514139913 ps
CPU time 26.81 seconds
Started Mar 26 12:31:09 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 196768 kb
Host smart-668302a8-d235-4190-b6fc-ef382da7c9ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873408347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.873408347
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3128247936
Short name T21
Test name
Test status
Simulation time 343999972 ps
CPU time 0.86 seconds
Started Mar 26 12:31:10 PM PDT 24
Finished Mar 26 12:31:11 PM PDT 24
Peak memory 196008 kb
Host smart-553d420c-381e-4390-a1a9-d4a26f46a1dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128247936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3128247936
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.806677739
Short name T577
Test name
Test status
Simulation time 59225760 ps
CPU time 1.1 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 196752 kb
Host smart-f791e732-3a10-489c-b861-0223a6232256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806677739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.806677739
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1855792905
Short name T657
Test name
Test status
Simulation time 247936540 ps
CPU time 2.47 seconds
Started Mar 26 12:31:05 PM PDT 24
Finished Mar 26 12:31:08 PM PDT 24
Peak memory 197968 kb
Host smart-fcb8450e-2e54-4c36-b0c5-16277216ab2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855792905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1855792905
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.453381684
Short name T680
Test name
Test status
Simulation time 229206780 ps
CPU time 1.18 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:31:08 PM PDT 24
Peak memory 196452 kb
Host smart-bdfecba6-e897-4295-9ecb-c44430c77b25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453381684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
453381684
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2011361900
Short name T452
Test name
Test status
Simulation time 55995479 ps
CPU time 1.09 seconds
Started Mar 26 12:31:07 PM PDT 24
Finished Mar 26 12:31:09 PM PDT 24
Peak memory 196660 kb
Host smart-94248e8d-a498-48c9-bbfc-e7f2e8c711bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011361900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2011361900
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1061105106
Short name T284
Test name
Test status
Simulation time 59993448 ps
CPU time 1.2 seconds
Started Mar 26 12:31:08 PM PDT 24
Finished Mar 26 12:31:09 PM PDT 24
Peak memory 196860 kb
Host smart-ad2c2166-ee50-47cb-bbca-b7e2a940a5c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061105106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1061105106
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3653495394
Short name T592
Test name
Test status
Simulation time 94404886 ps
CPU time 4.28 seconds
Started Mar 26 12:31:08 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 197888 kb
Host smart-5c3d97d0-234a-494f-916d-a020a639717f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653495394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3653495394
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2098017767
Short name T154
Test name
Test status
Simulation time 200898065 ps
CPU time 1.24 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 196556 kb
Host smart-dcc8c8ec-b001-409c-9141-8958133f10a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098017767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2098017767
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2999783494
Short name T115
Test name
Test status
Simulation time 410669109 ps
CPU time 1.42 seconds
Started Mar 26 12:31:09 PM PDT 24
Finished Mar 26 12:31:11 PM PDT 24
Peak memory 197828 kb
Host smart-be48136d-7a9a-4d4d-bd62-0d5f11550ac3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999783494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2999783494
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3596301915
Short name T24
Test name
Test status
Simulation time 12848957533 ps
CPU time 167.31 seconds
Started Mar 26 12:31:06 PM PDT 24
Finished Mar 26 12:33:54 PM PDT 24
Peak memory 197936 kb
Host smart-d5c31c56-55e7-4ba9-98d6-fafcc8b899b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596301915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3596301915
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2525751406
Short name T33
Test name
Test status
Simulation time 82130840958 ps
CPU time 1644.79 seconds
Started Mar 26 12:31:09 PM PDT 24
Finished Mar 26 12:58:35 PM PDT 24
Peak memory 198092 kb
Host smart-ffaecc22-18f5-4ecf-a5bb-5165448b1ea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2525751406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2525751406
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1246596423
Short name T651
Test name
Test status
Simulation time 47216645 ps
CPU time 0.57 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:14 PM PDT 24
Peak memory 194008 kb
Host smart-afdc4c23-a0ab-43a2-ba75-3eea83b6ddd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246596423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1246596423
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.403167139
Short name T201
Test name
Test status
Simulation time 97731434 ps
CPU time 0.86 seconds
Started Mar 26 12:31:16 PM PDT 24
Finished Mar 26 12:31:19 PM PDT 24
Peak memory 196292 kb
Host smart-d72e3627-b78d-48d8-98d6-0c529866438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403167139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.403167139
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2537136206
Short name T633
Test name
Test status
Simulation time 577090085 ps
CPU time 19.61 seconds
Started Mar 26 12:31:15 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 196948 kb
Host smart-b7133b24-e497-4680-8a9a-bde037875e70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537136206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2537136206
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1150438900
Short name T491
Test name
Test status
Simulation time 431293607 ps
CPU time 0.69 seconds
Started Mar 26 12:31:13 PM PDT 24
Finished Mar 26 12:31:15 PM PDT 24
Peak memory 194752 kb
Host smart-ad0ce0b9-ebfa-4516-8474-8ee6f7cb2862
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150438900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1150438900
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1399305057
Short name T420
Test name
Test status
Simulation time 155411470 ps
CPU time 1.28 seconds
Started Mar 26 12:31:17 PM PDT 24
Finished Mar 26 12:31:21 PM PDT 24
Peak memory 196736 kb
Host smart-4e7b3ada-6005-4183-b2e9-9467f6460d01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399305057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1399305057
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1117317167
Short name T559
Test name
Test status
Simulation time 35966549 ps
CPU time 1.51 seconds
Started Mar 26 12:31:16 PM PDT 24
Finished Mar 26 12:31:19 PM PDT 24
Peak memory 196308 kb
Host smart-7caa1719-ac75-4c57-a63d-c58e290f73bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117317167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1117317167
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.440635052
Short name T124
Test name
Test status
Simulation time 169053705 ps
CPU time 2.5 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:16 PM PDT 24
Peak memory 197948 kb
Host smart-4f290e26-1bb8-4740-8dbc-431cf312d495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440635052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
440635052
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3771551689
Short name T406
Test name
Test status
Simulation time 47393628 ps
CPU time 0.9 seconds
Started Mar 26 12:31:13 PM PDT 24
Finished Mar 26 12:31:14 PM PDT 24
Peak memory 195592 kb
Host smart-0b3307d9-1b5d-4a8e-b051-b0c971e723b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771551689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3771551689
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3295846733
Short name T516
Test name
Test status
Simulation time 115025275 ps
CPU time 1.05 seconds
Started Mar 26 12:31:12 PM PDT 24
Finished Mar 26 12:31:15 PM PDT 24
Peak memory 195640 kb
Host smart-ceeb0842-cca6-4631-842c-bc73882f51e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295846733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3295846733
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3176281839
Short name T8
Test name
Test status
Simulation time 293809488 ps
CPU time 3.55 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:21 PM PDT 24
Peak memory 197812 kb
Host smart-432bea93-9750-4051-9fe7-6cf2ce516693
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176281839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3176281839
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.4041366688
Short name T144
Test name
Test status
Simulation time 314049113 ps
CPU time 1.19 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 196496 kb
Host smart-0ec09ea2-ccbf-40fd-92a0-c0f1b7c24b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041366688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.4041366688
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1776476485
Short name T184
Test name
Test status
Simulation time 77077167 ps
CPU time 1.25 seconds
Started Mar 26 12:31:15 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 196520 kb
Host smart-8f808f3c-723c-4fbe-aa4c-a2adfb579bbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776476485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1776476485
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.94265617
Short name T584
Test name
Test status
Simulation time 7057886916 ps
CPU time 86.09 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:32:43 PM PDT 24
Peak memory 198036 kb
Host smart-d9364ac2-ce51-4f86-a399-6f0b62856db8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94265617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gp
io_stress_all.94265617
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2246906611
Short name T195
Test name
Test status
Simulation time 36090063 ps
CPU time 0.53 seconds
Started Mar 26 12:31:11 PM PDT 24
Finished Mar 26 12:31:13 PM PDT 24
Peak memory 192636 kb
Host smart-a84c9780-a6c6-446c-a81b-318e9ff276da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246906611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2246906611
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3134016411
Short name T498
Test name
Test status
Simulation time 51330742 ps
CPU time 0.58 seconds
Started Mar 26 12:31:15 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 193864 kb
Host smart-8b6b5657-658e-48b3-a387-85b7cfe5965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134016411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3134016411
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.121984661
Short name T303
Test name
Test status
Simulation time 1410746181 ps
CPU time 7.54 seconds
Started Mar 26 12:31:16 PM PDT 24
Finished Mar 26 12:31:25 PM PDT 24
Peak memory 196064 kb
Host smart-02e60a3f-3275-4bc0-880d-075a5e085be7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121984661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.121984661
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1195582445
Short name T50
Test name
Test status
Simulation time 49458839 ps
CPU time 0.78 seconds
Started Mar 26 12:31:17 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 195940 kb
Host smart-621571e0-6b55-4b1a-a2f0-4ad0f62fb6c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195582445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1195582445
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2498252195
Short name T686
Test name
Test status
Simulation time 300558570 ps
CPU time 0.93 seconds
Started Mar 26 12:31:16 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 195748 kb
Host smart-465f1fbd-9084-46b4-885a-699f34335d42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498252195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2498252195
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2358732405
Short name T181
Test name
Test status
Simulation time 55179061 ps
CPU time 2.19 seconds
Started Mar 26 12:31:13 PM PDT 24
Finished Mar 26 12:31:16 PM PDT 24
Peak memory 196180 kb
Host smart-7d1c94cf-9701-432b-a9f3-7ab62983ed30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358732405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2358732405
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3592828145
Short name T624
Test name
Test status
Simulation time 540151757 ps
CPU time 2.53 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:17 PM PDT 24
Peak memory 197096 kb
Host smart-9c50a7ea-e17f-4e62-be76-67e0d4ccad18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592828145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3592828145
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3523574748
Short name T586
Test name
Test status
Simulation time 322233731 ps
CPU time 0.74 seconds
Started Mar 26 12:31:16 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 196020 kb
Host smart-e2971904-6c1b-41af-91b6-e2a4531c85a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523574748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3523574748
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1018805746
Short name T501
Test name
Test status
Simulation time 79956053 ps
CPU time 1.3 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 195676 kb
Host smart-144cf27f-1933-4253-95d8-41b97f7e67c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018805746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1018805746
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1353080501
Short name T143
Test name
Test status
Simulation time 92255776 ps
CPU time 1.98 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:17 PM PDT 24
Peak memory 197760 kb
Host smart-57b31c03-a3d5-43d4-b0c4-a42b0a327093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353080501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1353080501
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1475404311
Short name T504
Test name
Test status
Simulation time 20243216 ps
CPU time 0.67 seconds
Started Mar 26 12:31:15 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 194684 kb
Host smart-6da6c2eb-9d67-4f4d-9722-48cf08f59d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475404311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1475404311
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2292694919
Short name T349
Test name
Test status
Simulation time 44545439 ps
CPU time 1.23 seconds
Started Mar 26 12:31:15 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 197812 kb
Host smart-0c107d35-f108-4946-a081-4800fca26f7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292694919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2292694919
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3944882829
Short name T416
Test name
Test status
Simulation time 54510619480 ps
CPU time 180.28 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:34:16 PM PDT 24
Peak memory 198092 kb
Host smart-cb735123-b5b1-4c8f-9c1e-5db328d4f0b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944882829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3944882829
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.192173184
Short name T34
Test name
Test status
Simulation time 33944707557 ps
CPU time 263.42 seconds
Started Mar 26 12:31:15 PM PDT 24
Finished Mar 26 12:35:40 PM PDT 24
Peak memory 198068 kb
Host smart-ad8879bb-ac8d-4012-9b7e-d66a7fa643e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=192173184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.192173184
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3328808707
Short name T231
Test name
Test status
Simulation time 12555772 ps
CPU time 0.54 seconds
Started Mar 26 12:31:19 PM PDT 24
Finished Mar 26 12:31:21 PM PDT 24
Peak memory 193636 kb
Host smart-8da7fcb7-0c2b-49df-8a0e-89de78f97be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328808707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3328808707
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4200861020
Short name T684
Test name
Test status
Simulation time 50980275 ps
CPU time 0.84 seconds
Started Mar 26 12:31:13 PM PDT 24
Finished Mar 26 12:31:15 PM PDT 24
Peak memory 196224 kb
Host smart-16c88d9e-9411-4ebc-908e-6f7e2386e1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200861020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4200861020
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.647725769
Short name T122
Test name
Test status
Simulation time 749401645 ps
CPU time 19.8 seconds
Started Mar 26 12:31:11 PM PDT 24
Finished Mar 26 12:31:31 PM PDT 24
Peak memory 196820 kb
Host smart-309276ac-3fe5-48c0-b545-5478043c7f25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647725769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.647725769
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.908444602
Short name T669
Test name
Test status
Simulation time 208689470 ps
CPU time 0.87 seconds
Started Mar 26 12:31:17 PM PDT 24
Finished Mar 26 12:31:19 PM PDT 24
Peak memory 196912 kb
Host smart-e95fe828-d1cc-4179-a920-113191a731cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908444602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.908444602
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2535112271
Short name T316
Test name
Test status
Simulation time 48903242 ps
CPU time 0.91 seconds
Started Mar 26 12:31:17 PM PDT 24
Finished Mar 26 12:31:20 PM PDT 24
Peak memory 197200 kb
Host smart-55fc6c68-7085-434e-b646-0c395ed2021e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535112271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2535112271
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3511845580
Short name T409
Test name
Test status
Simulation time 64486447 ps
CPU time 0.84 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:16 PM PDT 24
Peak memory 195928 kb
Host smart-d9b45b11-4a40-4048-af80-d13067fda347
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511845580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3511845580
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3222288951
Short name T137
Test name
Test status
Simulation time 153774923 ps
CPU time 1.61 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:16 PM PDT 24
Peak memory 195908 kb
Host smart-b3cb6275-6437-4925-b0e2-0123d06ddfbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222288951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3222288951
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3921345735
Short name T211
Test name
Test status
Simulation time 91250338 ps
CPU time 1.08 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:15 PM PDT 24
Peak memory 195880 kb
Host smart-a163f52f-c962-42a9-9893-91a070f53ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921345735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3921345735
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3517075495
Short name T691
Test name
Test status
Simulation time 44523632 ps
CPU time 1.08 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 195928 kb
Host smart-7a63b922-732e-4326-bffa-e7f5f992d6ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517075495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3517075495
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3416315353
Short name T561
Test name
Test status
Simulation time 238023315 ps
CPU time 2.97 seconds
Started Mar 26 12:31:14 PM PDT 24
Finished Mar 26 12:31:20 PM PDT 24
Peak memory 197836 kb
Host smart-f32ae52c-633b-4957-9f91-8b530ccb88ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416315353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3416315353
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1992411141
Short name T280
Test name
Test status
Simulation time 37046063 ps
CPU time 1.14 seconds
Started Mar 26 12:31:17 PM PDT 24
Finished Mar 26 12:31:19 PM PDT 24
Peak memory 196316 kb
Host smart-1414e693-0757-4c0b-b225-e5bef0ac4799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992411141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1992411141
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.155959057
Short name T72
Test name
Test status
Simulation time 154835858 ps
CPU time 0.96 seconds
Started Mar 26 12:31:15 PM PDT 24
Finished Mar 26 12:31:18 PM PDT 24
Peak memory 196084 kb
Host smart-5ee99555-9865-4b08-ae53-9594f19daeed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155959057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.155959057
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3935397971
Short name T560
Test name
Test status
Simulation time 123495457399 ps
CPU time 133.75 seconds
Started Mar 26 12:31:16 PM PDT 24
Finished Mar 26 12:33:31 PM PDT 24
Peak memory 198020 kb
Host smart-9f36c45c-c0f6-41b3-93e0-2eb903c47606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935397971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3935397971
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3624201145
Short name T28
Test name
Test status
Simulation time 15983248 ps
CPU time 0.57 seconds
Started Mar 26 12:31:25 PM PDT 24
Finished Mar 26 12:31:25 PM PDT 24
Peak memory 194440 kb
Host smart-da114bc0-e35b-4249-adc1-de1c8ef77c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624201145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3624201145
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1852728872
Short name T448
Test name
Test status
Simulation time 112146131 ps
CPU time 0.76 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 195852 kb
Host smart-b4f6b7a4-f5d9-4b79-9e88-c462b38c32cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852728872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1852728872
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1383033628
Short name T605
Test name
Test status
Simulation time 2720655547 ps
CPU time 18.03 seconds
Started Mar 26 12:31:22 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 198012 kb
Host smart-d354f8b1-bd22-4e98-8596-4f77e365667b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383033628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1383033628
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.137204952
Short name T693
Test name
Test status
Simulation time 30565391 ps
CPU time 0.66 seconds
Started Mar 26 12:31:25 PM PDT 24
Finished Mar 26 12:31:26 PM PDT 24
Peak memory 195188 kb
Host smart-1d3e0507-5b2c-453a-b77b-c6f7ad187277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137204952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.137204952
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1373900928
Short name T330
Test name
Test status
Simulation time 40196885 ps
CPU time 0.83 seconds
Started Mar 26 12:31:27 PM PDT 24
Finished Mar 26 12:31:28 PM PDT 24
Peak memory 197432 kb
Host smart-5755f606-4baf-4052-898d-e38f8f46a266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373900928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1373900928
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2396208549
Short name T534
Test name
Test status
Simulation time 141070095 ps
CPU time 2.77 seconds
Started Mar 26 12:31:27 PM PDT 24
Finished Mar 26 12:31:30 PM PDT 24
Peak memory 196336 kb
Host smart-b33face1-26b4-413f-9e62-d1206069a462
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396208549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2396208549
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2558379013
Short name T116
Test name
Test status
Simulation time 78263148 ps
CPU time 1.69 seconds
Started Mar 26 12:31:23 PM PDT 24
Finished Mar 26 12:31:25 PM PDT 24
Peak memory 195836 kb
Host smart-c0c32835-f0ce-403b-b2dc-8cc7d24f8c7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558379013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2558379013
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1324776119
Short name T378
Test name
Test status
Simulation time 42649718 ps
CPU time 0.68 seconds
Started Mar 26 12:31:25 PM PDT 24
Finished Mar 26 12:31:25 PM PDT 24
Peak memory 195400 kb
Host smart-da9c1f5d-eee7-42ed-addf-904da7808af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324776119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1324776119
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1595271392
Short name T313
Test name
Test status
Simulation time 77045605 ps
CPU time 0.97 seconds
Started Mar 26 12:31:34 PM PDT 24
Finished Mar 26 12:31:35 PM PDT 24
Peak memory 196396 kb
Host smart-8f0f0781-c4ac-49c1-9105-155430a70a55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595271392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1595271392
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3445637362
Short name T3
Test name
Test status
Simulation time 622847430 ps
CPU time 4.09 seconds
Started Mar 26 12:31:25 PM PDT 24
Finished Mar 26 12:31:30 PM PDT 24
Peak memory 198120 kb
Host smart-b836e28b-8780-420e-9d52-926a58c34ffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445637362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3445637362
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1708356397
Short name T650
Test name
Test status
Simulation time 375644136 ps
CPU time 0.98 seconds
Started Mar 26 12:31:23 PM PDT 24
Finished Mar 26 12:31:25 PM PDT 24
Peak memory 196360 kb
Host smart-3e07e101-7441-44d2-b1f8-824e3f00bfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708356397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1708356397
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.302726751
Short name T545
Test name
Test status
Simulation time 72149517 ps
CPU time 1.13 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 195708 kb
Host smart-81a8ead5-05d6-4edf-9ef1-fd365b15fab1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302726751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.302726751
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3117909581
Short name T69
Test name
Test status
Simulation time 16586373036 ps
CPU time 104.3 seconds
Started Mar 26 12:31:34 PM PDT 24
Finished Mar 26 12:33:18 PM PDT 24
Peak memory 198032 kb
Host smart-3c888a9e-c617-432f-bfaa-454bfbd3aedd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117909581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3117909581
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3047375154
Short name T61
Test name
Test status
Simulation time 177261489900 ps
CPU time 2085.37 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 01:06:22 PM PDT 24
Peak memory 198088 kb
Host smart-88b50c02-fba2-4b82-8fa2-1203529d125b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3047375154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3047375154
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.514368575
Short name T695
Test name
Test status
Simulation time 55271248 ps
CPU time 0.55 seconds
Started Mar 26 12:31:27 PM PDT 24
Finished Mar 26 12:31:28 PM PDT 24
Peak memory 193788 kb
Host smart-6e534722-ac9f-4abf-942c-dd758be2bf99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514368575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.514368575
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.55271521
Short name T718
Test name
Test status
Simulation time 324804297 ps
CPU time 0.76 seconds
Started Mar 26 12:31:25 PM PDT 24
Finished Mar 26 12:31:25 PM PDT 24
Peak memory 195196 kb
Host smart-5970f666-8878-4e2e-b2bb-1a3e8f3c0459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55271521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.55271521
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1317278832
Short name T667
Test name
Test status
Simulation time 1326814784 ps
CPU time 14.34 seconds
Started Mar 26 12:31:24 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 196840 kb
Host smart-b257f411-2a26-468a-a0f0-c4c943d76778
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317278832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1317278832
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2891303365
Short name T436
Test name
Test status
Simulation time 42380138 ps
CPU time 0.72 seconds
Started Mar 26 12:31:25 PM PDT 24
Finished Mar 26 12:31:26 PM PDT 24
Peak memory 194680 kb
Host smart-6d16a9df-0864-4a9e-80c5-25f063da26c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891303365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2891303365
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4257948987
Short name T468
Test name
Test status
Simulation time 497945688 ps
CPU time 1.2 seconds
Started Mar 26 12:31:33 PM PDT 24
Finished Mar 26 12:31:35 PM PDT 24
Peak memory 196760 kb
Host smart-8a0f3903-1137-4774-ac63-ae1e1aeac340
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257948987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4257948987
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2927188275
Short name T716
Test name
Test status
Simulation time 303372661 ps
CPU time 2.89 seconds
Started Mar 26 12:31:33 PM PDT 24
Finished Mar 26 12:31:36 PM PDT 24
Peak memory 197936 kb
Host smart-715f712e-22b0-4a9e-b770-d56b8b6fd7c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927188275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2927188275
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.614719125
Short name T149
Test name
Test status
Simulation time 1995833956 ps
CPU time 2.21 seconds
Started Mar 26 12:31:25 PM PDT 24
Finished Mar 26 12:31:27 PM PDT 24
Peak memory 197880 kb
Host smart-3196fa4e-ad53-434d-a825-6e49ddcaf33e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614719125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
614719125
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3123176720
Short name T612
Test name
Test status
Simulation time 153079062 ps
CPU time 0.95 seconds
Started Mar 26 12:31:28 PM PDT 24
Finished Mar 26 12:31:29 PM PDT 24
Peak memory 195760 kb
Host smart-d56420b6-875d-4ca9-a76b-632e0d42bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123176720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3123176720
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2291046254
Short name T53
Test name
Test status
Simulation time 98704927 ps
CPU time 0.8 seconds
Started Mar 26 12:31:27 PM PDT 24
Finished Mar 26 12:31:28 PM PDT 24
Peak memory 196140 kb
Host smart-136d9bf7-6ed7-4e6d-8927-20c2ebf30c22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291046254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2291046254
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3714377283
Short name T377
Test name
Test status
Simulation time 323292652 ps
CPU time 5.06 seconds
Started Mar 26 12:31:33 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 197832 kb
Host smart-45ae52b1-4588-4683-82a4-06c89a7b0617
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714377283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3714377283
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2872942065
Short name T67
Test name
Test status
Simulation time 43372387 ps
CPU time 1.13 seconds
Started Mar 26 12:31:26 PM PDT 24
Finished Mar 26 12:31:28 PM PDT 24
Peak memory 196152 kb
Host smart-8ab338c5-28ac-4990-878e-e5c2a9709a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872942065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2872942065
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1734586198
Short name T204
Test name
Test status
Simulation time 169556341 ps
CPU time 1.17 seconds
Started Mar 26 12:31:34 PM PDT 24
Finished Mar 26 12:31:36 PM PDT 24
Peak memory 195704 kb
Host smart-d64cd62f-77b0-4f1f-8cb3-5db11be4dc45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734586198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1734586198
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2064431083
Short name T514
Test name
Test status
Simulation time 4686465271 ps
CPU time 60.93 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:32:37 PM PDT 24
Peak memory 198032 kb
Host smart-422e03c8-ed9b-439a-a0fb-21f751a32e03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064431083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2064431083
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3989189772
Short name T554
Test name
Test status
Simulation time 16189438762 ps
CPU time 258.03 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:35:54 PM PDT 24
Peak memory 198144 kb
Host smart-340eca47-c7b0-41f2-81cd-61a2e26c15af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3989189772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3989189772
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2240539848
Short name T367
Test name
Test status
Simulation time 30899575 ps
CPU time 0.53 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:48 PM PDT 24
Peak memory 193796 kb
Host smart-23e0455d-026d-42df-8147-b8b37868af08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240539848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2240539848
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.10597240
Short name T271
Test name
Test status
Simulation time 247250999 ps
CPU time 0.79 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:48 PM PDT 24
Peak memory 195256 kb
Host smart-7e314ca2-eb7c-48d1-82ba-dc4884f280ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10597240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.10597240
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.375583586
Short name T660
Test name
Test status
Simulation time 409120140 ps
CPU time 20.81 seconds
Started Mar 26 12:29:45 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 196816 kb
Host smart-ccf70dee-7ba5-45b5-8aa1-9c966c6b527a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375583586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.375583586
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3959415037
Short name T365
Test name
Test status
Simulation time 66276817 ps
CPU time 0.92 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:48 PM PDT 24
Peak memory 196480 kb
Host smart-06b80a3b-c357-40e6-b21b-10367cc33833
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959415037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3959415037
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.783932156
Short name T638
Test name
Test status
Simulation time 27428625 ps
CPU time 0.86 seconds
Started Mar 26 12:29:48 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 197480 kb
Host smart-44f950a8-36ec-4593-a5c1-8d9f45a83ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783932156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.783932156
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2842181700
Short name T225
Test name
Test status
Simulation time 300295326 ps
CPU time 2.7 seconds
Started Mar 26 12:29:46 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 197888 kb
Host smart-28a77804-cace-45ed-9b57-a54a6a839c8c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842181700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2842181700
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2018901565
Short name T402
Test name
Test status
Simulation time 223850497 ps
CPU time 3.05 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:50 PM PDT 24
Peak memory 196984 kb
Host smart-6380c6a6-26c0-4aa8-84ec-175d0f6e8c61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018901565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2018901565
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.945325005
Short name T426
Test name
Test status
Simulation time 174823843 ps
CPU time 1.04 seconds
Started Mar 26 12:29:43 PM PDT 24
Finished Mar 26 12:29:45 PM PDT 24
Peak memory 195612 kb
Host smart-6ffa5c7c-b3a1-4ca1-bad7-b3fe31a5eedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945325005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.945325005
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2374634808
Short name T335
Test name
Test status
Simulation time 29171746 ps
CPU time 1.04 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 195836 kb
Host smart-0577a196-6b2c-4f9e-bbd1-76c8bd70dee4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374634808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2374634808
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.882587983
Short name T655
Test name
Test status
Simulation time 324277717 ps
CPU time 4.37 seconds
Started Mar 26 12:29:43 PM PDT 24
Finished Mar 26 12:29:47 PM PDT 24
Peak memory 197872 kb
Host smart-842216c4-347a-450e-aa99-51d1b1cf6a77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882587983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.882587983
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.434885428
Short name T41
Test name
Test status
Simulation time 83223866 ps
CPU time 0.87 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:48 PM PDT 24
Peak memory 213700 kb
Host smart-6b54036d-5cb1-4fe1-b14a-4420dbd79f1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434885428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.434885428
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2286058943
Short name T218
Test name
Test status
Simulation time 58316704 ps
CPU time 0.93 seconds
Started Mar 26 12:29:44 PM PDT 24
Finished Mar 26 12:29:45 PM PDT 24
Peak memory 196180 kb
Host smart-f0e72449-58df-4021-9c81-51796acac387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286058943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2286058943
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1474670242
Short name T278
Test name
Test status
Simulation time 290444276 ps
CPU time 1.3 seconds
Started Mar 26 12:29:42 PM PDT 24
Finished Mar 26 12:29:44 PM PDT 24
Peak memory 196660 kb
Host smart-be6f4879-f422-4af7-b6d1-3a2401477f01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474670242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1474670242
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2208341421
Short name T439
Test name
Test status
Simulation time 6784702045 ps
CPU time 173.48 seconds
Started Mar 26 12:29:55 PM PDT 24
Finished Mar 26 12:32:48 PM PDT 24
Peak memory 198052 kb
Host smart-42f3bc9d-a2a9-417a-adb2-c0f71388d18a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208341421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2208341421
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1138644222
Short name T696
Test name
Test status
Simulation time 239653427214 ps
CPU time 1827.19 seconds
Started Mar 26 12:29:44 PM PDT 24
Finished Mar 26 01:00:11 PM PDT 24
Peak memory 198112 kb
Host smart-8cb8ee04-d363-4eb5-9cd2-f2ff2e319786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1138644222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1138644222
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3592192833
Short name T196
Test name
Test status
Simulation time 122489986 ps
CPU time 0.55 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 193672 kb
Host smart-d17840db-6eb1-4bed-8118-7692d784cfdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592192833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3592192833
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3010485490
Short name T256
Test name
Test status
Simulation time 106250273 ps
CPU time 0.9 seconds
Started Mar 26 12:31:27 PM PDT 24
Finished Mar 26 12:31:28 PM PDT 24
Peak memory 196152 kb
Host smart-951aaf5d-c357-4ea9-8d0a-165b3fca6032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010485490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3010485490
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.162808836
Short name T552
Test name
Test status
Simulation time 162964369 ps
CPU time 8.2 seconds
Started Mar 26 12:31:35 PM PDT 24
Finished Mar 26 12:31:43 PM PDT 24
Peak memory 197808 kb
Host smart-1251a8c4-7998-4bf4-985f-3fd56939da6a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162808836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.162808836
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.793922281
Short name T537
Test name
Test status
Simulation time 107602931 ps
CPU time 1.15 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:31:42 PM PDT 24
Peak memory 196216 kb
Host smart-ad0056c6-9e87-4a45-9913-cc7f8c6c9e53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793922281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.793922281
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.29445116
Short name T197
Test name
Test status
Simulation time 44255993 ps
CPU time 0.91 seconds
Started Mar 26 12:31:26 PM PDT 24
Finished Mar 26 12:31:27 PM PDT 24
Peak memory 195404 kb
Host smart-dabfd5e7-a66a-4e43-a3f9-bd884989e481
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29445116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.29445116
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2457114814
Short name T656
Test name
Test status
Simulation time 146100494 ps
CPU time 1.57 seconds
Started Mar 26 12:31:28 PM PDT 24
Finished Mar 26 12:31:30 PM PDT 24
Peak memory 197816 kb
Host smart-40e2b565-6b46-4d99-a7bd-73cd3bd051ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457114814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2457114814
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1001117396
Short name T703
Test name
Test status
Simulation time 190602876 ps
CPU time 1.33 seconds
Started Mar 26 12:31:26 PM PDT 24
Finished Mar 26 12:31:28 PM PDT 24
Peak memory 197244 kb
Host smart-fb791075-286d-49d1-8d49-e59ec678cc41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001117396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1001117396
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1299314192
Short name T600
Test name
Test status
Simulation time 141409988 ps
CPU time 0.89 seconds
Started Mar 26 12:31:25 PM PDT 24
Finished Mar 26 12:31:26 PM PDT 24
Peak memory 195816 kb
Host smart-18336204-c448-405a-89f8-dee24f16bebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299314192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1299314192
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1348634873
Short name T712
Test name
Test status
Simulation time 63296026 ps
CPU time 1.2 seconds
Started Mar 26 12:31:27 PM PDT 24
Finished Mar 26 12:31:29 PM PDT 24
Peak memory 197916 kb
Host smart-935001a5-2a23-46ff-8f1b-28fcd6e870a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348634873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1348634873
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.243842602
Short name T475
Test name
Test status
Simulation time 195649058 ps
CPU time 2.52 seconds
Started Mar 26 12:31:23 PM PDT 24
Finished Mar 26 12:31:26 PM PDT 24
Peak memory 197844 kb
Host smart-f56fa959-e379-45fd-8f01-b9bfa546c393
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243842602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.243842602
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3089856499
Short name T488
Test name
Test status
Simulation time 64932013 ps
CPU time 1.13 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 196272 kb
Host smart-0ef8e828-f90a-4b81-b0e4-afcc16a6b4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089856499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3089856499
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1885359689
Short name T332
Test name
Test status
Simulation time 66068337 ps
CPU time 1.15 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 196456 kb
Host smart-a1d7d643-0c75-434f-8e73-b57b49ad6a7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885359689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1885359689
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.4201811991
Short name T572
Test name
Test status
Simulation time 18450520658 ps
CPU time 96.05 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:33:14 PM PDT 24
Peak memory 198048 kb
Host smart-a5e4a55c-8360-4d07-82aa-9750f3751e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201811991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.4201811991
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1911412411
Short name T619
Test name
Test status
Simulation time 343816861394 ps
CPU time 1174.19 seconds
Started Mar 26 12:31:42 PM PDT 24
Finished Mar 26 12:51:16 PM PDT 24
Peak memory 198104 kb
Host smart-79664dde-0a01-454b-9301-5854e0473f67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1911412411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1911412411
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.4262220922
Short name T31
Test name
Test status
Simulation time 12010283 ps
CPU time 0.56 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:40 PM PDT 24
Peak memory 193748 kb
Host smart-3296e91e-1cea-469e-bb5e-bfdc59c69184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262220922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.4262220922
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1046077746
Short name T400
Test name
Test status
Simulation time 45694417 ps
CPU time 0.65 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 193972 kb
Host smart-cd1f1ba5-2afe-4427-a70d-af17196afc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046077746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1046077746
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1724931069
Short name T487
Test name
Test status
Simulation time 2530014588 ps
CPU time 20.51 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:32:01 PM PDT 24
Peak memory 196528 kb
Host smart-91e1b467-c16b-4cc3-98e5-3332d3be85da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724931069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1724931069
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1286443250
Short name T375
Test name
Test status
Simulation time 57122451 ps
CPU time 0.85 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 195932 kb
Host smart-e306937d-755e-45ca-b796-2fc609ed9431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286443250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1286443250
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1398017855
Short name T352
Test name
Test status
Simulation time 133811356 ps
CPU time 1.25 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 195752 kb
Host smart-c385fe71-f6ef-46de-ad3f-3bfe9d637da0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398017855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1398017855
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1577505330
Short name T541
Test name
Test status
Simulation time 180508380 ps
CPU time 3.5 seconds
Started Mar 26 12:31:44 PM PDT 24
Finished Mar 26 12:31:47 PM PDT 24
Peak memory 197880 kb
Host smart-351ba32c-7f31-4340-8f4e-70964ce99607
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577505330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1577505330
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1874979838
Short name T344
Test name
Test status
Simulation time 506564710 ps
CPU time 2.23 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:31:44 PM PDT 24
Peak memory 195624 kb
Host smart-155635c5-ae81-4d99-9e0d-3cfe57c00f18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874979838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1874979838
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.544928982
Short name T626
Test name
Test status
Simulation time 168277317 ps
CPU time 1.01 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:31:42 PM PDT 24
Peak memory 195964 kb
Host smart-6a1f7c37-8573-491e-8893-d04078d71ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544928982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.544928982
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.849313898
Short name T355
Test name
Test status
Simulation time 30748290 ps
CPU time 0.83 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 195932 kb
Host smart-9f25beb7-50ba-46d4-ac45-9545245ada22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849313898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.849313898
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3402503400
Short name T199
Test name
Test status
Simulation time 356833648 ps
CPU time 3.52 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 197804 kb
Host smart-1f1e6e35-bcd8-4e03-91b1-b3bccd0fd427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402503400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3402503400
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.236152733
Short name T483
Test name
Test status
Simulation time 140716117 ps
CPU time 0.86 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 195308 kb
Host smart-11ca8bce-e36b-40e4-a292-87a2bf087155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236152733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.236152733
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2948148497
Short name T553
Test name
Test status
Simulation time 114039965 ps
CPU time 1.27 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 196600 kb
Host smart-b4e00893-08d3-44e0-9c94-03e96ca61e00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948148497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2948148497
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1850420062
Short name T113
Test name
Test status
Simulation time 20365557265 ps
CPU time 147.69 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:34:05 PM PDT 24
Peak memory 198016 kb
Host smart-20bec0bf-14a8-41ed-bf51-aa5dda5118e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850420062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1850420062
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3060307343
Short name T415
Test name
Test status
Simulation time 29648465 ps
CPU time 0.54 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 194312 kb
Host smart-b96a1dd4-78e5-4b5c-be7f-3d28c250e48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060307343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3060307343
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1180342644
Short name T141
Test name
Test status
Simulation time 117509132 ps
CPU time 0.77 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 195928 kb
Host smart-0277aed8-cc70-48aa-a6cf-5c905337ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180342644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1180342644
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2969251708
Short name T157
Test name
Test status
Simulation time 611895464 ps
CPU time 12.81 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:31:51 PM PDT 24
Peak memory 196548 kb
Host smart-f5800ff7-d582-4c91-997d-c50c5bbc6217
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969251708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2969251708
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.832839631
Short name T478
Test name
Test status
Simulation time 72520370 ps
CPU time 1.02 seconds
Started Mar 26 12:31:35 PM PDT 24
Finished Mar 26 12:31:37 PM PDT 24
Peak memory 197700 kb
Host smart-c52a904a-acf1-46af-9a88-fd150ba8e742
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832839631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.832839631
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.53174369
Short name T597
Test name
Test status
Simulation time 72676544 ps
CPU time 1.06 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 195808 kb
Host smart-31ebb021-d1aa-4684-aa5f-452e30c34f41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53174369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.53174369
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.567041781
Short name T550
Test name
Test status
Simulation time 178146313 ps
CPU time 3.62 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:31:44 PM PDT 24
Peak memory 197972 kb
Host smart-f8ba9170-378c-47b2-8fa5-63d8bce1fa3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567041781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.567041781
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.930041638
Short name T171
Test name
Test status
Simulation time 176220736 ps
CPU time 2.89 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 197784 kb
Host smart-725941d5-26a8-4ebc-add4-66a7a5029972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930041638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
930041638
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3182159607
Short name T381
Test name
Test status
Simulation time 18830886 ps
CPU time 0.67 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 194756 kb
Host smart-751b116a-c75c-42ef-89a1-6dd011cd49ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182159607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3182159607
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1208782401
Short name T300
Test name
Test status
Simulation time 70913571 ps
CPU time 0.84 seconds
Started Mar 26 12:31:39 PM PDT 24
Finished Mar 26 12:31:40 PM PDT 24
Peak memory 196536 kb
Host smart-34fa234b-46c2-423f-afec-fec8e5546345
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208782401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1208782401
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.4202150437
Short name T306
Test name
Test status
Simulation time 30032360 ps
CPU time 1.27 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 197804 kb
Host smart-e588ea15-740e-4a62-8ec5-b078e4008352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202150437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.4202150437
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3140775547
Short name T241
Test name
Test status
Simulation time 80321172 ps
CPU time 1.24 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 195692 kb
Host smart-18043273-334b-4a1f-91ad-d87aebd454da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140775547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3140775547
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2462336880
Short name T666
Test name
Test status
Simulation time 124042526 ps
CPU time 1.23 seconds
Started Mar 26 12:31:34 PM PDT 24
Finished Mar 26 12:31:35 PM PDT 24
Peak memory 196648 kb
Host smart-be592f53-56ef-42a3-84bb-c209d09c5772
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462336880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2462336880
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3993965805
Short name T214
Test name
Test status
Simulation time 15603676893 ps
CPU time 93.69 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:33:14 PM PDT 24
Peak memory 198032 kb
Host smart-97bae53c-0b4d-49a5-ad87-96fcd490eaef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993965805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3993965805
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.943743575
Short name T646
Test name
Test status
Simulation time 115648632302 ps
CPU time 688.63 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:43:05 PM PDT 24
Peak memory 198080 kb
Host smart-c356bd86-c341-4403-873d-94a207778166
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=943743575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.943743575
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3516960574
Short name T130
Test name
Test status
Simulation time 11702868 ps
CPU time 0.57 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 193836 kb
Host smart-28843da3-bbad-4077-bde5-f77c1183e2ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516960574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3516960574
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1633279976
Short name T148
Test name
Test status
Simulation time 58721675 ps
CPU time 0.72 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 195960 kb
Host smart-0616233f-1576-4513-889b-03a343dd158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633279976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1633279976
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2317345657
Short name T433
Test name
Test status
Simulation time 319032196 ps
CPU time 15.23 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 195424 kb
Host smart-0620b50e-40de-453e-95e7-3fd5599d17e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317345657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2317345657
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4276622457
Short name T27
Test name
Test status
Simulation time 24112660 ps
CPU time 0.61 seconds
Started Mar 26 12:31:39 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 194160 kb
Host smart-08fa7964-7222-4c69-a2e3-3e4f306a79b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276622457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4276622457
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2780795937
Short name T269
Test name
Test status
Simulation time 112887790 ps
CPU time 0.78 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 195964 kb
Host smart-bfc9ca6b-a85c-406e-93b2-ef8cbb3fb8e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780795937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2780795937
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2133971523
Short name T182
Test name
Test status
Simulation time 30282034 ps
CPU time 1.37 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:31:42 PM PDT 24
Peak memory 196656 kb
Host smart-fc0d5a08-5c50-4b59-afd4-1c7f1fb515e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133971523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2133971523
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.91938383
Short name T528
Test name
Test status
Simulation time 335089374 ps
CPU time 2.9 seconds
Started Mar 26 12:31:39 PM PDT 24
Finished Mar 26 12:31:42 PM PDT 24
Peak memory 197152 kb
Host smart-58c08f47-1e7a-4c7a-bac6-b26eae546d25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91938383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.91938383
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2556767966
Short name T608
Test name
Test status
Simulation time 84575260 ps
CPU time 0.7 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 195184 kb
Host smart-66403925-24d5-4f8d-8c6a-656822d65a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556767966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2556767966
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.940709071
Short name T228
Test name
Test status
Simulation time 54373008 ps
CPU time 0.95 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 195940 kb
Host smart-2dfd0215-5987-4a15-981f-4075e34492f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940709071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.940709071
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2260714367
Short name T518
Test name
Test status
Simulation time 390158231 ps
CPU time 3.33 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:44 PM PDT 24
Peak memory 197952 kb
Host smart-2931b391-9585-4b21-a201-0b6ed4e0538b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260714367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2260714367
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1911175845
Short name T536
Test name
Test status
Simulation time 73456188 ps
CPU time 1.13 seconds
Started Mar 26 12:31:36 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 195544 kb
Host smart-15e3b1f4-0be1-4b5c-b018-a5ecf36f0b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911175845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1911175845
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.403484471
Short name T492
Test name
Test status
Simulation time 36500184 ps
CPU time 0.98 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 195620 kb
Host smart-7846f47e-3147-4b10-a05a-f3472f718b57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403484471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.403484471
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1304232696
Short name T671
Test name
Test status
Simulation time 8913215038 ps
CPU time 62.87 seconds
Started Mar 26 12:31:42 PM PDT 24
Finished Mar 26 12:32:45 PM PDT 24
Peak memory 198032 kb
Host smart-8821545f-c1ae-4479-bbf2-d28f3dcd17e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304232696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1304232696
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2668421983
Short name T120
Test name
Test status
Simulation time 54017796 ps
CPU time 0.59 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 194012 kb
Host smart-b1b9ff6b-e32b-4563-ab80-a56adbc05243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668421983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2668421983
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.704987840
Short name T710
Test name
Test status
Simulation time 90167316 ps
CPU time 0.88 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 195828 kb
Host smart-5382d17c-8f31-4ecc-a146-38f45003f509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704987840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.704987840
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.38329547
Short name T690
Test name
Test status
Simulation time 669146994 ps
CPU time 8.33 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:46 PM PDT 24
Peak memory 196808 kb
Host smart-4de38e68-2823-4995-bb60-c32256b47af2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38329547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stress
.38329547
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1700889551
Short name T353
Test name
Test status
Simulation time 29120221 ps
CPU time 0.62 seconds
Started Mar 26 12:31:39 PM PDT 24
Finished Mar 26 12:31:40 PM PDT 24
Peak memory 194380 kb
Host smart-4619acd8-ce6b-4f41-bc43-2a38b33552c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700889551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1700889551
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.109445780
Short name T175
Test name
Test status
Simulation time 48402464 ps
CPU time 1.2 seconds
Started Mar 26 12:31:39 PM PDT 24
Finished Mar 26 12:31:40 PM PDT 24
Peak memory 197016 kb
Host smart-bd9bf2b6-0908-441b-a4b5-9c9fb1faf5b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109445780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.109445780
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.419944766
Short name T404
Test name
Test status
Simulation time 58442564 ps
CPU time 1.2 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 196192 kb
Host smart-c2571317-5cd7-4973-8252-67bafb9b5542
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419944766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.419944766
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4145618088
Short name T583
Test name
Test status
Simulation time 1125221715 ps
CPU time 1.42 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 196640 kb
Host smart-b872ae28-1437-493a-a9cd-1d474038c37f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145618088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4145618088
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3634104732
Short name T217
Test name
Test status
Simulation time 76705151 ps
CPU time 0.68 seconds
Started Mar 26 12:31:42 PM PDT 24
Finished Mar 26 12:31:43 PM PDT 24
Peak memory 194056 kb
Host smart-b661ba1d-cb0f-47d0-8e0f-2debf87e004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634104732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3634104732
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1323083111
Short name T268
Test name
Test status
Simulation time 81915662 ps
CPU time 1.03 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 196632 kb
Host smart-9ad0a07f-d628-49ca-850f-4b655d4d037e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323083111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1323083111
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.4057018106
Short name T135
Test name
Test status
Simulation time 549933459 ps
CPU time 2.36 seconds
Started Mar 26 12:31:39 PM PDT 24
Finished Mar 26 12:31:42 PM PDT 24
Peak memory 197892 kb
Host smart-fda07c6e-27db-4063-8f93-a529fce112b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057018106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.4057018106
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.192349630
Short name T563
Test name
Test status
Simulation time 91185012 ps
CPU time 1.2 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 196828 kb
Host smart-60c13b09-5863-4f3f-83ea-fb3d332b17f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192349630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.192349630
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1767346093
Short name T717
Test name
Test status
Simulation time 483181698 ps
CPU time 1.29 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:31:40 PM PDT 24
Peak memory 196052 kb
Host smart-7e3cc5bb-6358-4937-882e-a42ea46ce3a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767346093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1767346093
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.845051230
Short name T462
Test name
Test status
Simulation time 8790606750 ps
CPU time 118.63 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:33:36 PM PDT 24
Peak memory 198040 kb
Host smart-39f80fa6-6de2-40bc-bcc9-4d175d7ec28e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845051230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.845051230
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.783884257
Short name T339
Test name
Test status
Simulation time 39928719 ps
CPU time 0.56 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 194760 kb
Host smart-412bcd62-eae0-45ed-b431-eaf04d940537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783884257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.783884257
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2528073765
Short name T429
Test name
Test status
Simulation time 29671748 ps
CPU time 0.73 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 195948 kb
Host smart-4f741605-edd4-4969-b969-ac8e942b4ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528073765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2528073765
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1977440695
Short name T519
Test name
Test status
Simulation time 1634214825 ps
CPU time 13.39 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:32:05 PM PDT 24
Peak memory 196508 kb
Host smart-1ee499ce-d566-42f4-a385-a3f8d55d8782
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977440695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1977440695
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1997756633
Short name T474
Test name
Test status
Simulation time 23739459 ps
CPU time 0.62 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:52 PM PDT 24
Peak memory 195184 kb
Host smart-02dee535-fbf8-4cb2-9655-e2ac5cd469d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997756633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1997756633
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2728915566
Short name T437
Test name
Test status
Simulation time 52278130 ps
CPU time 0.74 seconds
Started Mar 26 12:31:55 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 195532 kb
Host smart-6ca88f92-5daf-45a7-8a4c-ec71694f4c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728915566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2728915566
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3936850582
Short name T567
Test name
Test status
Simulation time 26834866 ps
CPU time 1.03 seconds
Started Mar 26 12:31:48 PM PDT 24
Finished Mar 26 12:31:49 PM PDT 24
Peak memory 197408 kb
Host smart-07c7215a-0066-4e04-af43-ba6a95c2b92d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936850582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3936850582
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2405419802
Short name T548
Test name
Test status
Simulation time 59773309 ps
CPU time 1.36 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 196824 kb
Host smart-885e80ae-972b-49de-86d3-3a746da13dec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405419802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2405419802
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3381529859
Short name T417
Test name
Test status
Simulation time 100598157 ps
CPU time 0.83 seconds
Started Mar 26 12:31:40 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 195924 kb
Host smart-0c75827a-507e-4734-b449-10f78cc14788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381529859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3381529859
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.354649132
Short name T494
Test name
Test status
Simulation time 17207874 ps
CPU time 0.77 seconds
Started Mar 26 12:31:38 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 195244 kb
Host smart-1b0da6ca-363c-4e04-bfb7-518ceab8cdd7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354649132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.354649132
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2958941947
Short name T283
Test name
Test status
Simulation time 134272367 ps
CPU time 3.14 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:55 PM PDT 24
Peak memory 197888 kb
Host smart-b4d09d78-8cc4-481e-94fc-fae8395d9798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958941947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2958941947
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1353366203
Short name T581
Test name
Test status
Simulation time 66130415 ps
CPU time 1.08 seconds
Started Mar 26 12:31:37 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 195588 kb
Host smart-2bea24da-ecd2-426d-bae1-2a4cdccbb3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353366203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1353366203
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1491727587
Short name T110
Test name
Test status
Simulation time 120685480 ps
CPU time 1.3 seconds
Started Mar 26 12:31:41 PM PDT 24
Finished Mar 26 12:31:42 PM PDT 24
Peak memory 195508 kb
Host smart-b165b186-22af-452b-b22a-09aeea79e9eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491727587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1491727587
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.462329356
Short name T383
Test name
Test status
Simulation time 17482295283 ps
CPU time 37.25 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:32:31 PM PDT 24
Peak memory 198056 kb
Host smart-d3ba0597-4817-473b-9e5c-fec739084575
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462329356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.462329356
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3106849723
Short name T62
Test name
Test status
Simulation time 17291544609 ps
CPU time 557.27 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:41:09 PM PDT 24
Peak memory 198104 kb
Host smart-d80c86d5-b02f-42af-98a2-a5e437828bb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3106849723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3106849723
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2166514360
Short name T276
Test name
Test status
Simulation time 12668265 ps
CPU time 0.58 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 194524 kb
Host smart-1f1363e4-85fb-48c1-b406-425fc0efba10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166514360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2166514360
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2688563028
Short name T25
Test name
Test status
Simulation time 73331218 ps
CPU time 0.66 seconds
Started Mar 26 12:31:50 PM PDT 24
Finished Mar 26 12:31:50 PM PDT 24
Peak memory 193972 kb
Host smart-8b1ace41-3493-4a47-9244-5bda9982f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688563028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2688563028
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1034738652
Short name T32
Test name
Test status
Simulation time 1046870583 ps
CPU time 26.33 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:32:18 PM PDT 24
Peak memory 197872 kb
Host smart-ba84edff-2d69-4f3a-ac84-36ec8dec9787
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034738652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1034738652
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3878852249
Short name T376
Test name
Test status
Simulation time 48278986 ps
CPU time 0.76 seconds
Started Mar 26 12:31:55 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 195864 kb
Host smart-12d44057-c5ac-4ae9-9a8f-fe56abae7d2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878852249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3878852249
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.99850495
Short name T235
Test name
Test status
Simulation time 370309931 ps
CPU time 1.34 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 195800 kb
Host smart-a103bced-f10f-4fd7-a279-2611c36c7bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99850495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.99850495
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.76098151
Short name T309
Test name
Test status
Simulation time 93655283 ps
CPU time 1.51 seconds
Started Mar 26 12:31:54 PM PDT 24
Finished Mar 26 12:31:55 PM PDT 24
Peak memory 196796 kb
Host smart-8fc963f2-279f-4bf1-a807-834d00a4e71c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76098151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.gpio_intr_with_filter_rand_intr_event.76098151
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2136899179
Short name T326
Test name
Test status
Simulation time 95918101 ps
CPU time 2.7 seconds
Started Mar 26 12:31:48 PM PDT 24
Finished Mar 26 12:31:51 PM PDT 24
Peak memory 197876 kb
Host smart-61e24ddf-6936-4f88-979a-9c20806b58a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136899179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2136899179
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.921532498
Short name T685
Test name
Test status
Simulation time 168689224 ps
CPU time 0.88 seconds
Started Mar 26 12:31:47 PM PDT 24
Finished Mar 26 12:31:48 PM PDT 24
Peak memory 195856 kb
Host smart-4033fce7-4afa-43cf-88d4-99bab7bc25ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921532498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.921532498
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1302600744
Short name T297
Test name
Test status
Simulation time 26793004 ps
CPU time 0.76 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 196032 kb
Host smart-7b1a9ce8-7531-4829-84d9-f3cb0f9c3bf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302600744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1302600744
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3654330606
Short name T714
Test name
Test status
Simulation time 856085910 ps
CPU time 2.77 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 197940 kb
Host smart-75c6bff2-bd61-42b9-bcc6-525f45dd9314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654330606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3654330606
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2593012920
Short name T481
Test name
Test status
Simulation time 93833409 ps
CPU time 1.22 seconds
Started Mar 26 12:31:50 PM PDT 24
Finished Mar 26 12:31:51 PM PDT 24
Peak memory 196608 kb
Host smart-c9aaa9ce-6c9f-4849-9de1-c97c53e4a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593012920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2593012920
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3238901293
Short name T512
Test name
Test status
Simulation time 82015100 ps
CPU time 1.31 seconds
Started Mar 26 12:31:49 PM PDT 24
Finished Mar 26 12:31:50 PM PDT 24
Peak memory 196516 kb
Host smart-a5a0514c-788d-4417-a963-7d61d3d38b19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238901293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3238901293
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.767448702
Short name T136
Test name
Test status
Simulation time 8645848850 ps
CPU time 102.2 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:33:35 PM PDT 24
Peak memory 198036 kb
Host smart-a5372d82-1f6b-4a4b-bfac-c2ef736559e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767448702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.767448702
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.580870759
Short name T576
Test name
Test status
Simulation time 40300599232 ps
CPU time 687.76 seconds
Started Mar 26 12:31:49 PM PDT 24
Finished Mar 26 12:43:17 PM PDT 24
Peak memory 198040 kb
Host smart-194d707a-181b-41d4-964b-63519f7d289e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=580870759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.580870759
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3381855150
Short name T670
Test name
Test status
Simulation time 47408802 ps
CPU time 0.57 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 194688 kb
Host smart-11670827-3cee-4899-997a-289fc091a8bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381855150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3381855150
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2188752292
Short name T153
Test name
Test status
Simulation time 55434034 ps
CPU time 0.85 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 195792 kb
Host smart-ed8f04f9-0a34-41da-a0ac-e7f50161a2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188752292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2188752292
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.972494669
Short name T296
Test name
Test status
Simulation time 353600961 ps
CPU time 17.95 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:32:09 PM PDT 24
Peak memory 196140 kb
Host smart-f319ced2-4a2a-4637-8149-1ce905d0493d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972494669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.972494669
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1324995562
Short name T310
Test name
Test status
Simulation time 192110005 ps
CPU time 0.85 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 195936 kb
Host smart-8ac7667f-bcd0-45ca-9f94-7430b3b9aae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324995562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1324995562
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1116561334
Short name T281
Test name
Test status
Simulation time 185507983 ps
CPU time 1.31 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 196932 kb
Host smart-c79ce229-a1be-40f9-aa37-a7ca144b1cb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116561334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1116561334
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1407488835
Short name T636
Test name
Test status
Simulation time 91846362 ps
CPU time 3.3 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:55 PM PDT 24
Peak memory 197880 kb
Host smart-57fb7ae6-b995-41ca-8321-4a3ef6bba1c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407488835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1407488835
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3616840214
Short name T606
Test name
Test status
Simulation time 291743729 ps
CPU time 2.07 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 195680 kb
Host smart-281aa045-e57b-48fb-840d-408eec8fd608
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616840214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3616840214
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2392537503
Short name T499
Test name
Test status
Simulation time 30473176 ps
CPU time 1.09 seconds
Started Mar 26 12:31:54 PM PDT 24
Finished Mar 26 12:31:55 PM PDT 24
Peak memory 196348 kb
Host smart-c757ac0c-b0f9-495e-9fba-273c4c291ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392537503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2392537503
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3980140070
Short name T293
Test name
Test status
Simulation time 348467423 ps
CPU time 0.89 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:52 PM PDT 24
Peak memory 195856 kb
Host smart-c8edc889-94b6-41d0-8c7f-d91d7f0e14e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980140070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3980140070
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.355855721
Short name T73
Test name
Test status
Simulation time 556485129 ps
CPU time 2.52 seconds
Started Mar 26 12:31:54 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 197580 kb
Host smart-f06d06f9-0c8c-4601-90c4-87452602354e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355855721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.355855721
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.719377308
Short name T557
Test name
Test status
Simulation time 56575950 ps
CPU time 1.1 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 196300 kb
Host smart-42dc888a-5ff2-477f-a564-f05624da2831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719377308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.719377308
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.4215606935
Short name T247
Test name
Test status
Simulation time 66298549 ps
CPU time 1.3 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 196932 kb
Host smart-0f7eeb57-2337-4535-99c3-3af30324bb70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215606935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4215606935
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3870836663
Short name T227
Test name
Test status
Simulation time 19301693625 ps
CPU time 122.82 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:33:56 PM PDT 24
Peak memory 197944 kb
Host smart-e6fd85b0-f4ac-4579-8131-c485d794deb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870836663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3870836663
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.980878213
Short name T315
Test name
Test status
Simulation time 64310653 ps
CPU time 0.54 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:52 PM PDT 24
Peak memory 193984 kb
Host smart-47bcf9f0-b2a5-4086-94cc-8eebb74da4da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980878213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.980878213
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2888770424
Short name T510
Test name
Test status
Simulation time 48929746 ps
CPU time 0.87 seconds
Started Mar 26 12:31:48 PM PDT 24
Finished Mar 26 12:31:49 PM PDT 24
Peak memory 195600 kb
Host smart-1730e4ee-a11f-414a-af70-1dcf3dc0b7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888770424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2888770424
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.18666665
Short name T596
Test name
Test status
Simulation time 329487436 ps
CPU time 15.87 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:32:09 PM PDT 24
Peak memory 196180 kb
Host smart-bcf91cb3-f56e-4934-88d5-b32ad8fd7946
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18666665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stress
.18666665
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.913134902
Short name T701
Test name
Test status
Simulation time 19619094 ps
CPU time 0.64 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:52 PM PDT 24
Peak memory 194400 kb
Host smart-719ece36-956b-4278-9ec0-1b8cd583292a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913134902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.913134902
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2818102157
Short name T629
Test name
Test status
Simulation time 150188407 ps
CPU time 0.82 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:52 PM PDT 24
Peak memory 195532 kb
Host smart-57ffd7c7-8231-433d-8306-5dc469b9c2fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818102157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2818102157
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3431079877
Short name T248
Test name
Test status
Simulation time 54689289 ps
CPU time 2.09 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 197896 kb
Host smart-49d486e8-da06-4ce5-8c5f-b66415be014c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431079877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3431079877
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.164525347
Short name T632
Test name
Test status
Simulation time 132627094 ps
CPU time 2.83 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 196928 kb
Host smart-b771e49b-e987-4b3b-94eb-41c88807bd08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164525347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
164525347
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2666832690
Short name T51
Test name
Test status
Simulation time 23728544 ps
CPU time 0.69 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 195892 kb
Host smart-6dc8165a-0023-4a64-852c-413b895894f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666832690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2666832690
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2884823532
Short name T697
Test name
Test status
Simulation time 140484512 ps
CPU time 0.89 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 195712 kb
Host smart-dfb1bc88-db3b-471e-a9a2-6958c89911cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884823532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2884823532
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3599463093
Short name T659
Test name
Test status
Simulation time 202790465 ps
CPU time 4.17 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 197944 kb
Host smart-a4eab3df-9b47-442c-b6d8-1bf55f6ebd43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599463093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3599463093
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1892141078
Short name T587
Test name
Test status
Simulation time 34928962 ps
CPU time 0.93 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 195336 kb
Host smart-fa62da4d-50b4-49bf-8564-f8faef71ce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892141078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1892141078
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.715244445
Short name T216
Test name
Test status
Simulation time 45924449 ps
CPU time 0.89 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:52 PM PDT 24
Peak memory 195300 kb
Host smart-ef0d289d-2eef-4801-943c-6fb9124acaee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715244445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.715244445
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3770866365
Short name T360
Test name
Test status
Simulation time 14593579643 ps
CPU time 168.1 seconds
Started Mar 26 12:31:54 PM PDT 24
Finished Mar 26 12:34:42 PM PDT 24
Peak memory 198048 kb
Host smart-5777bc5d-7b43-4081-af3d-573ff3066643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770866365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3770866365
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1873092472
Short name T566
Test name
Test status
Simulation time 19666900 ps
CPU time 0.57 seconds
Started Mar 26 12:31:53 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 193744 kb
Host smart-eecaa4fa-ff50-4ba7-8cdd-e2da9e7ab56b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873092472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1873092472
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3008217098
Short name T603
Test name
Test status
Simulation time 55123411 ps
CPU time 0.61 seconds
Started Mar 26 12:31:51 PM PDT 24
Finished Mar 26 12:31:51 PM PDT 24
Peak memory 193820 kb
Host smart-a5c47882-be24-431a-9cef-cf61df5b5445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008217098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3008217098
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3082412909
Short name T661
Test name
Test status
Simulation time 618640154 ps
CPU time 17.32 seconds
Started Mar 26 12:31:54 PM PDT 24
Finished Mar 26 12:32:11 PM PDT 24
Peak memory 197732 kb
Host smart-d44a4a0a-d355-4f82-8621-6a283a04ebdc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082412909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3082412909
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2778060348
Short name T419
Test name
Test status
Simulation time 287684199 ps
CPU time 0.86 seconds
Started Mar 26 12:31:55 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 195940 kb
Host smart-2a1cd4dc-2e65-45b1-abe1-61433714a1a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778060348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2778060348
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1906539365
Short name T321
Test name
Test status
Simulation time 41924623 ps
CPU time 0.83 seconds
Started Mar 26 12:31:56 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 196468 kb
Host smart-6a9f0008-bb91-4153-8359-d472c39ebadd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906539365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1906539365
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1587830669
Short name T509
Test name
Test status
Simulation time 61668631 ps
CPU time 1.21 seconds
Started Mar 26 12:31:55 PM PDT 24
Finished Mar 26 12:31:56 PM PDT 24
Peak memory 196164 kb
Host smart-33a99f16-2476-4463-9ccb-b079898fc9f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587830669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1587830669
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2810885049
Short name T295
Test name
Test status
Simulation time 132730588 ps
CPU time 2.01 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:54 PM PDT 24
Peak memory 196980 kb
Host smart-25e1841e-c542-4894-ba32-eb37f0bb9d19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810885049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2810885049
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2631507801
Short name T382
Test name
Test status
Simulation time 380370259 ps
CPU time 0.91 seconds
Started Mar 26 12:31:57 PM PDT 24
Finished Mar 26 12:31:58 PM PDT 24
Peak memory 196416 kb
Host smart-cac07541-3ba5-4e10-b754-41c0d3bb0702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631507801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2631507801
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2246654113
Short name T524
Test name
Test status
Simulation time 120720962 ps
CPU time 0.91 seconds
Started Mar 26 12:31:57 PM PDT 24
Finished Mar 26 12:31:58 PM PDT 24
Peak memory 195832 kb
Host smart-cf0e27b0-c7df-49d3-8c3f-02f04edb7c41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246654113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2246654113
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2867322444
Short name T414
Test name
Test status
Simulation time 62770631 ps
CPU time 2.72 seconds
Started Mar 26 12:31:57 PM PDT 24
Finished Mar 26 12:32:00 PM PDT 24
Peak memory 197804 kb
Host smart-22824748-2ae8-40c2-908c-9d51595966e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867322444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2867322444
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3094268089
Short name T183
Test name
Test status
Simulation time 279375578 ps
CPU time 1.38 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 196716 kb
Host smart-cf8b36f4-6eeb-48e3-b6af-6aad4ee259fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094268089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3094268089
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3385580395
Short name T207
Test name
Test status
Simulation time 438978365 ps
CPU time 1.33 seconds
Started Mar 26 12:31:54 PM PDT 24
Finished Mar 26 12:31:55 PM PDT 24
Peak memory 196656 kb
Host smart-ec160145-bc74-4d2d-a136-bf2f1c14848b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385580395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3385580395
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2775096204
Short name T319
Test name
Test status
Simulation time 23920588718 ps
CPU time 61.87 seconds
Started Mar 26 12:31:52 PM PDT 24
Finished Mar 26 12:32:54 PM PDT 24
Peak memory 198056 kb
Host smart-ac2e2d6b-6617-498e-b707-ad3027857a9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775096204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2775096204
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2133539551
Short name T19
Test name
Test status
Simulation time 14254979 ps
CPU time 0.57 seconds
Started Mar 26 12:29:48 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 193700 kb
Host smart-4d060bd9-2c53-4669-a469-99cc8556187b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133539551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2133539551
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1871844896
Short name T704
Test name
Test status
Simulation time 19596958 ps
CPU time 0.65 seconds
Started Mar 26 12:29:44 PM PDT 24
Finished Mar 26 12:29:45 PM PDT 24
Peak memory 194016 kb
Host smart-ecdfb341-ae40-4ecf-b98f-c9a8473a731a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871844896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1871844896
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3127562620
Short name T244
Test name
Test status
Simulation time 264290723 ps
CPU time 12.02 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:59 PM PDT 24
Peak memory 196824 kb
Host smart-dba4dfe4-ebe1-4d5f-912e-549bffd962b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127562620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3127562620
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1301226715
Short name T640
Test name
Test status
Simulation time 60506185 ps
CPU time 0.67 seconds
Started Mar 26 12:30:01 PM PDT 24
Finished Mar 26 12:30:02 PM PDT 24
Peak memory 194608 kb
Host smart-533017a8-f548-457f-b7bb-93652510043f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301226715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1301226715
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2378627128
Short name T620
Test name
Test status
Simulation time 74199357 ps
CPU time 1.17 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 196840 kb
Host smart-b4efe90a-de30-44fd-b6fa-e6eeb6b7125f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378627128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2378627128
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2984766875
Short name T522
Test name
Test status
Simulation time 57586920 ps
CPU time 2.09 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 196360 kb
Host smart-79ecaa1b-8929-4ef7-82dd-978073b329f1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984766875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2984766875
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2414540626
Short name T405
Test name
Test status
Simulation time 97740069 ps
CPU time 2.08 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 197960 kb
Host smart-daf05496-dd60-4464-a201-d662ab9070f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414540626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2414540626
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1416086113
Short name T385
Test name
Test status
Simulation time 117650880 ps
CPU time 1.11 seconds
Started Mar 26 12:29:45 PM PDT 24
Finished Mar 26 12:29:46 PM PDT 24
Peak memory 196772 kb
Host smart-55c4432e-f46e-4ecf-bce8-0aba4a1070d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416086113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1416086113
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1174338903
Short name T364
Test name
Test status
Simulation time 37633092 ps
CPU time 0.84 seconds
Started Mar 26 12:29:45 PM PDT 24
Finished Mar 26 12:29:46 PM PDT 24
Peak memory 195784 kb
Host smart-46ec92dc-da86-412b-a5cc-3f0749d681c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174338903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1174338903
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1321109632
Short name T279
Test name
Test status
Simulation time 603226133 ps
CPU time 2.54 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 197956 kb
Host smart-c888e0c5-b27f-48fa-9c84-c848fb9dc513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321109632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1321109632
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1990241538
Short name T370
Test name
Test status
Simulation time 76615711 ps
CPU time 1.31 seconds
Started Mar 26 12:29:48 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 197776 kb
Host smart-a366b072-40c9-4831-b987-ae2c6169313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990241538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1990241538
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1789137535
Short name T380
Test name
Test status
Simulation time 167357901 ps
CPU time 0.93 seconds
Started Mar 26 12:29:44 PM PDT 24
Finished Mar 26 12:29:45 PM PDT 24
Peak memory 196264 kb
Host smart-0fbdfad1-d2f9-4481-9830-27f499a8b70f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789137535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1789137535
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3284955423
Short name T599
Test name
Test status
Simulation time 32398212396 ps
CPU time 106.57 seconds
Started Mar 26 12:29:44 PM PDT 24
Finished Mar 26 12:31:31 PM PDT 24
Peak memory 197880 kb
Host smart-ddc16427-faaa-49c7-9a8e-92e1a6b189da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284955423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3284955423
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2537339181
Short name T551
Test name
Test status
Simulation time 50756644 ps
CPU time 0.55 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 193952 kb
Host smart-0cc41087-c17b-4652-b1e2-75aa3105be80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537339181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2537339181
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1750411031
Short name T399
Test name
Test status
Simulation time 189208698 ps
CPU time 0.81 seconds
Started Mar 26 12:29:47 PM PDT 24
Finished Mar 26 12:29:48 PM PDT 24
Peak memory 196460 kb
Host smart-5251ae6c-d344-46e2-977f-1ff667871811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750411031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1750411031
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4187597599
Short name T159
Test name
Test status
Simulation time 425491116 ps
CPU time 14.24 seconds
Started Mar 26 12:29:53 PM PDT 24
Finished Mar 26 12:30:08 PM PDT 24
Peak memory 196456 kb
Host smart-46e0cd95-e07e-4104-abdb-be977a78e8f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187597599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4187597599
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1664329399
Short name T167
Test name
Test status
Simulation time 108477607 ps
CPU time 0.66 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:54 PM PDT 24
Peak memory 194648 kb
Host smart-60305e75-d56c-421b-aa88-9a049082f900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664329399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1664329399
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4173295920
Short name T507
Test name
Test status
Simulation time 48859044 ps
CPU time 1.24 seconds
Started Mar 26 12:29:55 PM PDT 24
Finished Mar 26 12:29:57 PM PDT 24
Peak memory 196776 kb
Host smart-a12ccb0e-91b2-47ec-8807-eff50fc84690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173295920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4173295920
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1913372588
Short name T441
Test name
Test status
Simulation time 383036348 ps
CPU time 2.65 seconds
Started Mar 26 12:29:46 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 197904 kb
Host smart-e02eaf1a-bb3b-4299-8d22-f5dc6358c2f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913372588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1913372588
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.881026430
Short name T119
Test name
Test status
Simulation time 147180952 ps
CPU time 2.56 seconds
Started Mar 26 12:29:55 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 196856 kb
Host smart-aa33d1c4-bed2-4842-91dd-f4358d403fbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881026430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.881026430
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1682611448
Short name T123
Test name
Test status
Simulation time 180428904 ps
CPU time 0.98 seconds
Started Mar 26 12:29:48 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 195908 kb
Host smart-cb9c7a1c-57f9-47fe-bd11-ff2550a49abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682611448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1682611448
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3308378091
Short name T221
Test name
Test status
Simulation time 18285605 ps
CPU time 0.61 seconds
Started Mar 26 12:29:44 PM PDT 24
Finished Mar 26 12:29:45 PM PDT 24
Peak memory 194112 kb
Host smart-905b55bd-5f48-4c4c-993d-46e49dc90db1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308378091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3308378091
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1394395612
Short name T595
Test name
Test status
Simulation time 1062405531 ps
CPU time 4.14 seconds
Started Mar 26 12:29:52 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 197900 kb
Host smart-82e8529a-dfb4-45b3-98b6-5b3fb2f8e69a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394395612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1394395612
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.562119841
Short name T688
Test name
Test status
Simulation time 60168166 ps
CPU time 0.93 seconds
Started Mar 26 12:29:43 PM PDT 24
Finished Mar 26 12:29:44 PM PDT 24
Peak memory 196372 kb
Host smart-5d997b90-1356-4ac4-8afe-745b224342b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562119841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.562119841
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.946615944
Short name T168
Test name
Test status
Simulation time 135001118 ps
CPU time 0.76 seconds
Started Mar 26 12:30:01 PM PDT 24
Finished Mar 26 12:30:02 PM PDT 24
Peak memory 195136 kb
Host smart-47cc5424-9b31-4e83-bae4-4d3353f1ef5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946615944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.946615944
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1238037704
Short name T532
Test name
Test status
Simulation time 4636805324 ps
CPU time 115.32 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:31:53 PM PDT 24
Peak memory 197976 kb
Host smart-784ad426-f47e-4ae2-bc7e-1f6015b3fd0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238037704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1238037704
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.542029574
Short name T70
Test name
Test status
Simulation time 124891543 ps
CPU time 0.52 seconds
Started Mar 26 12:29:52 PM PDT 24
Finished Mar 26 12:29:52 PM PDT 24
Peak memory 192584 kb
Host smart-c8762f35-ec2a-49d2-8145-f3e507fdf31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542029574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.542029574
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3257679502
Short name T422
Test name
Test status
Simulation time 24215499 ps
CPU time 0.7 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:54 PM PDT 24
Peak memory 194872 kb
Host smart-8d37fdd4-2258-420f-89d4-54b43409d2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257679502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3257679502
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2656012944
Short name T132
Test name
Test status
Simulation time 554032865 ps
CPU time 19.6 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:30:14 PM PDT 24
Peak memory 196748 kb
Host smart-6c94385d-7388-4702-b73f-2659dc5a0b4c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656012944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2656012944
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1512346733
Short name T496
Test name
Test status
Simulation time 65802326 ps
CPU time 0.87 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 196728 kb
Host smart-86ac1e3f-531b-448e-9896-01fd02b13e74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512346733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1512346733
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1117224139
Short name T564
Test name
Test status
Simulation time 200907403 ps
CPU time 0.98 seconds
Started Mar 26 12:29:53 PM PDT 24
Finished Mar 26 12:29:54 PM PDT 24
Peak memory 196420 kb
Host smart-cd1b13ae-a0ff-481f-8873-93e81a237f77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117224139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1117224139
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1318413046
Short name T263
Test name
Test status
Simulation time 179167090 ps
CPU time 2.66 seconds
Started Mar 26 12:29:58 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 196220 kb
Host smart-c96bc1b6-6705-4f57-9f7b-f9ffcacdd8cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318413046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1318413046
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2296010728
Short name T413
Test name
Test status
Simulation time 86457556 ps
CPU time 1.87 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 196400 kb
Host smart-986b6c10-dcf7-4844-9b35-5bae4ca2a8ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296010728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2296010728
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4070109410
Short name T644
Test name
Test status
Simulation time 140846915 ps
CPU time 0.98 seconds
Started Mar 26 12:29:59 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 195836 kb
Host smart-19a80e53-7086-4346-8ce7-4a8a80280db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070109410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4070109410
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2216918997
Short name T238
Test name
Test status
Simulation time 328961980 ps
CPU time 0.77 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:57 PM PDT 24
Peak memory 196148 kb
Host smart-f0185d08-4e62-4dca-a058-eff58d73af80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216918997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2216918997
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3935943384
Short name T705
Test name
Test status
Simulation time 493597352 ps
CPU time 4.55 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:30:02 PM PDT 24
Peak memory 197864 kb
Host smart-879594c9-d76b-42e3-bba1-af845eaea457
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935943384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3935943384
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1758717552
Short name T140
Test name
Test status
Simulation time 288042907 ps
CPU time 1.3 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 196672 kb
Host smart-b3b5d149-ee5b-4e4b-a851-0c343356bcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758717552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1758717552
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3211726996
Short name T340
Test name
Test status
Simulation time 184264376 ps
CPU time 0.83 seconds
Started Mar 26 12:29:52 PM PDT 24
Finished Mar 26 12:29:53 PM PDT 24
Peak memory 197084 kb
Host smart-f6cb1a5e-5ecf-4e99-849a-6f4cb313e8d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211726996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3211726996
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.456624887
Short name T351
Test name
Test status
Simulation time 29940801496 ps
CPU time 190.78 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:33:07 PM PDT 24
Peak memory 198008 kb
Host smart-af70af32-2987-4644-b9ad-a580ccf325ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456624887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.456624887
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.969774274
Short name T324
Test name
Test status
Simulation time 61191251734 ps
CPU time 816.8 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:43:31 PM PDT 24
Peak memory 198040 kb
Host smart-e0367812-9f20-4996-9632-aa9b2a8fd860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=969774274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.969774274
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3680016581
Short name T22
Test name
Test status
Simulation time 12171016 ps
CPU time 0.58 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 194664 kb
Host smart-fd85fd43-79a4-473d-8142-3670b5a37cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680016581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3680016581
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4262153859
Short name T395
Test name
Test status
Simulation time 162638396 ps
CPU time 0.91 seconds
Started Mar 26 12:30:00 PM PDT 24
Finished Mar 26 12:30:01 PM PDT 24
Peak memory 195764 kb
Host smart-b774c471-2f36-41fe-856f-921f5173953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262153859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4262153859
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1566162523
Short name T555
Test name
Test status
Simulation time 101498435 ps
CPU time 3.74 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 196264 kb
Host smart-b89ecea4-47a4-43e7-80ba-82f62fe2300c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566162523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1566162523
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.427943527
Short name T160
Test name
Test status
Simulation time 222181797 ps
CPU time 0.95 seconds
Started Mar 26 12:29:55 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 196500 kb
Host smart-e58e68e1-0b63-4207-b2ee-ffc5b2a91c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427943527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.427943527
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.495095685
Short name T438
Test name
Test status
Simulation time 290146446 ps
CPU time 1.08 seconds
Started Mar 26 12:29:59 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 195824 kb
Host smart-1b6db5fd-e233-4190-a3a1-9b655319bb6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495095685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.495095685
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2918171059
Short name T106
Test name
Test status
Simulation time 78809479 ps
CPU time 3.08 seconds
Started Mar 26 12:29:55 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 197900 kb
Host smart-b3ebed17-201d-4677-8c6a-6d527dbd4fe2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918171059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2918171059
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.658095124
Short name T294
Test name
Test status
Simulation time 182552366 ps
CPU time 1.01 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 195980 kb
Host smart-a4c4ee32-3ba6-4371-9547-ef5295127a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658095124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.658095124
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.746365114
Short name T698
Test name
Test status
Simulation time 37083137 ps
CPU time 0.77 seconds
Started Mar 26 12:29:55 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 195204 kb
Host smart-0024d8c0-5ac0-45cc-9b44-627f9f9e5a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746365114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.746365114
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3818017408
Short name T242
Test name
Test status
Simulation time 26250849 ps
CPU time 1.02 seconds
Started Mar 26 12:29:58 PM PDT 24
Finished Mar 26 12:29:59 PM PDT 24
Peak memory 196416 kb
Host smart-8e04bccb-c854-45a3-b4d2-8909c8325bae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818017408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3818017408
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3852737259
Short name T653
Test name
Test status
Simulation time 393633093 ps
CPU time 5.85 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 197816 kb
Host smart-ae7c5b09-78b0-42ac-9e54-30338b88ef2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852737259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3852737259
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3028413286
Short name T155
Test name
Test status
Simulation time 93123439 ps
CPU time 1.2 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 195612 kb
Host smart-08204e18-af5b-433c-903e-16889386040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028413286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3028413286
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1013779023
Short name T163
Test name
Test status
Simulation time 29969852 ps
CPU time 0.75 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 194984 kb
Host smart-c07854f3-2dad-42bb-8e6e-e80919c346cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013779023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1013779023
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.397084740
Short name T588
Test name
Test status
Simulation time 9303339441 ps
CPU time 127.67 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:32:04 PM PDT 24
Peak memory 197968 kb
Host smart-8fa64e32-49f1-495b-a161-2ee2466b246e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397084740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.397084740
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.367133694
Short name T147
Test name
Test status
Simulation time 12799534 ps
CPU time 0.56 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:57 PM PDT 24
Peak memory 193768 kb
Host smart-c76074e5-3987-43ed-91f0-78830fd0c69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367133694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.367133694
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1613937742
Short name T347
Test name
Test status
Simulation time 126808547 ps
CPU time 0.71 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:57 PM PDT 24
Peak memory 195232 kb
Host smart-faebe05e-5b07-4bd0-9599-629ab6ed17bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613937742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1613937742
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2318088466
Short name T484
Test name
Test status
Simulation time 398908242 ps
CPU time 13.57 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:30:09 PM PDT 24
Peak memory 196416 kb
Host smart-ccaee65c-59cc-413b-a509-4557f1e4d514
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318088466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2318088466
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3031679863
Short name T663
Test name
Test status
Simulation time 72281814 ps
CPU time 1.04 seconds
Started Mar 26 12:29:53 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 197668 kb
Host smart-977388f9-51e7-45ea-b8e8-cb0a5c5996b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031679863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3031679863
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1345476310
Short name T570
Test name
Test status
Simulation time 39667726 ps
CPU time 0.77 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:57 PM PDT 24
Peak memory 195276 kb
Host smart-2201b3c1-32b5-416a-a9f4-e5f62fd650c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345476310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1345476310
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.992824939
Short name T549
Test name
Test status
Simulation time 41268338 ps
CPU time 1.52 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 196736 kb
Host smart-e7801099-f864-4177-934d-63d26622fcdf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992824939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.992824939
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1255685406
Short name T544
Test name
Test status
Simulation time 705129789 ps
CPU time 3 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 197020 kb
Host smart-e98cc8b2-34a9-4b56-a6e5-e34162811218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255685406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1255685406
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1914877939
Short name T232
Test name
Test status
Simulation time 252755325 ps
CPU time 1.23 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 197824 kb
Host smart-3bf83b99-4101-41d6-80b8-80d626ee7dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914877939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1914877939
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.471989164
Short name T368
Test name
Test status
Simulation time 71507425 ps
CPU time 0.84 seconds
Started Mar 26 12:29:57 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 196432 kb
Host smart-8711f898-554d-42a6-baff-4f2d700c8c46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471989164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.471989164
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3358494997
Short name T169
Test name
Test status
Simulation time 222732452 ps
CPU time 4.72 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 197804 kb
Host smart-bdae3650-bd8e-43f4-a5bd-e607e1e4af91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358494997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3358494997
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.47146644
Short name T189
Test name
Test status
Simulation time 272547790 ps
CPU time 0.93 seconds
Started Mar 26 12:29:52 PM PDT 24
Finished Mar 26 12:29:53 PM PDT 24
Peak memory 195736 kb
Host smart-4f9cc02b-b614-4bb2-9eeb-1524b864a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47146644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.47146644
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2738937514
Short name T590
Test name
Test status
Simulation time 276865413 ps
CPU time 1.23 seconds
Started Mar 26 12:29:54 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 197884 kb
Host smart-35ebf22d-5854-47fb-a5d1-332b54267815
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738937514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2738937514
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1031733106
Short name T129
Test name
Test status
Simulation time 948604638 ps
CPU time 20.66 seconds
Started Mar 26 12:29:55 PM PDT 24
Finished Mar 26 12:30:15 PM PDT 24
Peak memory 197876 kb
Host smart-64500dd6-bf34-43e7-95cd-70584ef72c65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031733106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1031733106
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.605916226
Short name T63
Test name
Test status
Simulation time 120314284684 ps
CPU time 2445.95 seconds
Started Mar 26 12:29:56 PM PDT 24
Finished Mar 26 01:10:42 PM PDT 24
Peak memory 198116 kb
Host smart-d93b769f-75a1-48a5-8e52-6eae9c672f5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=605916226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.605916226
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1227988210
Short name T889
Test name
Test status
Simulation time 65799643 ps
CPU time 1.29 seconds
Started Mar 26 12:24:54 PM PDT 24
Finished Mar 26 12:24:56 PM PDT 24
Peak memory 198572 kb
Host smart-941d935d-62cf-4939-b37c-a36a1923e14d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1227988210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1227988210
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639342223
Short name T893
Test name
Test status
Simulation time 91379800 ps
CPU time 0.81 seconds
Started Mar 26 12:25:03 PM PDT 24
Finished Mar 26 12:25:04 PM PDT 24
Peak memory 192300 kb
Host smart-d5f9056a-3d2a-41ad-abf8-a3a72fac18c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639342223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1639342223
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.16942597
Short name T876
Test name
Test status
Simulation time 43565873 ps
CPU time 1.24 seconds
Started Mar 26 12:24:47 PM PDT 24
Finished Mar 26 12:24:49 PM PDT 24
Peak memory 192092 kb
Host smart-49413289-598e-4fe9-ba20-b24a40e20d82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=16942597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.16942597
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.598011648
Short name T917
Test name
Test status
Simulation time 69162254 ps
CPU time 1.27 seconds
Started Mar 26 12:26:33 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 192072 kb
Host smart-443aa673-7c63-4cd7-9e8b-1c2648ee348c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598011648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.598011648
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2629505701
Short name T888
Test name
Test status
Simulation time 70513856 ps
CPU time 1.14 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 192132 kb
Host smart-2426105c-228b-48eb-a9e2-d8be506e5a04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2629505701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2629505701
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3506690309
Short name T880
Test name
Test status
Simulation time 178650867 ps
CPU time 1.24 seconds
Started Mar 26 12:25:06 PM PDT 24
Finished Mar 26 12:25:08 PM PDT 24
Peak memory 192460 kb
Host smart-e97355ea-9881-4367-b981-b02639b8fb94
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506690309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3506690309
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3126299796
Short name T868
Test name
Test status
Simulation time 162028370 ps
CPU time 1.35 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:11 PM PDT 24
Peak memory 192168 kb
Host smart-9957e99f-8349-4796-b15b-5d06f6322fc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3126299796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3126299796
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.792706089
Short name T873
Test name
Test status
Simulation time 311527767 ps
CPU time 1.27 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:11 PM PDT 24
Peak memory 192112 kb
Host smart-a5165761-e01b-422f-88e6-07f72f1a4b5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792706089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.792706089
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2227502594
Short name T850
Test name
Test status
Simulation time 49838079 ps
CPU time 1.26 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:45 PM PDT 24
Peak memory 192136 kb
Host smart-3a0b6a4e-9f0c-4190-9ac9-da04a08a1e3d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2227502594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2227502594
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1136894290
Short name T866
Test name
Test status
Simulation time 26210612 ps
CPU time 0.89 seconds
Started Mar 26 12:25:14 PM PDT 24
Finished Mar 26 12:25:15 PM PDT 24
Peak memory 192460 kb
Host smart-55438936-43f7-4399-9e9a-dd63f23ee38b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136894290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1136894290
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.118757314
Short name T895
Test name
Test status
Simulation time 116242261 ps
CPU time 1.17 seconds
Started Mar 26 12:26:45 PM PDT 24
Finished Mar 26 12:26:46 PM PDT 24
Peak memory 197084 kb
Host smart-f788a2a2-f381-4264-b4bd-a09a8241c834
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=118757314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.118757314
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2889301493
Short name T857
Test name
Test status
Simulation time 53579091 ps
CPU time 1.04 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:10 PM PDT 24
Peak memory 192112 kb
Host smart-46530d3f-5def-4933-bb49-a906d95717a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889301493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2889301493
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1152280015
Short name T886
Test name
Test status
Simulation time 202477786 ps
CPU time 0.84 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 197668 kb
Host smart-94435fc2-3bd4-4556-80ba-f378e86a667f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1152280015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1152280015
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3667099888
Short name T884
Test name
Test status
Simulation time 176255129 ps
CPU time 1.05 seconds
Started Mar 26 12:25:19 PM PDT 24
Finished Mar 26 12:25:21 PM PDT 24
Peak memory 192460 kb
Host smart-3402100d-a13f-4cb0-8628-ec1f4562bcc5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667099888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3667099888
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2159292873
Short name T924
Test name
Test status
Simulation time 146753983 ps
CPU time 0.88 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 197488 kb
Host smart-0801096d-256b-42d8-a378-d6116c3bf81c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2159292873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2159292873
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1984751951
Short name T890
Test name
Test status
Simulation time 149037122 ps
CPU time 0.93 seconds
Started Mar 26 12:25:19 PM PDT 24
Finished Mar 26 12:25:21 PM PDT 24
Peak memory 192120 kb
Host smart-1b8040dc-bf7b-4a0b-a4fd-bfccbdddb3fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984751951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1984751951
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.875831649
Short name T932
Test name
Test status
Simulation time 114069317 ps
CPU time 1.46 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:11 PM PDT 24
Peak memory 192112 kb
Host smart-e22d8256-5fa6-4861-bc89-5720776e0678
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=875831649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.875831649
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3668861734
Short name T891
Test name
Test status
Simulation time 118801330 ps
CPU time 1.01 seconds
Started Mar 26 12:25:02 PM PDT 24
Finished Mar 26 12:25:03 PM PDT 24
Peak memory 191940 kb
Host smart-274abc5e-2f06-4f7e-bf35-b10bf63637fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668861734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3668861734
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.867481348
Short name T882
Test name
Test status
Simulation time 31052772 ps
CPU time 0.83 seconds
Started Mar 26 12:25:42 PM PDT 24
Finished Mar 26 12:25:43 PM PDT 24
Peak memory 191928 kb
Host smart-258e8925-3a3b-4619-b2fd-63a7b9e8c1d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=867481348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.867481348
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3243357308
Short name T923
Test name
Test status
Simulation time 219947700 ps
CPU time 0.99 seconds
Started Mar 26 12:26:06 PM PDT 24
Finished Mar 26 12:26:07 PM PDT 24
Peak memory 192116 kb
Host smart-2bc83946-a12e-44eb-b041-30075f7026b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243357308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3243357308
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1964105349
Short name T881
Test name
Test status
Simulation time 139205706 ps
CPU time 1.2 seconds
Started Mar 26 12:26:26 PM PDT 24
Finished Mar 26 12:26:28 PM PDT 24
Peak memory 197244 kb
Host smart-f05e75d8-a4bf-4826-918e-55a4e89a1df2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1964105349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1964105349
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.645171044
Short name T937
Test name
Test status
Simulation time 53288493 ps
CPU time 1.02 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:27:04 PM PDT 24
Peak memory 192232 kb
Host smart-0deddb99-ff96-4e97-9cd7-189a24c93ef1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645171044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.645171044
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.349217742
Short name T883
Test name
Test status
Simulation time 56465656 ps
CPU time 0.96 seconds
Started Mar 26 12:26:05 PM PDT 24
Finished Mar 26 12:26:06 PM PDT 24
Peak memory 192056 kb
Host smart-9c35c9a8-0362-4112-a601-193e18e3174b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=349217742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.349217742
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1516537354
Short name T898
Test name
Test status
Simulation time 179016881 ps
CPU time 0.87 seconds
Started Mar 26 12:26:14 PM PDT 24
Finished Mar 26 12:26:14 PM PDT 24
Peak memory 191952 kb
Host smart-51187e54-3a20-49fa-964c-63d84e50dfcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516537354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1516537354
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.81400385
Short name T860
Test name
Test status
Simulation time 88406126 ps
CPU time 0.7 seconds
Started Mar 26 12:26:21 PM PDT 24
Finished Mar 26 12:26:22 PM PDT 24
Peak memory 192052 kb
Host smart-b3e0f5bb-5445-4426-b611-34281c6958fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=81400385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.81400385
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2555915308
Short name T859
Test name
Test status
Simulation time 78511360 ps
CPU time 1.27 seconds
Started Mar 26 12:25:01 PM PDT 24
Finished Mar 26 12:25:02 PM PDT 24
Peak memory 192120 kb
Host smart-22cbbc63-ec6a-4bb9-8b24-4c5b91b271c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555915308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2555915308
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4053323085
Short name T853
Test name
Test status
Simulation time 84186726 ps
CPU time 0.77 seconds
Started Mar 26 12:25:17 PM PDT 24
Finished Mar 26 12:25:17 PM PDT 24
Peak memory 191980 kb
Host smart-0ca592ea-551a-41d3-a3d7-a5c2a0c0d078
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4053323085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4053323085
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1657190146
Short name T912
Test name
Test status
Simulation time 180418837 ps
CPU time 0.88 seconds
Started Mar 26 12:25:20 PM PDT 24
Finished Mar 26 12:25:21 PM PDT 24
Peak memory 198264 kb
Host smart-e839b7e1-f4c1-4c80-a024-e2191e71dd35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657190146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1657190146
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.240090442
Short name T928
Test name
Test status
Simulation time 104518681 ps
CPU time 1.04 seconds
Started Mar 26 12:26:28 PM PDT 24
Finished Mar 26 12:26:29 PM PDT 24
Peak memory 198404 kb
Host smart-3b7ec88f-175f-48f4-ac9a-b76955eb2d86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=240090442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.240090442
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3072796299
Short name T941
Test name
Test status
Simulation time 57692404 ps
CPU time 1.24 seconds
Started Mar 26 12:25:20 PM PDT 24
Finished Mar 26 12:25:22 PM PDT 24
Peak memory 192120 kb
Host smart-a9e7c66c-1fdf-4c79-8a38-8f9932081495
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072796299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3072796299
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3800216024
Short name T906
Test name
Test status
Simulation time 72721013 ps
CPU time 0.8 seconds
Started Mar 26 12:25:18 PM PDT 24
Finished Mar 26 12:25:18 PM PDT 24
Peak memory 191956 kb
Host smart-dfce6338-af0c-4ae7-b799-61a067c0e2f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3800216024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3800216024
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.843764877
Short name T904
Test name
Test status
Simulation time 217819421 ps
CPU time 1.25 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:26:23 PM PDT 24
Peak memory 192452 kb
Host smart-de08526f-8aaf-4784-acb9-19487123fe7f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843764877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.843764877
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3288886953
Short name T847
Test name
Test status
Simulation time 139258999 ps
CPU time 1.24 seconds
Started Mar 26 12:25:19 PM PDT 24
Finished Mar 26 12:25:20 PM PDT 24
Peak memory 192088 kb
Host smart-6ce931fd-a607-439b-8abd-b88b9aec36ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3288886953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3288886953
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2637422275
Short name T926
Test name
Test status
Simulation time 137753065 ps
CPU time 0.88 seconds
Started Mar 26 12:25:30 PM PDT 24
Finished Mar 26 12:25:31 PM PDT 24
Peak memory 191964 kb
Host smart-132934be-3cb5-437e-aa29-3bcb594becc3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637422275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2637422275
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3770174148
Short name T916
Test name
Test status
Simulation time 1403426607 ps
CPU time 1.22 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:22 PM PDT 24
Peak memory 198512 kb
Host smart-277c7399-47dc-4025-9070-6b00d434e117
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3770174148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3770174148
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3845850640
Short name T864
Test name
Test status
Simulation time 27203682 ps
CPU time 0.79 seconds
Started Mar 26 12:25:18 PM PDT 24
Finished Mar 26 12:25:18 PM PDT 24
Peak memory 191940 kb
Host smart-f45420a6-1837-407f-a976-a5829a565388
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845850640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3845850640
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1098769865
Short name T854
Test name
Test status
Simulation time 66308892 ps
CPU time 1.21 seconds
Started Mar 26 12:25:20 PM PDT 24
Finished Mar 26 12:25:22 PM PDT 24
Peak memory 197076 kb
Host smart-794279ad-cf32-4ead-95b5-f7850cd14476
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1098769865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1098769865
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1188142205
Short name T879
Test name
Test status
Simulation time 51149530 ps
CPU time 1.37 seconds
Started Mar 26 12:25:19 PM PDT 24
Finished Mar 26 12:25:20 PM PDT 24
Peak memory 192168 kb
Host smart-4b7852b3-a2ea-4167-bb0f-c24b9029bd49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188142205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1188142205
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2162466241
Short name T870
Test name
Test status
Simulation time 49554697 ps
CPU time 1.07 seconds
Started Mar 26 12:25:32 PM PDT 24
Finished Mar 26 12:25:34 PM PDT 24
Peak memory 192084 kb
Host smart-0069be17-95db-4e84-b6e5-691e81b1e10c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2162466241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2162466241
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1146010940
Short name T938
Test name
Test status
Simulation time 62468643 ps
CPU time 1.15 seconds
Started Mar 26 12:25:32 PM PDT 24
Finished Mar 26 12:25:33 PM PDT 24
Peak memory 198456 kb
Host smart-fb237a8a-0fb1-490e-961d-69efb041a0ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146010940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1146010940
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1535666138
Short name T903
Test name
Test status
Simulation time 211595410 ps
CPU time 0.91 seconds
Started Mar 26 12:25:36 PM PDT 24
Finished Mar 26 12:25:37 PM PDT 24
Peak memory 192176 kb
Host smart-a2848092-e783-476c-9aee-49f0db22413a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1535666138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1535666138
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3132035593
Short name T871
Test name
Test status
Simulation time 194576671 ps
CPU time 1.26 seconds
Started Mar 26 12:25:35 PM PDT 24
Finished Mar 26 12:25:37 PM PDT 24
Peak memory 198444 kb
Host smart-c2074add-40ec-4e5c-94fb-3daf47bdad7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132035593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3132035593
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1075720426
Short name T846
Test name
Test status
Simulation time 41813814 ps
CPU time 1.08 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:26:39 PM PDT 24
Peak memory 192260 kb
Host smart-087c2de4-9391-4543-87f9-d6776c47f8e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1075720426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1075720426
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1001996121
Short name T848
Test name
Test status
Simulation time 71048332 ps
CPU time 1.22 seconds
Started Mar 26 12:25:32 PM PDT 24
Finished Mar 26 12:25:33 PM PDT 24
Peak memory 192104 kb
Host smart-af8d9c22-a932-4476-9819-37eb61a2a172
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001996121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1001996121
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2775837107
Short name T915
Test name
Test status
Simulation time 193163660 ps
CPU time 0.91 seconds
Started Mar 26 12:25:32 PM PDT 24
Finished Mar 26 12:25:33 PM PDT 24
Peak memory 191956 kb
Host smart-36e7e5fc-4c5b-4b58-9ab1-6a4def840e98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2775837107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2775837107
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2772639313
Short name T905
Test name
Test status
Simulation time 86222107 ps
CPU time 0.97 seconds
Started Mar 26 12:25:34 PM PDT 24
Finished Mar 26 12:25:35 PM PDT 24
Peak memory 198528 kb
Host smart-561f2b73-4fc2-451e-b478-1b2aa56a145a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772639313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2772639313
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3228821634
Short name T849
Test name
Test status
Simulation time 99005057 ps
CPU time 0.95 seconds
Started Mar 26 12:24:57 PM PDT 24
Finished Mar 26 12:24:58 PM PDT 24
Peak memory 191984 kb
Host smart-9e514770-a6e8-4cd5-98b0-5897b84c5d37
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3228821634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3228821634
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1524140920
Short name T845
Test name
Test status
Simulation time 50636758 ps
CPU time 0.97 seconds
Started Mar 26 12:24:52 PM PDT 24
Finished Mar 26 12:24:53 PM PDT 24
Peak memory 192120 kb
Host smart-608e3c99-71f3-4732-8fe8-feca1afdb9f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524140920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1524140920
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3786603798
Short name T913
Test name
Test status
Simulation time 196368231 ps
CPU time 1.17 seconds
Started Mar 26 12:25:30 PM PDT 24
Finished Mar 26 12:25:31 PM PDT 24
Peak memory 192124 kb
Host smart-783d7784-02d4-4569-84d3-5f9d48d224d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3786603798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3786603798
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1778959278
Short name T936
Test name
Test status
Simulation time 29797945 ps
CPU time 0.89 seconds
Started Mar 26 12:25:31 PM PDT 24
Finished Mar 26 12:25:32 PM PDT 24
Peak memory 197780 kb
Host smart-4a41c45b-489d-4653-a55a-38eb8133bc0c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778959278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1778959278
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1063861195
Short name T894
Test name
Test status
Simulation time 207288122 ps
CPU time 1.08 seconds
Started Mar 26 12:26:34 PM PDT 24
Finished Mar 26 12:26:35 PM PDT 24
Peak memory 192104 kb
Host smart-23e7315a-3efe-44c0-a6cd-ff0f041ca962
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1063861195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1063861195
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4163942253
Short name T897
Test name
Test status
Simulation time 141402329 ps
CPU time 1.02 seconds
Started Mar 26 12:25:34 PM PDT 24
Finished Mar 26 12:25:35 PM PDT 24
Peak memory 192120 kb
Host smart-e9bdcd20-c77c-4d61-ad88-3e7c8687fcc3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163942253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4163942253
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4211727867
Short name T942
Test name
Test status
Simulation time 36942566 ps
CPU time 0.85 seconds
Started Mar 26 12:25:33 PM PDT 24
Finished Mar 26 12:25:34 PM PDT 24
Peak memory 198296 kb
Host smart-7ead33de-9e86-41bc-942b-ea8516a6ae80
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4211727867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4211727867
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3581458651
Short name T851
Test name
Test status
Simulation time 170205369 ps
CPU time 1.01 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:26:13 PM PDT 24
Peak memory 192248 kb
Host smart-6b5a3c39-bbff-4f42-ae39-9315017f2b64
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581458651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3581458651
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2974651798
Short name T927
Test name
Test status
Simulation time 110857759 ps
CPU time 1.14 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:26:48 PM PDT 24
Peak memory 192144 kb
Host smart-5c71de63-41c7-4596-9990-a7ae121533a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2974651798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2974651798
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1920198693
Short name T885
Test name
Test status
Simulation time 23158280 ps
CPU time 0.66 seconds
Started Mar 26 12:26:13 PM PDT 24
Finished Mar 26 12:26:14 PM PDT 24
Peak memory 191960 kb
Host smart-2b1ddeae-f839-43cf-a2aa-ee6d9c4a7985
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920198693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1920198693
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1020436471
Short name T930
Test name
Test status
Simulation time 162003026 ps
CPU time 0.98 seconds
Started Mar 26 12:25:34 PM PDT 24
Finished Mar 26 12:25:35 PM PDT 24
Peak memory 192176 kb
Host smart-2f5fd9f1-fdfb-45e6-87fb-6ef45c169381
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1020436471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1020436471
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.73530571
Short name T872
Test name
Test status
Simulation time 155421098 ps
CPU time 1.23 seconds
Started Mar 26 12:26:08 PM PDT 24
Finished Mar 26 12:26:10 PM PDT 24
Peak memory 192096 kb
Host smart-de473924-ab2e-4809-b518-fa5662e16ac6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73530571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.73530571
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3911232959
Short name T865
Test name
Test status
Simulation time 537404229 ps
CPU time 1.32 seconds
Started Mar 26 12:26:01 PM PDT 24
Finished Mar 26 12:26:02 PM PDT 24
Peak memory 192496 kb
Host smart-73eee1d7-a74a-494b-aefa-0ce0f316e006
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3911232959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3911232959
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2234084345
Short name T939
Test name
Test status
Simulation time 57256756 ps
CPU time 0.9 seconds
Started Mar 26 12:26:23 PM PDT 24
Finished Mar 26 12:26:24 PM PDT 24
Peak memory 192116 kb
Host smart-0ea7509b-5c43-4a60-85a5-4d7cd8d5ddb3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234084345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2234084345
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2088398979
Short name T925
Test name
Test status
Simulation time 86562879 ps
CPU time 1.02 seconds
Started Mar 26 12:26:44 PM PDT 24
Finished Mar 26 12:26:46 PM PDT 24
Peak memory 196928 kb
Host smart-d63c0b1a-6eee-4f95-bd0d-3e14089f7561
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2088398979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2088398979
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2252579237
Short name T902
Test name
Test status
Simulation time 129336848 ps
CPU time 1.27 seconds
Started Mar 26 12:25:35 PM PDT 24
Finished Mar 26 12:25:36 PM PDT 24
Peak memory 192152 kb
Host smart-71bd6698-0027-4525-bd42-d42ba44e53d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252579237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2252579237
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2869804541
Short name T935
Test name
Test status
Simulation time 48343541 ps
CPU time 0.89 seconds
Started Mar 26 12:25:34 PM PDT 24
Finished Mar 26 12:25:35 PM PDT 24
Peak memory 197760 kb
Host smart-26143b58-cadd-4449-a579-955941617594
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2869804541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2869804541
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2484468875
Short name T907
Test name
Test status
Simulation time 54145127 ps
CPU time 1.05 seconds
Started Mar 26 12:25:34 PM PDT 24
Finished Mar 26 12:25:36 PM PDT 24
Peak memory 196940 kb
Host smart-dcc25fe0-e610-4570-9051-3efd01a08eff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484468875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2484468875
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2283323510
Short name T911
Test name
Test status
Simulation time 55877207 ps
CPU time 1.12 seconds
Started Mar 26 12:25:34 PM PDT 24
Finished Mar 26 12:25:35 PM PDT 24
Peak memory 198496 kb
Host smart-299ba62c-f06b-4746-a60e-f872723b1032
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2283323510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2283323510
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1026347277
Short name T914
Test name
Test status
Simulation time 106041771 ps
CPU time 1.49 seconds
Started Mar 26 12:25:32 PM PDT 24
Finished Mar 26 12:25:33 PM PDT 24
Peak memory 192200 kb
Host smart-e25a46da-8e7b-491c-b5c9-1309c1343301
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026347277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1026347277
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3023172262
Short name T920
Test name
Test status
Simulation time 77598646 ps
CPU time 1.21 seconds
Started Mar 26 12:25:39 PM PDT 24
Finished Mar 26 12:25:41 PM PDT 24
Peak memory 198408 kb
Host smart-66395cb0-9580-4ebb-95ed-6bd529c7c789
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3023172262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3023172262
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2405022941
Short name T852
Test name
Test status
Simulation time 519689031 ps
CPU time 0.93 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:26:42 PM PDT 24
Peak memory 192136 kb
Host smart-9b817246-bfef-443f-b923-a816b4e856e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405022941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2405022941
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2374433302
Short name T918
Test name
Test status
Simulation time 198403428 ps
CPU time 1 seconds
Started Mar 26 12:25:05 PM PDT 24
Finished Mar 26 12:25:07 PM PDT 24
Peak memory 192128 kb
Host smart-39ae7503-2bd0-4146-a2a9-5d3acfa70cc8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2374433302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2374433302
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2213561703
Short name T855
Test name
Test status
Simulation time 318569043 ps
CPU time 1.49 seconds
Started Mar 26 12:25:05 PM PDT 24
Finished Mar 26 12:25:07 PM PDT 24
Peak memory 192172 kb
Host smart-ad984dd5-272b-4c9f-976b-04b738fd0935
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213561703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2213561703
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.443356954
Short name T899
Test name
Test status
Simulation time 194777224 ps
CPU time 0.99 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:26:38 PM PDT 24
Peak memory 192148 kb
Host smart-b345c3e6-6e20-4fc1-afc7-4461b0464825
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=443356954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.443356954
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3930776867
Short name T921
Test name
Test status
Simulation time 346474607 ps
CPU time 1.34 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:26:23 PM PDT 24
Peak memory 192132 kb
Host smart-f107c315-0f9b-4412-9d10-4eaf795694ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930776867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3930776867
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1203222147
Short name T858
Test name
Test status
Simulation time 836679326 ps
CPU time 1.29 seconds
Started Mar 26 12:25:45 PM PDT 24
Finished Mar 26 12:25:46 PM PDT 24
Peak memory 191872 kb
Host smart-c14a5ce6-d8c6-41cf-b858-8f7537daef25
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1203222147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1203222147
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3605007948
Short name T875
Test name
Test status
Simulation time 41138022 ps
CPU time 1.05 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:50 PM PDT 24
Peak memory 198776 kb
Host smart-6d05c974-6174-41ec-86b2-7abb399c7b2c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605007948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3605007948
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2562259153
Short name T863
Test name
Test status
Simulation time 43445311 ps
CPU time 0.93 seconds
Started Mar 26 12:26:15 PM PDT 24
Finished Mar 26 12:26:16 PM PDT 24
Peak memory 198360 kb
Host smart-cd4cf1b1-7cd5-4eb3-9d7f-d8bbe747f01c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2562259153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2562259153
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4161935143
Short name T856
Test name
Test status
Simulation time 237783812 ps
CPU time 1.02 seconds
Started Mar 26 12:26:33 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 192100 kb
Host smart-98a39f62-a9d1-4333-bf4d-5b2c87a75b65
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161935143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4161935143
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2585899916
Short name T901
Test name
Test status
Simulation time 88754458 ps
CPU time 1.34 seconds
Started Mar 26 12:26:44 PM PDT 24
Finished Mar 26 12:26:46 PM PDT 24
Peak memory 192052 kb
Host smart-1f003736-94d5-417a-a4d4-c4a6fdc143ed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2585899916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2585899916
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2588609685
Short name T896
Test name
Test status
Simulation time 60757928 ps
CPU time 1.28 seconds
Started Mar 26 12:25:45 PM PDT 24
Finished Mar 26 12:25:46 PM PDT 24
Peak memory 196588 kb
Host smart-cecf76cd-96e7-4292-a92b-f8ff41d8a601
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588609685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2588609685
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1768361783
Short name T867
Test name
Test status
Simulation time 53264874 ps
CPU time 1.44 seconds
Started Mar 26 12:25:45 PM PDT 24
Finished Mar 26 12:25:47 PM PDT 24
Peak memory 198264 kb
Host smart-ee7f719d-2c49-4c11-8f0d-3bdee5653095
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1768361783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1768361783
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2859460733
Short name T892
Test name
Test status
Simulation time 205727798 ps
CPU time 1.42 seconds
Started Mar 26 12:26:13 PM PDT 24
Finished Mar 26 12:26:15 PM PDT 24
Peak memory 192104 kb
Host smart-fc06af49-37f8-4521-a869-6c4e6530f866
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859460733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2859460733
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.114098332
Short name T922
Test name
Test status
Simulation time 53360054 ps
CPU time 1.2 seconds
Started Mar 26 12:25:45 PM PDT 24
Finished Mar 26 12:25:46 PM PDT 24
Peak memory 191896 kb
Host smart-12b2836e-bb6f-4b16-976a-4344a129c6bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=114098332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.114098332
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3114585493
Short name T929
Test name
Test status
Simulation time 191959310 ps
CPU time 0.96 seconds
Started Mar 26 12:26:09 PM PDT 24
Finished Mar 26 12:26:10 PM PDT 24
Peak memory 192132 kb
Host smart-a7d0f27e-12a7-4cce-abfc-7c472fbe026f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114585493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3114585493
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2792392808
Short name T900
Test name
Test status
Simulation time 72281642 ps
CPU time 1.22 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:26:13 PM PDT 24
Peak memory 192252 kb
Host smart-e11f7c4f-5d88-4b46-a95c-71a642779176
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2792392808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2792392808
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.473719174
Short name T887
Test name
Test status
Simulation time 65434380 ps
CPU time 1.19 seconds
Started Mar 26 12:26:00 PM PDT 24
Finished Mar 26 12:26:01 PM PDT 24
Peak memory 192216 kb
Host smart-3158177e-0a00-4e02-84d9-aafd83517a0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473719174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.473719174
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2697755753
Short name T877
Test name
Test status
Simulation time 141375932 ps
CPU time 1.01 seconds
Started Mar 26 12:26:09 PM PDT 24
Finished Mar 26 12:26:10 PM PDT 24
Peak memory 192220 kb
Host smart-0a2afa21-d420-41a7-88d3-5dad3c58d4f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2697755753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2697755753
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.652302382
Short name T933
Test name
Test status
Simulation time 116575903 ps
CPU time 1.31 seconds
Started Mar 26 12:25:51 PM PDT 24
Finished Mar 26 12:25:52 PM PDT 24
Peak memory 192156 kb
Host smart-f59ada1a-26ca-4c29-b8bd-1b3ab41d15eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652302382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.652302382
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.575467398
Short name T910
Test name
Test status
Simulation time 215930510 ps
CPU time 0.92 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:45 PM PDT 24
Peak memory 191936 kb
Host smart-372024d3-1a0a-4927-afc7-ad3d25e6a34d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=575467398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.575467398
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439075250
Short name T861
Test name
Test status
Simulation time 51639522 ps
CPU time 0.95 seconds
Started Mar 26 12:25:53 PM PDT 24
Finished Mar 26 12:25:54 PM PDT 24
Peak memory 192132 kb
Host smart-858948ba-83fb-485a-90b4-f444a63e9ba6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439075250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2439075250
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4267733559
Short name T862
Test name
Test status
Simulation time 51133572 ps
CPU time 0.94 seconds
Started Mar 26 12:25:46 PM PDT 24
Finished Mar 26 12:25:47 PM PDT 24
Peak memory 192184 kb
Host smart-6036844c-cee1-4057-a144-47fdd3c0668c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4267733559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4267733559
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2886173185
Short name T874
Test name
Test status
Simulation time 44518608 ps
CPU time 0.93 seconds
Started Mar 26 12:25:46 PM PDT 24
Finished Mar 26 12:25:47 PM PDT 24
Peak memory 198372 kb
Host smart-0cf8645b-a220-40ba-a467-655bf59f5601
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886173185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2886173185
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3886132228
Short name T909
Test name
Test status
Simulation time 239743276 ps
CPU time 1.11 seconds
Started Mar 26 12:25:01 PM PDT 24
Finished Mar 26 12:25:03 PM PDT 24
Peak memory 192220 kb
Host smart-f16f2bc4-37dc-4b4c-a577-70eafd4503b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3886132228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3886132228
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1599846460
Short name T908
Test name
Test status
Simulation time 37607734 ps
CPU time 1.01 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:10 PM PDT 24
Peak memory 192124 kb
Host smart-edab0ae7-3a0e-48ec-94eb-b4bf1a4150c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599846460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1599846460
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2185380598
Short name T919
Test name
Test status
Simulation time 174381330 ps
CPU time 1.12 seconds
Started Mar 26 12:25:02 PM PDT 24
Finished Mar 26 12:25:03 PM PDT 24
Peak memory 192104 kb
Host smart-551cf6c6-7a78-4a62-b087-bc269edd76b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2185380598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2185380598
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3671966585
Short name T844
Test name
Test status
Simulation time 73841069 ps
CPU time 1.1 seconds
Started Mar 26 12:25:01 PM PDT 24
Finished Mar 26 12:25:02 PM PDT 24
Peak memory 192112 kb
Host smart-d5559afb-e294-4a0d-9c25-2ba7eb724fb6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671966585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3671966585
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1998154526
Short name T934
Test name
Test status
Simulation time 206563585 ps
CPU time 1 seconds
Started Mar 26 12:25:08 PM PDT 24
Finished Mar 26 12:25:10 PM PDT 24
Peak memory 198292 kb
Host smart-26343a2c-3130-40da-b751-efc81c83881b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1998154526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1998154526
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3855613749
Short name T943
Test name
Test status
Simulation time 40145940 ps
CPU time 1.19 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 192052 kb
Host smart-da43c016-0ae9-4704-b77b-c3e350f3ee65
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855613749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3855613749
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1482706832
Short name T878
Test name
Test status
Simulation time 174995209 ps
CPU time 1.29 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 192028 kb
Host smart-93d1bfc6-49b9-4843-a029-3ac974b77286
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1482706832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1482706832
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.80647793
Short name T869
Test name
Test status
Simulation time 65891508 ps
CPU time 0.9 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:45 PM PDT 24
Peak memory 198236 kb
Host smart-cb3e6a48-791d-4340-89f8-4055828ca68a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80647793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.80647793
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1179095901
Short name T940
Test name
Test status
Simulation time 167393226 ps
CPU time 0.95 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 192108 kb
Host smart-dbdfc46c-a802-436b-a68f-7032fc305381
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1179095901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1179095901
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.239502678
Short name T931
Test name
Test status
Simulation time 64395279 ps
CPU time 1.09 seconds
Started Mar 26 12:25:19 PM PDT 24
Finished Mar 26 12:25:20 PM PDT 24
Peak memory 192104 kb
Host smart-3b6ce96b-3669-4740-ab4c-105b7bab70c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239502678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.239502678
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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