Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[1]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[2]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[3]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[4]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[5]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[6]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[7]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[8]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[9]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[10]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[11]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[12]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[13]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[14]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[15]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[16]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[17]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[18]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[19]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[20]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[21]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[22]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[23]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[24]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[25]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[26]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[27]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[28]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[29]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[30]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[31]	11289017	1			T31	39638		T32	45766		T33	106685

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

214109805

1

T31

126841

T32

146451

T33

187370

auto[1]

147138739

1

T33

154021

T34

1314

T1

509

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95393091

1

T31

126841

T32

146451

T33

661699

auto[1]

265855453

1

T33

275222

T34

1463

T1

1140

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2530342	1			T31	39638		T32	45766		T33	15318
all_values[0]	auto[0]	auto[1]	4154462	1			T33	43189		T34	18		T1	28
all_values[0]	auto[1]	auto[0]	448227	1			T33	5457		T34	36		T1	4
all_values[0]	auto[1]	auto[1]	4155986	1			T33	42721		T34	22		T1	13
all_values[1]	auto[0]	auto[0]	2532897	1			T31	39638		T32	45766		T33	15622
all_values[1]	auto[0]	auto[1]	4146404	1			T33	43484		T34	30		T1	24
all_values[1]	auto[1]	auto[0]	451990	1			T33	5091		T34	16		T1	4
all_values[1]	auto[1]	auto[1]	4157726	1			T33	42488		T34	10		T1	7
all_values[2]	auto[0]	auto[0]	2528056	1			T31	39638		T32	45766		T33	15448
all_values[2]	auto[0]	auto[1]	4166613	1			T33	43322		T34	29		T1	27
all_values[2]	auto[1]	auto[0]	449608	1			T33	5050		T34	8		T1	8
all_values[2]	auto[1]	auto[1]	4144740	1			T33	42865		T34	14		T1	17
all_values[3]	auto[0]	auto[0]	2536022	1			T31	39638		T32	45766		T33	15068
all_values[3]	auto[0]	auto[1]	4156840	1			T33	43584		T34	41		T1	42
all_values[3]	auto[1]	auto[0]	449654	1			T33	5876		T34	16		T1	5
all_values[3]	auto[1]	auto[1]	4146501	1			T33	42157		T34	10		T1	7
all_values[4]	auto[0]	auto[0]	2525870	1			T31	39638		T32	45766		T33	16431
all_values[4]	auto[0]	auto[1]	4166306	1			T33	44108		T34	26		T1	14
all_values[4]	auto[1]	auto[0]	452837	1			T33	5390		T34	11		T1	3
all_values[4]	auto[1]	auto[1]	4144004	1			T33	40756		T34	28		T1	16
all_values[5]	auto[0]	auto[0]	2524141	1			T31	39638		T32	45766		T33	14847
all_values[5]	auto[0]	auto[1]	4164555	1			T33	42029		T34	18		T1	27
all_values[5]	auto[1]	auto[0]	453860	1			T33	5534		T34	24		T1	8
all_values[5]	auto[1]	auto[1]	4146461	1			T33	44275		T34	31		T1	9
all_values[6]	auto[0]	auto[0]	2528038	1			T31	39638		T32	45766		T33	15438
all_values[6]	auto[0]	auto[1]	4180077	1			T33	42336		T34	16		T1	22
all_values[6]	auto[1]	auto[0]	442742	1			T33	4971		T34	26		T1	6
all_values[6]	auto[1]	auto[1]	4138160	1			T33	43940		T34	29		T1	13
all_values[7]	auto[0]	auto[0]	2535112	1			T31	39638		T32	45766		T33	15313
all_values[7]	auto[0]	auto[1]	4151521	1			T33	43899		T34	16		T1	22
all_values[7]	auto[1]	auto[0]	458392	1			T33	5519		T34	13		T1	11
all_values[7]	auto[1]	auto[1]	4143992	1			T33	41954		T34	26		T1	6
all_values[8]	auto[0]	auto[0]	2536839	1			T31	39638		T32	45766		T33	15108
all_values[8]	auto[0]	auto[1]	4149644	1			T33	43182		T34	42		T1	18
all_values[8]	auto[1]	auto[0]	448269	1			T33	5280		T34	19		T1	22
all_values[8]	auto[1]	auto[1]	4154265	1			T33	43115		T34	5		T1	8
all_values[9]	auto[0]	auto[0]	2534556	1			T31	39638		T32	45766		T33	15092
all_values[9]	auto[0]	auto[1]	4169045	1			T33	42832		T34	35		T1	22
all_values[9]	auto[1]	auto[0]	448651	1			T33	5995		T34	18		T1	13
all_values[9]	auto[1]	auto[1]	4136765	1			T33	42766		T34	21		T1	11
all_values[10]	auto[0]	auto[0]	2526426	1			T31	39638		T32	45766		T33	15144
all_values[10]	auto[0]	auto[1]	4149571	1			T33	44073		T34	22		T1	35
all_values[10]	auto[1]	auto[0]	450330	1			T33	5231		T34	21		T1	9
all_values[10]	auto[1]	auto[1]	4162690	1			T33	42237		T34	34		T1	9
all_values[11]	auto[0]	auto[0]	2530603	1			T31	39638		T32	45766		T33	15350
all_values[11]	auto[0]	auto[1]	4185378	1			T33	40595		T34	37		T1	27
all_values[11]	auto[1]	auto[0]	443532	1			T33	5881		T34	14		T1	5
all_values[11]	auto[1]	auto[1]	4129504	1			T33	44859		T34	15		T1	20
all_values[12]	auto[0]	auto[0]	2532545	1			T31	39638		T32	45766		T33	15422
all_values[12]	auto[0]	auto[1]	4166504	1			T33	44769		T34	35		T1	23
all_values[12]	auto[1]	auto[0]	454561	1			T33	5041		T34	9		T1	1
all_values[12]	auto[1]	auto[1]	4135407	1			T33	41453		T34	23		T1	5
all_values[13]	auto[0]	auto[0]	2528228	1			T31	39638		T32	45766		T33	15437
all_values[13]	auto[0]	auto[1]	4150325	1			T33	43942		T34	37		T1	31
all_values[13]	auto[1]	auto[0]	446293	1			T33	4958		T34	27		T1	5
all_values[13]	auto[1]	auto[1]	4164171	1			T33	42348		T34	7		T12	1098
all_values[14]	auto[0]	auto[0]	2532523	1			T31	39638		T32	45766		T33	15663
all_values[14]	auto[0]	auto[1]	4139438	1			T33	44103		T34	24		T1	22
all_values[14]	auto[1]	auto[0]	455749	1			T33	5246		T34	24		T1	10
all_values[14]	auto[1]	auto[1]	4161307	1			T33	41673		T34	24		T1	14
all_values[15]	auto[0]	auto[0]	2531907	1			T31	39638		T32	45766		T33	14888
all_values[15]	auto[0]	auto[1]	4171330	1			T33	43815		T34	23		T1	34
all_values[15]	auto[1]	auto[0]	447398	1			T33	5441		T34	37		T1	8
all_values[15]	auto[1]	auto[1]	4138382	1			T33	42541		T34	20		T1	4
all_values[16]	auto[0]	auto[0]	2528656	1			T31	39638		T32	45766		T33	15447
all_values[16]	auto[0]	auto[1]	4172028	1			T33	43008		T34	26		T1	36
all_values[16]	auto[1]	auto[0]	450033	1			T33	4617		T34	29		T12	141
all_values[16]	auto[1]	auto[1]	4138300	1			T33	43613		T34	13		T12	1811
all_values[17]	auto[0]	auto[0]	2526757	1			T31	39638		T32	45766		T33	15173
all_values[17]	auto[0]	auto[1]	4184342	1			T33	43891		T34	18		T1	17
all_values[17]	auto[1]	auto[0]	448104	1			T33	5006		T34	36		T1	12
all_values[17]	auto[1]	auto[1]	4129814	1			T33	42615		T34	18		T12	1317
all_values[18]	auto[0]	auto[0]	2533498	1			T31	39638		T32	45766		T33	15369
all_values[18]	auto[0]	auto[1]	4143922	1			T33	43371		T34	41		T1	22
all_values[18]	auto[1]	auto[0]	449376	1			T33	5529		T34	16		T1	11
all_values[18]	auto[1]	auto[1]	4162221	1			T33	42416		T34	17		T1	13
all_values[19]	auto[0]	auto[0]	2529692	1			T31	39638		T32	45766		T33	14853
all_values[19]	auto[0]	auto[1]	4157557	1			T33	42793		T34	29		T1	26
all_values[19]	auto[1]	auto[0]	447078	1			T33	5153		T34	26		T1	5
all_values[19]	auto[1]	auto[1]	4154690	1			T33	43886		T34	14		T1	6
all_values[20]	auto[0]	auto[0]	2532705	1			T31	39638		T32	45766		T33	15341
all_values[20]	auto[0]	auto[1]	4162155	1			T33	43804		T34	28		T1	26
all_values[20]	auto[1]	auto[0]	456552	1			T33	5519		T34	30		T1	7
all_values[20]	auto[1]	auto[1]	4137605	1			T33	42021		T34	25		T1	23
all_values[21]	auto[0]	auto[0]	2526411	1			T31	39638		T32	45766		T33	14837
all_values[21]	auto[0]	auto[1]	4196907	1			T33	42706		T34	24		T1	32
all_values[21]	auto[1]	auto[0]	442347	1			T33	4884		T34	39		T12	122
all_values[21]	auto[1]	auto[1]	4123352	1			T33	44258		T34	12		T1	6
all_values[22]	auto[0]	auto[0]	2534099	1			T31	39638		T32	45766		T33	15857
all_values[22]	auto[0]	auto[1]	4164050	1			T33	40997		T34	17		T1	21
all_values[22]	auto[1]	auto[0]	450546	1			T33	5596		T34	32		T1	2
all_values[22]	auto[1]	auto[1]	4140322	1			T33	44235		T34	14		T1	5
all_values[23]	auto[0]	auto[0]	2524653	1			T31	39638		T32	45766		T33	15120
all_values[23]	auto[0]	auto[1]	4157195	1			T33	42950		T34	41		T1	25
all_values[23]	auto[1]	auto[0]	449639	1			T33	5323		T34	12		T1	4
all_values[23]	auto[1]	auto[1]	4157530	1			T33	43292		T34	10		T1	15
all_values[24]	auto[0]	auto[0]	2534477	1			T31	39638		T32	45766		T33	15868
all_values[24]	auto[0]	auto[1]	4139387	1			T33	44155		T34	21		T1	22
all_values[24]	auto[1]	auto[0]	451983	1			T33	5380		T34	34		T1	8
all_values[24]	auto[1]	auto[1]	4163170	1			T33	41282		T34	17		T1	16
all_values[25]	auto[0]	auto[0]	2539315	1			T31	39638		T32	45766		T33	15680
all_values[25]	auto[0]	auto[1]	4173003	1			T33	42925		T34	47		T1	23
all_values[25]	auto[1]	auto[0]	445736	1			T33	5099		T34	7		T1	3
all_values[25]	auto[1]	auto[1]	4130963	1			T33	42981		T34	13		T1	20
all_values[26]	auto[0]	auto[0]	2525668	1			T31	39638		T32	45766		T33	15162
all_values[26]	auto[0]	auto[1]	4159593	1			T33	42381		T34	18		T1	14
all_values[26]	auto[1]	auto[0]	449576	1			T33	5195		T34	27		T1	8
all_values[26]	auto[1]	auto[1]	4154180	1			T33	43947		T34	23		T1	5
all_values[27]	auto[0]	auto[0]	2532214	1			T31	39638		T32	45766		T33	15612
all_values[27]	auto[0]	auto[1]	4152187	1			T33	42148		T34	12		T1	39
all_values[27]	auto[1]	auto[0]	453815	1			T33	5450		T34	28		T12	128
all_values[27]	auto[1]	auto[1]	4150801	1			T33	43475		T34	35		T12	1347
all_values[28]	auto[0]	auto[0]	2527462	1			T31	39638		T32	45766		T33	15714
all_values[28]	auto[0]	auto[1]	4143311	1			T33	43161		T34	37		T1	30
all_values[28]	auto[1]	auto[0]	456339	1			T33	5865		T34	13		T1	4
all_values[28]	auto[1]	auto[1]	4161905	1			T33	41945		T34	19		T1	1
all_values[29]	auto[0]	auto[0]	2535685	1			T31	39638		T32	45766		T33	15710
all_values[29]	auto[0]	auto[1]	4127749	1			T33	43570		T34	21		T1	38
all_values[29]	auto[1]	auto[0]	465390	1			T33	5108		T34	26		T1	4
all_values[29]	auto[1]	auto[1]	4160193	1			T33	42297		T34	5		T1	7
all_values[30]	auto[0]	auto[0]	2530582	1			T31	39638		T32	45766		T33	15138
all_values[30]	auto[0]	auto[1]	4145568	1			T33	43194		T34	16		T1	29
all_values[30]	auto[1]	auto[0]	444087	1			T33	4737		T34	20		T1	7
all_values[30]	auto[1]	auto[1]	4168780	1			T33	43616		T34	26		T1	12
all_values[31]	auto[0]	auto[0]	2531952	1			T31	39638		T32	45766		T33	15615
all_values[31]	auto[0]	auto[1]	4174907	1			T33	43303		T34	20		T1	20
all_values[31]	auto[1]	auto[0]	442466	1			T33	5192		T34	22		T1	10
all_values[31]	auto[1]	auto[1]	4139692	1			T33	42575		T34	18		T1	14