Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3296679	1			T31	57		T32	92		T33	38447
all_pins[1]	3296679	1			T31	57		T32	92		T33	38447
all_pins[2]	3296679	1			T31	57		T32	92		T33	38447
all_pins[3]	3296679	1			T31	57		T32	92		T33	38447
all_pins[4]	3296679	1			T31	57		T32	92		T33	38447
all_pins[5]	3296679	1			T31	57		T32	92		T33	38447
all_pins[6]	3296679	1			T31	57		T32	92		T33	38447
all_pins[7]	3296679	1			T31	57		T32	92		T33	38447
all_pins[8]	3296679	1			T31	57		T32	92		T33	38447
all_pins[9]	3296679	1			T31	57		T32	92		T33	38447
all_pins[10]	3296679	1			T31	57		T32	92		T33	38447
all_pins[11]	3296679	1			T31	57		T32	92		T33	38447
all_pins[12]	3296679	1			T31	57		T32	92		T33	38447
all_pins[13]	3296679	1			T31	57		T32	92		T33	38447
all_pins[14]	3296679	1			T31	57		T32	92		T33	38447
all_pins[15]	3296679	1			T31	57		T32	92		T33	38447
all_pins[16]	3296679	1			T31	57		T32	92		T33	38447
all_pins[17]	3296679	1			T31	57		T32	92		T33	38447
all_pins[18]	3296679	1			T31	57		T32	92		T33	38447
all_pins[19]	3296679	1			T31	57		T32	92		T33	38447
all_pins[20]	3296679	1			T31	57		T32	92		T33	38447
all_pins[21]	3296679	1			T31	57		T32	92		T33	38447
all_pins[22]	3296679	1			T31	57		T32	92		T33	38447
all_pins[23]	3296679	1			T31	57		T32	92		T33	38447
all_pins[24]	3296679	1			T31	57		T32	92		T33	38447
all_pins[25]	3296679	1			T31	57		T32	92		T33	38447
all_pins[26]	3296679	1			T31	57		T32	92		T33	38447
all_pins[27]	3296679	1			T31	57		T32	92		T33	38447
all_pins[28]	3296679	1			T31	57		T32	92		T33	38447
all_pins[29]	3296679	1			T31	57		T32	92		T33	38447
all_pins[30]	3296679	1			T31	57		T32	92		T33	38447
all_pins[31]	3296679	1			T31	57		T32	92		T33	38447

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	65578658	1			T31	921		T32	1533		T33	767563
values[0x1]	39915070	1			T31	903		T32	1411		T33	462741
transitions[0x0=>0x1]	23932634	1			T31	455		T32	718		T33	277897
transitions[0x1=>0x0]	23932483	1			T31	455		T32	717		T33	277896

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2049784	1			T31	33		T32	47		T33	24344
all_pins[0]	values[0x1]	1246895	1			T31	24		T32	45		T33	14103
all_pins[0]	transitions[0x0=>0x1]	772956	1			T31	13		T32	21		T33	8829
all_pins[0]	transitions[0x1=>0x0]	770737	1			T31	19		T32	23		T33	8797
all_pins[1]	values[0x0]	2050898	1			T31	27		T32	40		T33	24316
all_pins[1]	values[0x1]	1245781	1			T31	30		T32	52		T33	14131
all_pins[1]	transitions[0x0=>0x1]	744455	1			T31	16		T32	22		T33	8526
all_pins[1]	transitions[0x1=>0x0]	745569	1			T31	10		T32	15		T33	8498
all_pins[2]	values[0x0]	2049154	1			T31	24		T32	46		T33	24292
all_pins[2]	values[0x1]	1247525	1			T31	33		T32	46		T33	14155
all_pins[2]	transitions[0x0=>0x1]	747509	1			T31	19		T32	19		T33	8516
all_pins[2]	transitions[0x1=>0x0]	745765	1			T31	16		T32	25		T33	8492
all_pins[3]	values[0x0]	2054019	1			T31	30		T32	51		T33	24086
all_pins[3]	values[0x1]	1242660	1			T31	27		T32	41		T33	14361
all_pins[3]	transitions[0x0=>0x1]	744129	1			T31	12		T32	17		T33	8451
all_pins[3]	transitions[0x1=>0x0]	748994	1			T31	18		T32	22		T33	8245
all_pins[4]	values[0x0]	2051627	1			T31	28		T32	48		T33	24003
all_pins[4]	values[0x1]	1245052	1			T31	29		T32	44		T33	14444
all_pins[4]	transitions[0x0=>0x1]	746195	1			T31	16		T32	26		T33	8651
all_pins[4]	transitions[0x1=>0x0]	743803	1			T31	14		T32	23		T33	8568
all_pins[5]	values[0x0]	2047755	1			T31	27		T32	44		T33	23421
all_pins[5]	values[0x1]	1248924	1			T31	30		T32	48		T33	15026
all_pins[5]	transitions[0x0=>0x1]	749535	1			T31	14		T32	25		T33	8973
all_pins[5]	transitions[0x1=>0x0]	745663	1			T31	13		T32	21		T33	8391
all_pins[6]	values[0x0]	2047213	1			T31	31		T32	48		T33	23895
all_pins[6]	values[0x1]	1249466	1			T31	26		T32	44		T33	14552
all_pins[6]	transitions[0x0=>0x1]	747917	1			T31	11		T32	24		T33	8292
all_pins[6]	transitions[0x1=>0x0]	747375	1			T31	15		T32	28		T33	8766
all_pins[7]	values[0x0]	2052744	1			T31	28		T32	59		T33	23942
all_pins[7]	values[0x1]	1243935	1			T31	29		T32	33		T33	14505
all_pins[7]	transitions[0x0=>0x1]	744324	1			T31	16		T32	16		T33	8822
all_pins[7]	transitions[0x1=>0x0]	749855	1			T31	13		T32	27		T33	8869
all_pins[8]	values[0x0]	2049595	1			T31	28		T32	61		T33	23623
all_pins[8]	values[0x1]	1247084	1			T31	29		T32	31		T33	14824
all_pins[8]	transitions[0x0=>0x1]	747867	1			T31	13		T32	21		T33	8824
all_pins[8]	transitions[0x1=>0x0]	744718	1			T31	13		T32	23		T33	8505
all_pins[9]	values[0x0]	2051773	1			T31	31		T32	38		T33	23590
all_pins[9]	values[0x1]	1244906	1			T31	26		T32	54		T33	14857
all_pins[9]	transitions[0x0=>0x1]	746081	1			T31	13		T32	37		T33	8818
all_pins[9]	transitions[0x1=>0x0]	748259	1			T31	16		T32	14		T33	8785
all_pins[10]	values[0x0]	2047087	1			T31	31		T32	45		T33	23719
all_pins[10]	values[0x1]	1249592	1			T31	26		T32	47		T33	14728
all_pins[10]	transitions[0x0=>0x1]	747447	1			T31	15		T32	24		T33	9033
all_pins[10]	transitions[0x1=>0x0]	742761	1			T31	15		T32	31		T33	9162
all_pins[11]	values[0x0]	2045100	1			T31	22		T32	52		T33	24065
all_pins[11]	values[0x1]	1251579	1			T31	35		T32	40		T33	14382
all_pins[11]	transitions[0x0=>0x1]	749211	1			T31	17		T32	21		T33	8652
all_pins[11]	transitions[0x1=>0x0]	747224	1			T31	8		T32	28		T33	8998
all_pins[12]	values[0x0]	2049568	1			T31	29		T32	46		T33	24059
all_pins[12]	values[0x1]	1247111	1			T31	28		T32	46		T33	14388
all_pins[12]	transitions[0x0=>0x1]	747762	1			T31	11		T32	25		T33	8842
all_pins[12]	transitions[0x1=>0x0]	752230	1			T31	18		T32	19		T33	8836
all_pins[13]	values[0x0]	2052464	1			T31	30		T32	54		T33	24373
all_pins[13]	values[0x1]	1244215	1			T31	27		T32	38		T33	14074
all_pins[13]	transitions[0x0=>0x1]	744783	1			T31	14		T32	18		T33	8565
all_pins[13]	transitions[0x1=>0x0]	747679	1			T31	15		T32	26		T33	8879
all_pins[14]	values[0x0]	2047368	1			T31	31		T32	50		T33	24487
all_pins[14]	values[0x1]	1249311	1			T31	26		T32	42		T33	13960
all_pins[14]	transitions[0x0=>0x1]	750251	1			T31	13		T32	22		T33	8411
all_pins[14]	transitions[0x1=>0x0]	745155	1			T31	14		T32	18		T33	8525
all_pins[15]	values[0x0]	2051414	1			T31	30		T32	45		T33	24000
all_pins[15]	values[0x1]	1245265	1			T31	27		T32	47		T33	14447
all_pins[15]	transitions[0x0=>0x1]	746572	1			T31	11		T32	22		T33	8841
all_pins[15]	transitions[0x1=>0x0]	750618	1			T31	10		T32	17		T33	8354
all_pins[16]	values[0x0]	2051144	1			T31	29		T32	49		T33	23946
all_pins[16]	values[0x1]	1245535	1			T31	28		T32	43		T33	14501
all_pins[16]	transitions[0x0=>0x1]	745689	1			T31	13		T32	21		T33	8525
all_pins[16]	transitions[0x1=>0x0]	745419	1			T31	12		T32	25		T33	8471
all_pins[17]	values[0x0]	2047940	1			T31	26		T32	50		T33	23948
all_pins[17]	values[0x1]	1248739	1			T31	31		T32	42		T33	14499
all_pins[17]	transitions[0x0=>0x1]	747503	1			T31	17		T32	23		T33	8724
all_pins[17]	transitions[0x1=>0x0]	744299	1			T31	14		T32	24		T33	8726
all_pins[18]	values[0x0]	2047157	1			T31	25		T32	49		T33	23671
all_pins[18]	values[0x1]	1249522	1			T31	32		T32	43		T33	14776
all_pins[18]	transitions[0x0=>0x1]	748051	1			T31	15		T32	19		T33	8802
all_pins[18]	transitions[0x1=>0x0]	747268	1			T31	14		T32	18		T33	8525
all_pins[19]	values[0x0]	2050840	1			T31	31		T32	52		T33	23642
all_pins[19]	values[0x1]	1245839	1			T31	26		T32	40		T33	14805
all_pins[19]	transitions[0x0=>0x1]	745721	1			T31	13		T32	21		T33	8834
all_pins[19]	transitions[0x1=>0x0]	749404	1			T31	19		T32	24		T33	8805
all_pins[20]	values[0x0]	2052112	1			T31	24		T32	46		T33	23888
all_pins[20]	values[0x1]	1244567	1			T31	33		T32	46		T33	14559
all_pins[20]	transitions[0x0=>0x1]	746345	1			T31	17		T32	29		T33	8615
all_pins[20]	transitions[0x1=>0x0]	747617	1			T31	10		T32	23		T33	8861
all_pins[21]	values[0x0]	2049725	1			T31	38		T32	42		T33	23584
all_pins[21]	values[0x1]	1246954	1			T31	19		T32	50		T33	14863
all_pins[21]	transitions[0x0=>0x1]	748637	1			T31	10		T32	21		T33	9093
all_pins[21]	transitions[0x1=>0x0]	746250	1			T31	24		T32	17		T33	8789
all_pins[22]	values[0x0]	2051088	1			T31	25		T32	43		T33	24012
all_pins[22]	values[0x1]	1245591	1			T31	32		T32	49		T33	14435
all_pins[22]	transitions[0x0=>0x1]	746762	1			T31	20		T32	21		T33	8331
all_pins[22]	transitions[0x1=>0x0]	748125	1			T31	7		T32	22		T33	8759
all_pins[23]	values[0x0]	2046932	1			T31	25		T32	45		T33	23785
all_pins[23]	values[0x1]	1249747	1			T31	32		T32	47		T33	14662
all_pins[23]	transitions[0x0=>0x1]	750133	1			T31	10		T32	23		T33	8775
all_pins[23]	transitions[0x1=>0x0]	745977	1			T31	10		T32	25		T33	8548
all_pins[24]	values[0x0]	2044656	1			T31	32		T32	42		T33	24494
all_pins[24]	values[0x1]	1252023	1			T31	25		T32	50		T33	13953
all_pins[24]	transitions[0x0=>0x1]	750064	1			T31	12		T32	21		T33	8254
all_pins[24]	transitions[0x1=>0x0]	747788	1			T31	19		T32	18		T33	8963
all_pins[25]	values[0x0]	2048078	1			T31	30		T32	47		T33	23864
all_pins[25]	values[0x1]	1248601	1			T31	27		T32	45		T33	14583
all_pins[25]	transitions[0x0=>0x1]	745284	1			T31	13		T32	23		T33	9038
all_pins[25]	transitions[0x1=>0x0]	748706	1			T31	11		T32	28		T33	8408
all_pins[26]	values[0x0]	2049010	1			T31	31		T32	51		T33	23577
all_pins[26]	values[0x1]	1247669	1			T31	26		T32	41		T33	14870
all_pins[26]	transitions[0x0=>0x1]	747772	1			T31	13		T32	16		T33	8902
all_pins[26]	transitions[0x1=>0x0]	748704	1			T31	14		T32	20		T33	8615
all_pins[27]	values[0x0]	2049561	1			T31	26		T32	53		T33	24122
all_pins[27]	values[0x1]	1247118	1			T31	31		T32	39		T33	14325
all_pins[27]	transitions[0x0=>0x1]	746437	1			T31	17		T32	22		T33	8455
all_pins[27]	transitions[0x1=>0x0]	746988	1			T31	12		T32	24		T33	9000
all_pins[28]	values[0x0]	2050103	1			T31	34		T32	39		T33	24331
all_pins[28]	values[0x1]	1246576	1			T31	23		T32	53		T33	14116
all_pins[28]	transitions[0x0=>0x1]	746913	1			T31	12		T32	29		T33	8693
all_pins[28]	transitions[0x1=>0x0]	747455	1			T31	20		T32	15		T33	8902
all_pins[29]	values[0x0]	2047490	1			T31	24		T32	52		T33	24329
all_pins[29]	values[0x1]	1249189	1			T31	33		T32	40		T33	14118
all_pins[29]	transitions[0x0=>0x1]	747387	1			T31	21		T32	13		T33	8491
all_pins[29]	transitions[0x1=>0x0]	744774	1			T31	11		T32	26		T33	8489
all_pins[30]	values[0x0]	2043407	1			T31	34		T32	55		T33	23780
all_pins[30]	values[0x1]	1253272	1			T31	23		T32	37		T33	14667
all_pins[30]	transitions[0x0=>0x1]	750258	1			T31	7		T32	23		T33	8945
all_pins[30]	transitions[0x1=>0x0]	746175	1			T31	17		T32	26		T33	8396
all_pins[31]	values[0x0]	2051852	1			T31	27		T32	44		T33	24375
all_pins[31]	values[0x1]	1244827	1			T31	30		T32	48		T33	14072
all_pins[31]	transitions[0x0=>0x1]	742684	1			T31	21		T32	33		T33	8374
all_pins[31]	transitions[0x1=>0x0]	751129	1			T31	14		T32	22		T33	8969