Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[1]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[2]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[3]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[4]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[5]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[6]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[7]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[8]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[9]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[10]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[11]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[12]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[13]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[14]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[15]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[16]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[17]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[18]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[19]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[20]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[21]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[22]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[23]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[24]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[25]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[26]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[27]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[28]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[29]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[30]	11289017	1			T31	39638		T32	45766		T33	106685
all_values[31]	11289017	1			T31	39638		T32	45766		T33	106685

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

214109805

1

T31

126841

T32

146451

T33

187370

auto[1]

147138739

1

T33

154021

T34

1314

T1

509

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95393091

1

T31

126841

T32

146451

T33

661699

auto[1]

265855453

1

T33

275222

T34

1463

T1

1140

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

357485335

1

T31

126841

T32

146451

T33

336879

auto[1]

3763209

1

T33

45128

T34

144

T1

123

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2530342	1			T31	39638		T32	45766		T33	15318
all_values[0]	auto[0]	auto[0]	auto[1]	4095354	1			T33	42484		T34	17		T1	23
all_values[0]	auto[0]	auto[1]	auto[0]	448227	1			T33	5457		T34	36		T1	4
all_values[0]	auto[0]	auto[1]	auto[1]	4097272	1			T33	42029		T34	19		T1	13
all_values[0]	auto[1]	auto[0]	auto[1]	59108	1			T33	705		T34	1		T1	5
all_values[0]	auto[1]	auto[1]	auto[1]	58714	1			T33	692		T34	3		T2	886
all_values[1]	auto[0]	auto[0]	auto[0]	2532897	1			T31	39638		T32	45766		T33	15622
all_values[1]	auto[0]	auto[0]	auto[1]	4087371	1			T33	42823		T34	29		T1	21
all_values[1]	auto[0]	auto[1]	auto[0]	451990	1			T33	5091		T34	16		T1	4
all_values[1]	auto[0]	auto[1]	auto[1]	4099230	1			T33	41758		T34	10		T1	6
all_values[1]	auto[1]	auto[0]	auto[1]	59033	1			T33	661		T34	1		T1	3
all_values[1]	auto[1]	auto[1]	auto[1]	58496	1			T33	730		T1	1		T2	859
all_values[2]	auto[0]	auto[0]	auto[0]	2528056	1			T31	39638		T32	45766		T33	15448
all_values[2]	auto[0]	auto[0]	auto[1]	4107316	1			T33	42622		T34	25		T1	24
all_values[2]	auto[0]	auto[1]	auto[0]	449608	1			T33	5050		T34	8		T1	8
all_values[2]	auto[0]	auto[1]	auto[1]	4086307	1			T33	42228		T34	14		T1	16
all_values[2]	auto[1]	auto[0]	auto[1]	59297	1			T33	700		T34	4		T1	3
all_values[2]	auto[1]	auto[1]	auto[1]	58433	1			T33	637		T1	1		T2	867
all_values[3]	auto[0]	auto[0]	auto[0]	2536022	1			T31	39638		T32	45766		T33	15068
all_values[3]	auto[0]	auto[0]	auto[1]	4097960	1			T33	42860		T34	36		T1	39
all_values[3]	auto[0]	auto[1]	auto[0]	449654	1			T33	5876		T34	16		T1	5
all_values[3]	auto[0]	auto[1]	auto[1]	4087974	1			T33	41463		T34	9		T1	7
all_values[3]	auto[1]	auto[0]	auto[1]	58880	1			T33	724		T34	5		T1	3
all_values[3]	auto[1]	auto[1]	auto[1]	58527	1			T33	694		T34	1		T2	841
all_values[4]	auto[0]	auto[0]	auto[0]	2525870	1			T31	39638		T32	45766		T33	16431
all_values[4]	auto[0]	auto[0]	auto[1]	4107654	1			T33	43397		T34	24		T1	10
all_values[4]	auto[0]	auto[1]	auto[0]	452837	1			T33	5390		T34	11		T1	3
all_values[4]	auto[0]	auto[1]	auto[1]	4085117	1			T33	40028		T34	24		T1	14
all_values[4]	auto[1]	auto[0]	auto[1]	58652	1			T33	711		T34	2		T1	4
all_values[4]	auto[1]	auto[1]	auto[1]	58887	1			T33	728		T34	4		T1	2
all_values[5]	auto[0]	auto[0]	auto[0]	2524141	1			T31	39638		T32	45766		T33	14847
all_values[5]	auto[0]	auto[0]	auto[1]	4105931	1			T33	41316		T34	16		T1	23
all_values[5]	auto[0]	auto[1]	auto[0]	453860	1			T33	5534		T34	24		T1	8
all_values[5]	auto[0]	auto[1]	auto[1]	4087820	1			T33	43576		T34	29		T1	9
all_values[5]	auto[1]	auto[0]	auto[1]	58624	1			T33	713		T34	2		T1	4
all_values[5]	auto[1]	auto[1]	auto[1]	58641	1			T33	699		T34	2		T2	874
all_values[6]	auto[0]	auto[0]	auto[0]	2528038	1			T31	39638		T32	45766		T33	15438
all_values[6]	auto[0]	auto[0]	auto[1]	4120905	1			T33	41624		T34	13		T1	20
all_values[6]	auto[0]	auto[1]	auto[0]	442742	1			T33	4971		T34	26		T1	6
all_values[6]	auto[0]	auto[1]	auto[1]	4079448	1			T33	43223		T34	27		T1	13
all_values[6]	auto[1]	auto[0]	auto[1]	59172	1			T33	712		T34	3		T1	2
all_values[6]	auto[1]	auto[1]	auto[1]	58712	1			T33	717		T34	2		T2	873
all_values[7]	auto[0]	auto[0]	auto[0]	2535112	1			T31	39638		T32	45766		T33	15313
all_values[7]	auto[0]	auto[0]	auto[1]	4092294	1			T33	43189		T34	14		T1	19
all_values[7]	auto[0]	auto[1]	auto[0]	458392	1			T33	5519		T34	13		T1	11
all_values[7]	auto[0]	auto[1]	auto[1]	4085424	1			T33	41271		T34	24		T1	6
all_values[7]	auto[1]	auto[0]	auto[1]	59227	1			T33	710		T34	2		T1	3
all_values[7]	auto[1]	auto[1]	auto[1]	58568	1			T33	683		T34	2		T2	909
all_values[8]	auto[0]	auto[0]	auto[0]	2536839	1			T31	39638		T32	45766		T33	15108
all_values[8]	auto[0]	auto[0]	auto[1]	4090807	1			T33	42450		T34	37		T1	15
all_values[8]	auto[0]	auto[1]	auto[0]	448269	1			T33	5280		T34	19		T1	22
all_values[8]	auto[0]	auto[1]	auto[1]	4095603	1			T33	42397		T34	4		T1	7
all_values[8]	auto[1]	auto[0]	auto[1]	58837	1			T33	732		T34	5		T1	3
all_values[8]	auto[1]	auto[1]	auto[1]	58662	1			T33	718		T34	1		T1	1
all_values[9]	auto[0]	auto[0]	auto[0]	2534556	1			T31	39638		T32	45766		T33	15092
all_values[9]	auto[0]	auto[0]	auto[1]	4110228	1			T33	42132		T34	32		T1	18
all_values[9]	auto[0]	auto[1]	auto[0]	448651	1			T33	5995		T34	18		T1	13
all_values[9]	auto[0]	auto[1]	auto[1]	4078517	1			T33	42066		T34	20		T1	9
all_values[9]	auto[1]	auto[0]	auto[1]	58817	1			T33	700		T34	3		T1	4
all_values[9]	auto[1]	auto[1]	auto[1]	58248	1			T33	700		T34	1		T1	2
all_values[10]	auto[0]	auto[0]	auto[0]	2526426	1			T31	39638		T32	45766		T33	15144
all_values[10]	auto[0]	auto[0]	auto[1]	4090998	1			T33	43380		T34	20		T1	33
all_values[10]	auto[0]	auto[1]	auto[0]	450330	1			T33	5231		T34	21		T1	9
all_values[10]	auto[0]	auto[1]	auto[1]	4103361	1			T33	41552		T34	32		T1	9
all_values[10]	auto[1]	auto[0]	auto[1]	58573	1			T33	693		T34	2		T1	2
all_values[10]	auto[1]	auto[1]	auto[1]	59329	1			T33	685		T34	2		T2	890
all_values[11]	auto[0]	auto[0]	auto[0]	2530603	1			T31	39638		T32	45766		T33	15350
all_values[11]	auto[0]	auto[0]	auto[1]	4126737	1			T33	39896		T34	33		T1	25
all_values[11]	auto[0]	auto[1]	auto[0]	443532	1			T33	5881		T34	14		T1	5
all_values[11]	auto[0]	auto[1]	auto[1]	4071039	1			T33	44137		T34	14		T1	17
all_values[11]	auto[1]	auto[0]	auto[1]	58641	1			T33	699		T34	4		T1	2
all_values[11]	auto[1]	auto[1]	auto[1]	58465	1			T33	722		T34	1		T1	3
all_values[12]	auto[0]	auto[0]	auto[0]	2532545	1			T31	39638		T32	45766		T33	15422
all_values[12]	auto[0]	auto[0]	auto[1]	4107566	1			T33	44031		T34	32		T1	20
all_values[12]	auto[0]	auto[1]	auto[0]	454561	1			T33	5041		T34	9		T1	1
all_values[12]	auto[0]	auto[1]	auto[1]	4076217	1			T33	40779		T34	21		T1	4
all_values[12]	auto[1]	auto[0]	auto[1]	58938	1			T33	738		T34	3		T1	3
all_values[12]	auto[1]	auto[1]	auto[1]	59190	1			T33	674		T34	2		T1	1
all_values[13]	auto[0]	auto[0]	auto[0]	2528228	1			T31	39638		T32	45766		T33	15437
all_values[13]	auto[0]	auto[0]	auto[1]	4091598	1			T33	43249		T34	33		T1	29
all_values[13]	auto[0]	auto[1]	auto[0]	446293	1			T33	4958		T34	27		T1	5
all_values[13]	auto[0]	auto[1]	auto[1]	4105541	1			T33	41630		T34	7		T12	1098
all_values[13]	auto[1]	auto[0]	auto[1]	58727	1			T33	693		T34	4		T1	2
all_values[13]	auto[1]	auto[1]	auto[1]	58630	1			T33	718		T2	859		T26	37
all_values[14]	auto[0]	auto[0]	auto[0]	2532523	1			T31	39638		T32	45766		T33	15663
all_values[14]	auto[0]	auto[0]	auto[1]	4080090	1			T33	43343		T34	20		T1	19
all_values[14]	auto[0]	auto[1]	auto[0]	455749	1			T33	5246		T34	24		T1	10
all_values[14]	auto[0]	auto[1]	auto[1]	4103033	1			T33	41025		T34	21		T1	13
all_values[14]	auto[1]	auto[0]	auto[1]	59348	1			T33	760		T34	4		T1	3
all_values[14]	auto[1]	auto[1]	auto[1]	58274	1			T33	648		T34	3		T1	1
all_values[15]	auto[0]	auto[0]	auto[0]	2531907	1			T31	39638		T32	45766		T33	14888
all_values[15]	auto[0]	auto[0]	auto[1]	4112003	1			T33	43089		T34	19		T1	28
all_values[15]	auto[0]	auto[1]	auto[0]	447398	1			T33	5441		T34	37		T1	8
all_values[15]	auto[0]	auto[1]	auto[1]	4080407	1			T33	41854		T34	18		T1	4
all_values[15]	auto[1]	auto[0]	auto[1]	59327	1			T33	726		T34	4		T1	6
all_values[15]	auto[1]	auto[1]	auto[1]	57975	1			T33	687		T34	2		T2	822
all_values[16]	auto[0]	auto[0]	auto[0]	2528656	1			T31	39638		T32	45766		T33	15447
all_values[16]	auto[0]	auto[0]	auto[1]	4113014	1			T33	42280		T34	24		T1	33
all_values[16]	auto[0]	auto[1]	auto[0]	450033	1			T33	4617		T34	29		T12	141
all_values[16]	auto[0]	auto[1]	auto[1]	4079298	1			T33	42923		T34	12		T12	1811
all_values[16]	auto[1]	auto[0]	auto[1]	59014	1			T33	728		T34	2		T1	3
all_values[16]	auto[1]	auto[1]	auto[1]	59002	1			T33	690		T34	1		T2	842
all_values[17]	auto[0]	auto[0]	auto[0]	2526757	1			T31	39638		T32	45766		T33	15173
all_values[17]	auto[0]	auto[0]	auto[1]	4125371	1			T33	43173		T34	15		T1	13
all_values[17]	auto[0]	auto[1]	auto[0]	448104	1			T33	5006		T34	36		T1	12
all_values[17]	auto[0]	auto[1]	auto[1]	4071110	1			T33	41923		T34	16		T12	1317
all_values[17]	auto[1]	auto[0]	auto[1]	58971	1			T33	718		T34	3		T1	4
all_values[17]	auto[1]	auto[1]	auto[1]	58704	1			T33	692		T34	2		T2	907
all_values[18]	auto[0]	auto[0]	auto[0]	2533498	1			T31	39638		T32	45766		T33	15369
all_values[18]	auto[0]	auto[0]	auto[1]	4084811	1			T33	42648		T34	39		T1	20
all_values[18]	auto[0]	auto[1]	auto[0]	449376	1			T33	5529		T34	16		T1	11
all_values[18]	auto[0]	auto[1]	auto[1]	4103741	1			T33	41711		T34	15		T1	12
all_values[18]	auto[1]	auto[0]	auto[1]	59111	1			T33	723		T34	2		T1	2
all_values[18]	auto[1]	auto[1]	auto[1]	58480	1			T33	705		T34	2		T1	1
all_values[19]	auto[0]	auto[0]	auto[0]	2529692	1			T31	39638		T32	45766		T33	14853
all_values[19]	auto[0]	auto[0]	auto[1]	4098346	1			T33	42075		T34	25		T1	22
all_values[19]	auto[0]	auto[1]	auto[0]	447078	1			T33	5153		T34	26		T1	5
all_values[19]	auto[0]	auto[1]	auto[1]	4096126	1			T33	43162		T34	13		T1	6
all_values[19]	auto[1]	auto[0]	auto[1]	59211	1			T33	718		T34	4		T1	4
all_values[19]	auto[1]	auto[1]	auto[1]	58564	1			T33	724		T34	1		T2	882
all_values[20]	auto[0]	auto[0]	auto[0]	2532705	1			T31	39638		T32	45766		T33	15341
all_values[20]	auto[0]	auto[0]	auto[1]	4103138	1			T33	43133		T34	26		T1	23
all_values[20]	auto[0]	auto[1]	auto[0]	456552	1			T33	5519		T34	30		T1	7
all_values[20]	auto[0]	auto[1]	auto[1]	4078905	1			T33	41238		T34	25		T1	21
all_values[20]	auto[1]	auto[0]	auto[1]	59017	1			T33	671		T34	2		T1	3
all_values[20]	auto[1]	auto[1]	auto[1]	58700	1			T33	783		T1	2		T2	881
all_values[21]	auto[0]	auto[0]	auto[0]	2526411	1			T31	39638		T32	45766		T33	14837
all_values[21]	auto[0]	auto[0]	auto[1]	4137535	1			T33	42046		T34	21		T1	28
all_values[21]	auto[0]	auto[1]	auto[0]	442347	1			T33	4884		T34	39		T12	122
all_values[21]	auto[0]	auto[1]	auto[1]	4065048	1			T33	43560		T34	10		T1	6
all_values[21]	auto[1]	auto[0]	auto[1]	59372	1			T33	660		T34	3		T1	4
all_values[21]	auto[1]	auto[1]	auto[1]	58304	1			T33	698		T34	2		T2	854
all_values[22]	auto[0]	auto[0]	auto[0]	2534099	1			T31	39638		T32	45766		T33	15857
all_values[22]	auto[0]	auto[0]	auto[1]	4104806	1			T33	40236		T34	15		T1	16
all_values[22]	auto[0]	auto[1]	auto[0]	450546	1			T33	5596		T34	32		T1	2
all_values[22]	auto[0]	auto[1]	auto[1]	4081643	1			T33	43574		T34	12		T1	5
all_values[22]	auto[1]	auto[0]	auto[1]	59244	1			T33	761		T34	2		T1	5
all_values[22]	auto[1]	auto[1]	auto[1]	58679	1			T33	661		T34	2		T2	867
all_values[23]	auto[0]	auto[0]	auto[0]	2524653	1			T31	39638		T32	45766		T33	15120
all_values[23]	auto[0]	auto[0]	auto[1]	4097785	1			T33	42292		T34	34		T1	23
all_values[23]	auto[0]	auto[1]	auto[0]	449639	1			T33	5323		T34	12		T1	4
all_values[23]	auto[0]	auto[1]	auto[1]	4099293	1			T33	42537		T34	10		T1	14
all_values[23]	auto[1]	auto[0]	auto[1]	59410	1			T33	658		T34	7		T1	2
all_values[23]	auto[1]	auto[1]	auto[1]	58237	1			T33	755		T1	1		T2	825
all_values[24]	auto[0]	auto[0]	auto[0]	2534477	1			T31	39638		T32	45766		T33	15868
all_values[24]	auto[0]	auto[0]	auto[1]	4080412	1			T33	43401		T34	18		T1	19
all_values[24]	auto[0]	auto[1]	auto[0]	451983	1			T33	5380		T34	34		T1	8
all_values[24]	auto[0]	auto[1]	auto[1]	4104185	1			T33	40630		T34	16		T1	15
all_values[24]	auto[1]	auto[0]	auto[1]	58975	1			T33	754		T34	3		T1	3
all_values[24]	auto[1]	auto[1]	auto[1]	58985	1			T33	652		T34	1		T1	1
all_values[25]	auto[0]	auto[0]	auto[0]	2539315	1			T31	39638		T32	45766		T33	15680
all_values[25]	auto[0]	auto[0]	auto[1]	4113938	1			T33	42210		T34	43		T1	22
all_values[25]	auto[0]	auto[1]	auto[0]	445736	1			T33	5099		T34	7		T1	3
all_values[25]	auto[0]	auto[1]	auto[1]	4072956	1			T33	42307		T34	12		T1	18
all_values[25]	auto[1]	auto[0]	auto[1]	59065	1			T33	715		T34	4		T1	1
all_values[25]	auto[1]	auto[1]	auto[1]	58007	1			T33	674		T34	1		T1	2
all_values[26]	auto[0]	auto[0]	auto[0]	2525668	1			T31	39638		T32	45766		T33	15162
all_values[26]	auto[0]	auto[0]	auto[1]	4100325	1			T33	41718		T34	16		T1	12
all_values[26]	auto[0]	auto[1]	auto[0]	449576	1			T33	5195		T34	27		T1	8
all_values[26]	auto[0]	auto[1]	auto[1]	4095847	1			T33	43226		T34	20		T1	4
all_values[26]	auto[1]	auto[0]	auto[1]	59268	1			T33	663		T34	2		T1	2
all_values[26]	auto[1]	auto[1]	auto[1]	58333	1			T33	721		T34	3		T1	1
all_values[27]	auto[0]	auto[0]	auto[0]	2532214	1			T31	39638		T32	45766		T33	15612
all_values[27]	auto[0]	auto[0]	auto[1]	4092827	1			T33	41472		T34	11		T1	36
all_values[27]	auto[0]	auto[1]	auto[0]	453815	1			T33	5450		T34	28		T12	128
all_values[27]	auto[0]	auto[1]	auto[1]	4092611	1			T33	42727		T34	32		T12	1347
all_values[27]	auto[1]	auto[0]	auto[1]	59360	1			T33	676		T34	1		T1	3
all_values[27]	auto[1]	auto[1]	auto[1]	58190	1			T33	748		T34	3		T2	861
all_values[28]	auto[0]	auto[0]	auto[0]	2527462	1			T31	39638		T32	45766		T33	15714
all_values[28]	auto[0]	auto[0]	auto[1]	4084650	1			T33	42467		T34	34		T1	26
all_values[28]	auto[0]	auto[1]	auto[0]	456339	1			T33	5865		T34	13		T1	4
all_values[28]	auto[0]	auto[1]	auto[1]	4103225	1			T33	41226		T34	19		T1	1
all_values[28]	auto[1]	auto[0]	auto[1]	58661	1			T33	694		T34	3		T1	4
all_values[28]	auto[1]	auto[1]	auto[1]	58680	1			T33	719		T2	849		T26	35
all_values[29]	auto[0]	auto[0]	auto[0]	2535685	1			T31	39638		T32	45766		T33	15710
all_values[29]	auto[0]	auto[0]	auto[1]	4068903	1			T33	42849		T34	17		T1	34
all_values[29]	auto[0]	auto[1]	auto[0]	465390	1			T33	5108		T34	26		T1	4
all_values[29]	auto[0]	auto[1]	auto[1]	4101182	1			T33	41568		T34	4		T1	7
all_values[29]	auto[1]	auto[0]	auto[1]	58846	1			T33	721		T34	4		T1	4
all_values[29]	auto[1]	auto[1]	auto[1]	59011	1			T33	729		T34	1		T2	839
all_values[30]	auto[0]	auto[0]	auto[0]	2530582	1			T31	39638		T32	45766		T33	15138
all_values[30]	auto[0]	auto[0]	auto[1]	4086730	1			T33	42502		T34	13		T1	25
all_values[30]	auto[0]	auto[1]	auto[0]	444087	1			T33	4737		T34	20		T1	7
all_values[30]	auto[0]	auto[1]	auto[1]	4110253	1			T33	42910		T34	25		T1	12
all_values[30]	auto[1]	auto[0]	auto[1]	58838	1			T33	692		T34	3		T1	4
all_values[30]	auto[1]	auto[1]	auto[1]	58527	1			T33	706		T34	1		T2	854
all_values[31]	auto[0]	auto[0]	auto[0]	2531952	1			T31	39638		T32	45766		T33	15615
all_values[31]	auto[0]	auto[0]	auto[1]	4116107	1			T33	42564		T34	18		T1	18
all_values[31]	auto[0]	auto[1]	auto[0]	442466	1			T33	5192		T34	22		T1	10
all_values[31]	auto[0]	auto[1]	auto[1]	4081001	1			T33	41904		T34	16		T1	13
all_values[31]	auto[1]	auto[0]	auto[1]	58800	1			T33	739		T34	2		T1	2
all_values[31]	auto[1]	auto[1]	auto[1]	58691	1			T33	671		T34	2		T1	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal