Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[1]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[2]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[3]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[4]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[5]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[6]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[7]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[8]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[9]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[10]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[11]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[12]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[13]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[14]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[15]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[16]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[17]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[18]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[19]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[20]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[21]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[22]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[23]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[24]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[25]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[26]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[27]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[28]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[29]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[30]	11103496	1			T31	39638		T32	45766		T33	102590
bins_for_gpio_bits[31]	11103496	1			T31	39638		T32	45766		T33	102590

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

209587781

1

T31

633204

T32

736221

T33

112304

auto[1]

145724091

1

T31

635212

T32

728291

T33

215983

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

287562188

1

T31

126841

T32

146451

T33

252941

auto[1]

67749684

1

T33

753462

T34

794

T35

3631

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267840249

1

T31

126841

T32

146451

T33

232896

auto[1]

87471623

1

T33

953918

T34

2315

T35

3537

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4160452	1			T31	18892		T32	25493		T33	22052
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3141268	1			T31	20746		T32	20273		T33	38654
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1064479	1			T33	12388		T35	46		T1	4
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1328697	1			T33	1168		T34	73		T1	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	351251	1			T33	16889		T34	15		T35	68
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1057349	1			T33	11439		T34	21		T35	55
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4150369	1			T31	19547		T32	23155		T33	22211
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3151259	1			T31	20091		T32	22611		T33	38381
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1069312	1			T33	11903		T34	13		T35	50
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1321813	1			T33	1230		T34	12		T1	7
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	351257	1			T33	17081		T34	17		T35	66
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1059486	1			T33	11784		T34	9		T35	62
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4145796	1			T31	18833		T32	23393		T33	21794
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3162756	1			T31	20805		T32	22373		T33	39572
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1065385	1			T33	11506		T35	61		T1	6
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1329344	1			T33	1093		T34	30		T1	10
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	348440	1			T33	17100		T34	35		T35	40
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1051775	1			T33	11525		T34	19		T35	80
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4151671	1			T31	20009		T32	21700		T33	22053
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3152091	1			T31	19629		T32	24066		T33	39021
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1062383	1			T33	11866		T34	13		T35	68
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1332118	1			T33	996		T34	13		T1	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	350391	1			T33	17180		T34	25		T35	58
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1054842	1			T33	11474		T34	35		T35	53
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4150921	1			T31	19771		T32	24021		T33	22124
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3151535	1			T31	19867		T32	21745		T33	38202
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1062222	1			T33	11615		T34	2		T35	50
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1329456	1			T33	1108		T34	37		T1	11
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	352017	1			T33	17574		T34	8		T35	60
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1057345	1			T33	11967		T34	30		T35	47
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4160283	1			T31	20492		T32	22741		T33	22232
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3144026	1			T31	19146		T32	23025		T33	38586
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1069616	1			T33	12293		T34	3		T35	54
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1320083	1			T33	1050		T34	41		T1	6
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	350734	1			T33	16974		T34	24		T35	56
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1058754	1			T33	11455		T34	36		T35	67
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4156322	1			T31	20179		T32	23894		T33	22257
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3150513	1			T31	19459		T32	21872		T33	38474
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1061029	1			T33	12134		T34	11		T35	45
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1330562	1			T33	1086		T34	22		T1	9
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	351138	1			T33	17036		T34	12		T35	76
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1053932	1			T33	11603		T34	19		T35	52
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4141705	1			T31	19854		T32	23655		T33	21917
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3160337	1			T31	19784		T32	22111		T33	38522
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1060743	1			T33	11958		T35	58		T1	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1328515	1			T33	1127		T34	26		T1	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	352757	1			T33	17311		T34	14		T35	69
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1059439	1			T33	11755		T34	17		T35	58
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4157514	1			T31	19010		T32	21776		T33	21963
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3143007	1			T31	20628		T32	23990		T33	38889
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1066662	1			T33	11755		T34	5		T35	77
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1330242	1			T33	1081		T34	28		T1	15
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	350577	1			T33	17080		T34	11		T35	36
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1055494	1			T33	11822		T34	31		T35	40
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4157796	1			T31	19320		T32	23562		T33	21987
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3143980	1			T31	20318		T32	22204		T33	38613
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1068493	1			T33	11833		T34	10		T35	62
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1325296	1			T33	1183		T34	32		T1	5
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	350597	1			T33	17518		T34	15		T35	74
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1057334	1			T33	11456		T34	18		T35	38
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4153278	1			T31	20036		T32	23397		T33	22072
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3155571	1			T31	19602		T32	22369		T33	39239
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1067017	1			T33	11685		T34	10		T35	52
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1325356	1			T33	1023		T34	53		T1	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	347924	1			T33	17006		T34	16		T35	58
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1054350	1			T33	11565		T34	20		T35	61
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4149384	1			T31	20426		T32	22471		T33	21996
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3150411	1			T31	19212		T32	23295		T33	38476
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1068272	1			T33	11710		T34	12		T35	70
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1325232	1			T33	1177		T34	43		T1	18
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	350599	1			T33	17228		T34	7		T35	42
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1059598	1			T33	12003		T34	3		T35	50
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4159699	1			T31	18269		T32	23571		T33	21909
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3143590	1			T31	21369		T32	22195		T33	39166
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1066304	1			T33	11806		T34	12		T35	59
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1326594	1			T33	1098		T34	39		T1	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	352885	1			T33	17079		T34	19		T35	50
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1054424	1			T33	11532		T34	17		T35	50
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4156323	1			T31	19546		T32	22076		T33	22150
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3149165	1			T31	20092		T32	23690		T33	38345
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1068862	1			T33	12339		T34	12		T35	62
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1325951	1			T33	1071		T34	31		T11	39
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	350280	1			T33	17104		T34	25		T35	52
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1052915	1			T33	11581		T34	19		T35	47
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4157761	1			T31	20913		T32	23455		T33	22148
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3143548	1			T31	18725		T32	22311		T33	38619
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1065381	1			T33	12404		T34	22		T35	80
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1329408	1			T33	1125		T34	16		T1	19
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	350386	1			T33	16633		T34	18		T35	56
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1057012	1			T33	11661		T34	19		T35	48
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4149216	1			T31	18667		T32	23175		T33	21983
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3149476	1			T31	20971		T32	22591		T33	38733
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1066090	1			T33	11988		T34	3		T35	50
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1331658	1			T33	1110		T34	57		T1	8
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	351195	1			T33	17514		T34	14		T35	61
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1055861	1			T33	11262		T34	34		T35	58
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4174615	1			T31	20354		T32	23422		T33	22012
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3142316	1			T31	19284		T32	22344		T33	39526
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1062764	1			T33	12106		T34	5		T35	64
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1328596	1			T33	1033		T34	33		T1	15
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	349265	1			T33	16533		T34	21		T35	52
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1045940	1			T33	11380		T34	13		T35	60
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4165671	1			T31	20199		T32	22614		T33	21908
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3138575	1			T31	19439		T32	23152		T33	38772
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1062472	1			T33	12268		T34	1		T35	58
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1332952	1			T33	1045		T34	25		T11	18
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	349763	1			T33	16886		T34	34		T35	46
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1054063	1			T33	11711		T34	26		T35	42
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4165559	1			T31	20009		T32	23551		T33	21946
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3145009	1			T31	19629		T32	22215		T33	38767
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1061344	1			T33	11798		T34	2		T35	48
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1331104	1			T33	1133		T34	25		T1	13
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	351510	1			T33	17088		T34	19		T35	40
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1048970	1			T33	11858		T34	18		T35	64
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4148697	1			T31	19761		T32	22152		T33	21866
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3159742	1			T31	19877		T32	23614		T33	38927
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1060767	1			T33	11639		T34	5		T35	74
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1329032	1			T33	1097		T34	36		T1	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	350456	1			T33	17481		T34	33		T35	36
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1054802	1			T33	11580		T34	18		T35	43
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4158873	1			T31	18612		T32	23110		T33	21929
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3149548	1			T31	21026		T32	22656		T33	38656
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1063286	1			T33	11751		T35	57		T11	8
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1328472	1			T33	1184		T34	68		T1	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	350968	1			T33	17478		T34	22		T35	56
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1052349	1			T33	11592		T34	13		T35	76
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4152551	1			T31	18726		T32	24129		T33	22038
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3156649	1			T31	20912		T32	21637		T33	38651
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1064584	1			T33	12353		T35	68		T1	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1331017	1			T33	1094		T34	28		T1	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	350062	1			T33	16297		T34	15		T35	58
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1048633	1			T33	12157		T34	29		T35	53
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4160774	1			T31	21571		T32	22859		T33	21819
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3147882	1			T31	18067		T32	22907		T33	38199
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1057983	1			T33	11600		T34	8		T35	64
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1332945	1			T33	1225		T34	31		T1	13
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	351223	1			T33	17785		T34	13		T35	70
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1052689	1			T33	11962		T34	10		T35	57
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4163387	1			T31	20201		T32	22689		T33	22368
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3142254	1			T31	19437		T32	23077		T33	38738
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1065311	1			T33	12334		T34	5		T35	54
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1327677	1			T33	1035		T34	24		T1	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	351508	1			T33	16637		T34	31		T35	68
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1053359	1			T33	11478		T34	20		T35	51
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4154563	1			T31	19866		T32	22489		T33	22047
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3148679	1			T31	19772		T32	23277		T33	37990
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1065148	1			T33	12051		T35	58		T11	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1331089	1			T33	1092		T34	36		T1	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	351499	1			T33	17210		T34	18		T35	36
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1052518	1			T33	12200		T34	11		T35	71
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4153163	1			T31	19629		T32	22909		T33	22012
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3163376	1			T31	20009		T32	22857		T33	39019
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1060279	1			T33	11812		T34	22		T35	52
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1327848	1			T33	1082		T34	27		T1	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	350225	1			T33	17297		T34	8		T35	54
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1048605	1			T33	11368		T34	10		T35	53
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4159338	1			T31	19650		T32	21538		T33	21983
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3148672	1			T31	19988		T32	24228		T33	39374
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1062343	1			T33	12349		T34	6		T35	50
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1332736	1			T33	1089		T34	42		T1	16
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	351335	1			T33	16491		T34	17		T35	49
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1049072	1			T33	11304		T34	12		T35	54
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4164417	1			T31	20165		T32	22620		T33	22062
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3148684	1			T31	19473		T32	23146		T33	39353
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1059039	1			T33	12405		T34	1		T35	42
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1331550	1			T33	1076		T34	23		T1	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	350903	1			T33	16691		T34	9		T35	64
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1048903	1			T33	11003		T34	1		T35	63
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4160016	1			T31	21424		T32	22529		T33	21999
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3143713	1			T31	18214		T32	23237		T33	38625
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1062581	1			T33	11683		T34	12		T35	74
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1332295	1			T33	1183		T34	26		T1	11
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	354225	1			T33	17604		T34	25		T35	37
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1050666	1			T33	11496		T34	22		T35	38
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4144926	1			T31	19339		T32	22376		T33	22033
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3164505	1			T31	20299		T32	23390		T33	39382
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1060247	1			T33	11654		T34	3		T35	50
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1334288	1			T33	1154		T34	74		T1	19
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	349296	1			T33	17180		T34	14		T35	65
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1050234	1			T33	11187		T34	17		T35	66
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4166586	1			T31	20587		T32	23686		T33	22149
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3145401	1			T31	19051		T32	22080		T33	38738
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1055815	1			T33	11642		T35	55		T1	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1337068	1			T33	1062		T34	36		T11	23
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	351037	1			T33	17738		T34	22		T35	58
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1047589	1			T33	11261		T34	17		T35	42
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4161873	1			T31	19347		T32	22013		T33	21958
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3150232	1			T31	20291		T32	23753		T33	39064
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1062767	1			T33	12084		T34	7		T35	54
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1326308	1			T33	1043		T34	47		T1	16
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	349914	1			T33	17112		T34	16		T35	61
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1052402	1			T33	11329		T34	5		T35	66

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal