Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6684804 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58507 |
auto[1] |
4604213 |
1 |
|
|
T33 |
48178 |
|
T34 |
58 |
|
T1 |
17 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10694626 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100904 |
auto[1] |
594391 |
1 |
|
|
T33 |
5781 |
|
T1 |
1 |
|
T12 |
264 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6676294 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59820 |
auto[1] |
4612723 |
1 |
|
|
T33 |
46865 |
|
T34 |
23 |
|
T1 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2006688 |
1 |
|
|
T33 |
20791 |
|
T34 |
10 |
|
T1 |
29 |
auto[1] |
auto[0] |
auto[1] |
296985 |
1 |
|
|
T33 |
2915 |
|
T1 |
1 |
|
T12 |
135 |
auto[1] |
auto[1] |
auto[0] |
2011644 |
1 |
|
|
T33 |
20293 |
|
T34 |
13 |
|
T12 |
554 |
auto[1] |
auto[1] |
auto[1] |
297406 |
1 |
|
|
T33 |
2866 |
|
T12 |
129 |
|
T15 |
138 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6679301 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59106 |
auto[1] |
4609716 |
1 |
|
|
T33 |
47579 |
|
T34 |
26 |
|
T1 |
11 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10697384 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
101324 |
auto[1] |
591633 |
1 |
|
|
T33 |
5361 |
|
T34 |
2 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6692272 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60203 |
auto[1] |
4596745 |
1 |
|
|
T33 |
46482 |
|
T34 |
17 |
|
T1 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1997459 |
1 |
|
|
T33 |
20980 |
|
T34 |
10 |
|
T1 |
24 |
auto[1] |
auto[0] |
auto[1] |
293874 |
1 |
|
|
T33 |
2855 |
|
T34 |
1 |
|
T1 |
1 |
auto[1] |
auto[1] |
auto[0] |
2007653 |
1 |
|
|
T33 |
20141 |
|
T34 |
5 |
|
T12 |
693 |
auto[1] |
auto[1] |
auto[1] |
297759 |
1 |
|
|
T33 |
2506 |
|
T34 |
1 |
|
T12 |
174 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6675997 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59217 |
auto[1] |
4613020 |
1 |
|
|
T33 |
47468 |
|
T34 |
55 |
|
T1 |
18 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10697333 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
101043 |
auto[1] |
591684 |
1 |
|
|
T33 |
5642 |
|
T34 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6687164 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59635 |
auto[1] |
4601853 |
1 |
|
|
T33 |
47050 |
|
T34 |
28 |
|
T1 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2004480 |
1 |
|
|
T33 |
21010 |
|
T34 |
15 |
|
T1 |
25 |
auto[1] |
auto[0] |
auto[1] |
296264 |
1 |
|
|
T33 |
2904 |
|
T34 |
1 |
|
T1 |
1 |
auto[1] |
auto[1] |
auto[0] |
2005689 |
1 |
|
|
T33 |
20398 |
|
T34 |
12 |
|
T1 |
10 |
auto[1] |
auto[1] |
auto[1] |
295420 |
1 |
|
|
T33 |
2738 |
|
T12 |
183 |
|
T15 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6715981 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
55945 |
auto[1] |
4573036 |
1 |
|
|
T33 |
50740 |
|
T34 |
29 |
|
T1 |
25 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10695986 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100981 |
auto[1] |
593031 |
1 |
|
|
T33 |
5704 |
|
T12 |
295 |
|
T15 |
231 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6680062 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58951 |
auto[1] |
4608955 |
1 |
|
|
T33 |
47734 |
|
T34 |
3 |
|
T1 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2025435 |
1 |
|
|
T33 |
19536 |
|
T1 |
23 |
|
T12 |
619 |
auto[1] |
auto[0] |
auto[1] |
299999 |
1 |
|
|
T33 |
2608 |
|
T12 |
145 |
|
T15 |
129 |
auto[1] |
auto[1] |
auto[0] |
1990489 |
1 |
|
|
T33 |
22494 |
|
T34 |
3 |
|
T1 |
21 |
auto[1] |
auto[1] |
auto[1] |
293032 |
1 |
|
|
T33 |
3096 |
|
T12 |
150 |
|
T15 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6699049 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60191 |
auto[1] |
4589968 |
1 |
|
|
T33 |
46494 |
|
T34 |
32 |
|
T1 |
6 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10698889 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100779 |
auto[1] |
590128 |
1 |
|
|
T33 |
5906 |
|
T34 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6699383 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58652 |
auto[1] |
4589634 |
1 |
|
|
T33 |
48033 |
|
T34 |
18 |
|
T1 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1997174 |
1 |
|
|
T33 |
20855 |
|
T34 |
11 |
|
T1 |
33 |
auto[1] |
auto[0] |
auto[1] |
294188 |
1 |
|
|
T33 |
2868 |
|
T34 |
1 |
|
T1 |
1 |
auto[1] |
auto[1] |
auto[0] |
2002332 |
1 |
|
|
T33 |
21272 |
|
T34 |
6 |
|
T12 |
752 |
auto[1] |
auto[1] |
auto[1] |
295940 |
1 |
|
|
T33 |
3038 |
|
T12 |
212 |
|
T15 |
151 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6678553 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59379 |
auto[1] |
4610464 |
1 |
|
|
T33 |
47306 |
|
T34 |
34 |
|
T1 |
5 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10697555 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100865 |
auto[1] |
591462 |
1 |
|
|
T33 |
5820 |
|
T1 |
1 |
|
T12 |
315 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6695446 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58640 |
auto[1] |
4593571 |
1 |
|
|
T33 |
48045 |
|
T34 |
17 |
|
T1 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1994829 |
1 |
|
|
T33 |
21141 |
|
T34 |
3 |
|
T1 |
29 |
auto[1] |
auto[0] |
auto[1] |
294178 |
1 |
|
|
T33 |
3001 |
|
T1 |
1 |
|
T12 |
208 |
auto[1] |
auto[1] |
auto[0] |
2007280 |
1 |
|
|
T33 |
21084 |
|
T34 |
14 |
|
T12 |
501 |
auto[1] |
auto[1] |
auto[1] |
297284 |
1 |
|
|
T33 |
2819 |
|
T12 |
107 |
|
T15 |
147 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6671961 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59766 |
auto[1] |
4617056 |
1 |
|
|
T33 |
46919 |
|
T34 |
48 |
|
T1 |
24 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10697995 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100982 |
auto[1] |
591022 |
1 |
|
|
T33 |
5703 |
|
T12 |
318 |
|
T15 |
201 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6698147 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58969 |
auto[1] |
4590870 |
1 |
|
|
T33 |
47716 |
|
T34 |
20 |
|
T1 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1986744 |
1 |
|
|
T33 |
21038 |
|
T34 |
20 |
|
T1 |
13 |
auto[1] |
auto[0] |
auto[1] |
292522 |
1 |
|
|
T33 |
2848 |
|
T12 |
132 |
|
T15 |
80 |
auto[1] |
auto[1] |
auto[0] |
2013104 |
1 |
|
|
T33 |
20975 |
|
T1 |
9 |
|
T12 |
765 |
auto[1] |
auto[1] |
auto[1] |
298500 |
1 |
|
|
T33 |
2855 |
|
T12 |
186 |
|
T15 |
121 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6703237 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58703 |
auto[1] |
4585780 |
1 |
|
|
T33 |
47982 |
|
T34 |
57 |
|
T1 |
12 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10699734 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100287 |
auto[1] |
589283 |
1 |
|
|
T33 |
6398 |
|
T34 |
1 |
|
T12 |
250 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6707445 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
55410 |
auto[1] |
4581572 |
1 |
|
|
T33 |
51275 |
|
T34 |
10 |
|
T1 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2011932 |
1 |
|
|
T33 |
22663 |
|
T34 |
9 |
|
T1 |
25 |
auto[1] |
auto[0] |
auto[1] |
296731 |
1 |
|
|
T33 |
3183 |
|
T34 |
1 |
|
T12 |
139 |
auto[1] |
auto[1] |
auto[0] |
1980357 |
1 |
|
|
T33 |
22214 |
|
T1 |
4 |
|
T12 |
514 |
auto[1] |
auto[1] |
auto[1] |
292552 |
1 |
|
|
T33 |
3215 |
|
T12 |
111 |
|
T15 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6700684 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58455 |
auto[1] |
4588333 |
1 |
|
|
T33 |
48230 |
|
T34 |
42 |
|
T12 |
1952 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10699717 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
101177 |
auto[1] |
589300 |
1 |
|
|
T33 |
5508 |
|
T1 |
1 |
|
T12 |
251 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6709845 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59564 |
auto[1] |
4579172 |
1 |
|
|
T33 |
47121 |
|
T34 |
15 |
|
T1 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2006831 |
1 |
|
|
T33 |
20938 |
|
T34 |
4 |
|
T1 |
35 |
auto[1] |
auto[0] |
auto[1] |
296146 |
1 |
|
|
T33 |
2747 |
|
T1 |
1 |
|
T12 |
92 |
auto[1] |
auto[1] |
auto[0] |
1983041 |
1 |
|
|
T33 |
20675 |
|
T34 |
11 |
|
T12 |
719 |
auto[1] |
auto[1] |
auto[1] |
293154 |
1 |
|
|
T33 |
2761 |
|
T12 |
159 |
|
T15 |
86 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6711099 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59064 |
auto[1] |
4577918 |
1 |
|
|
T33 |
47621 |
|
T34 |
54 |
|
T1 |
12 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10694678 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100307 |
auto[1] |
594339 |
1 |
|
|
T33 |
6378 |
|
T34 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6667695 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
55635 |
auto[1] |
4621322 |
1 |
|
|
T33 |
51050 |
|
T34 |
26 |
|
T1 |
56 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2022279 |
1 |
|
|
T33 |
22638 |
|
T34 |
10 |
|
T1 |
51 |
auto[1] |
auto[0] |
auto[1] |
298427 |
1 |
|
|
T33 |
3276 |
|
T1 |
1 |
|
T12 |
142 |
auto[1] |
auto[1] |
auto[0] |
2004704 |
1 |
|
|
T33 |
22034 |
|
T34 |
15 |
|
T1 |
4 |
auto[1] |
auto[1] |
auto[1] |
295912 |
1 |
|
|
T33 |
3102 |
|
T34 |
1 |
|
T12 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6677420 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58740 |
auto[1] |
4611597 |
1 |
|
|
T33 |
47945 |
|
T34 |
33 |
|
T1 |
24 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10702949 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100780 |
auto[1] |
586068 |
1 |
|
|
T33 |
5905 |
|
T34 |
1 |
|
T12 |
301 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6725714 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58634 |
auto[1] |
4563303 |
1 |
|
|
T33 |
48051 |
|
T34 |
27 |
|
T1 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1974032 |
1 |
|
|
T33 |
21684 |
|
T34 |
23 |
|
T1 |
25 |
auto[1] |
auto[0] |
auto[1] |
289503 |
1 |
|
|
T33 |
3142 |
|
T34 |
1 |
|
T12 |
162 |
auto[1] |
auto[1] |
auto[0] |
2003203 |
1 |
|
|
T33 |
20462 |
|
T34 |
3 |
|
T1 |
10 |
auto[1] |
auto[1] |
auto[1] |
296565 |
1 |
|
|
T33 |
2763 |
|
T12 |
139 |
|
T15 |
101 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6687249 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57646 |
auto[1] |
4601768 |
1 |
|
|
T33 |
49039 |
|
T34 |
40 |
|
T1 |
11 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10702228 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100788 |
auto[1] |
586789 |
1 |
|
|
T33 |
5897 |
|
T1 |
1 |
|
T12 |
281 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6724285 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57296 |
auto[1] |
4564732 |
1 |
|
|
T33 |
49389 |
|
T34 |
38 |
|
T1 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1997119 |
1 |
|
|
T33 |
21547 |
|
T34 |
19 |
|
T1 |
23 |
auto[1] |
auto[0] |
auto[1] |
294299 |
1 |
|
|
T33 |
2880 |
|
T1 |
1 |
|
T12 |
153 |
auto[1] |
auto[1] |
auto[0] |
1980824 |
1 |
|
|
T33 |
21945 |
|
T34 |
19 |
|
T1 |
6 |
auto[1] |
auto[1] |
auto[1] |
292490 |
1 |
|
|
T33 |
3017 |
|
T12 |
128 |
|
T15 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6694669 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58770 |
auto[1] |
4594348 |
1 |
|
|
T33 |
47915 |
|
T34 |
22 |
|
T1 |
25 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10698195 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100826 |
auto[1] |
590822 |
1 |
|
|
T33 |
5859 |
|
T34 |
1 |
|
T12 |
308 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6696878 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58015 |
auto[1] |
4592139 |
1 |
|
|
T33 |
48670 |
|
T34 |
42 |
|
T1 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2009217 |
1 |
|
|
T33 |
21652 |
|
T34 |
34 |
|
T1 |
10 |
auto[1] |
auto[0] |
auto[1] |
296907 |
1 |
|
|
T33 |
3048 |
|
T12 |
105 |
|
T15 |
126 |
auto[1] |
auto[1] |
auto[0] |
1992100 |
1 |
|
|
T33 |
21159 |
|
T34 |
7 |
|
T1 |
5 |
auto[1] |
auto[1] |
auto[1] |
293915 |
1 |
|
|
T33 |
2811 |
|
T34 |
1 |
|
T12 |
203 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6694860 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59145 |
auto[1] |
4594157 |
1 |
|
|
T33 |
47540 |
|
T34 |
55 |
|
T1 |
30 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10696925 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
101200 |
auto[1] |
592092 |
1 |
|
|
T33 |
5485 |
|
T34 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6685473 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60026 |
auto[1] |
4603544 |
1 |
|
|
T33 |
46659 |
|
T34 |
32 |
|
T1 |
56 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2025842 |
1 |
|
|
T33 |
20623 |
|
T34 |
19 |
|
T1 |
33 |
auto[1] |
auto[0] |
auto[1] |
300056 |
1 |
|
|
T33 |
2760 |
|
T34 |
1 |
|
T1 |
1 |
auto[1] |
auto[1] |
auto[0] |
1985610 |
1 |
|
|
T33 |
20551 |
|
T34 |
12 |
|
T1 |
22 |
auto[1] |
auto[1] |
auto[1] |
292036 |
1 |
|
|
T33 |
2725 |
|
T12 |
96 |
|
T15 |
95 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6723318 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57543 |
auto[1] |
4565699 |
1 |
|
|
T33 |
49142 |
|
T34 |
51 |
|
T1 |
6 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10697792 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100734 |
auto[1] |
591225 |
1 |
|
|
T33 |
5951 |
|
T1 |
2 |
|
T12 |
298 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6687808 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57932 |
auto[1] |
4601209 |
1 |
|
|
T33 |
48753 |
|
T34 |
23 |
|
T1 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2019457 |
1 |
|
|
T33 |
20746 |
|
T34 |
20 |
|
T1 |
36 |
auto[1] |
auto[0] |
auto[1] |
297829 |
1 |
|
|
T33 |
2855 |
|
T1 |
2 |
|
T12 |
159 |
auto[1] |
auto[1] |
auto[0] |
1990527 |
1 |
|
|
T33 |
22056 |
|
T34 |
3 |
|
T12 |
577 |
auto[1] |
auto[1] |
auto[1] |
293396 |
1 |
|
|
T33 |
3096 |
|
T12 |
139 |
|
T15 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6698149 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
56854 |
auto[1] |
4590868 |
1 |
|
|
T33 |
49831 |
|
T34 |
46 |
|
T1 |
7 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10697365 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100759 |
auto[1] |
591652 |
1 |
|
|
T33 |
5926 |
|
T1 |
1 |
|
T12 |
344 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6688071 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57026 |
auto[1] |
4600946 |
1 |
|
|
T33 |
49659 |
|
T34 |
35 |
|
T1 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2021882 |
1 |
|
|
T33 |
20724 |
|
T34 |
19 |
|
T1 |
26 |
auto[1] |
auto[0] |
auto[1] |
299839 |
1 |
|
|
T33 |
2733 |
|
T1 |
1 |
|
T12 |
172 |
auto[1] |
auto[1] |
auto[0] |
1987412 |
1 |
|
|
T33 |
23009 |
|
T34 |
16 |
|
T1 |
2 |
auto[1] |
auto[1] |
auto[1] |
291813 |
1 |
|
|
T33 |
3193 |
|
T12 |
172 |
|
T15 |
141 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6681848 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58070 |
auto[1] |
4607169 |
1 |
|
|
T33 |
48615 |
|
T34 |
22 |
|
T1 |
19 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10700455 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
101104 |
auto[1] |
588562 |
1 |
|
|
T33 |
5581 |
|
T34 |
2 |
|
T12 |
277 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6710175 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59350 |
auto[1] |
4578842 |
1 |
|
|
T33 |
47335 |
|
T34 |
41 |
|
T1 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1997931 |
1 |
|
|
T33 |
21049 |
|
T34 |
34 |
|
T1 |
19 |
auto[1] |
auto[0] |
auto[1] |
294093 |
1 |
|
|
T33 |
2865 |
|
T34 |
2 |
|
T12 |
137 |
auto[1] |
auto[1] |
auto[0] |
1992349 |
1 |
|
|
T33 |
20705 |
|
T34 |
5 |
|
T1 |
16 |
auto[1] |
auto[1] |
auto[1] |
294469 |
1 |
|
|
T33 |
2716 |
|
T12 |
140 |
|
T15 |
67 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6673864 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60023 |
auto[1] |
4615153 |
1 |
|
|
T33 |
46662 |
|
T34 |
51 |
|
T1 |
24 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10691072 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100883 |
auto[1] |
597945 |
1 |
|
|
T33 |
5802 |
|
T12 |
294 |
|
T15 |
182 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6653847 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58806 |
auto[1] |
4635170 |
1 |
|
|
T33 |
47879 |
|
T34 |
23 |
|
T1 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2017036 |
1 |
|
|
T33 |
21601 |
|
T34 |
9 |
|
T1 |
25 |
auto[1] |
auto[0] |
auto[1] |
298535 |
1 |
|
|
T33 |
3020 |
|
T12 |
94 |
|
T15 |
95 |
auto[1] |
auto[1] |
auto[0] |
2020189 |
1 |
|
|
T33 |
20476 |
|
T34 |
14 |
|
T1 |
11 |
auto[1] |
auto[1] |
auto[1] |
299410 |
1 |
|
|
T33 |
2782 |
|
T12 |
200 |
|
T15 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6712318 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58605 |
auto[1] |
4576699 |
1 |
|
|
T33 |
48080 |
|
T34 |
20 |
|
T1 |
23 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10699052 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100889 |
auto[1] |
589965 |
1 |
|
|
T33 |
5796 |
|
T34 |
1 |
|
T12 |
293 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6694262 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58975 |
auto[1] |
4594755 |
1 |
|
|
T33 |
47710 |
|
T34 |
44 |
|
T1 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2006112 |
1 |
|
|
T33 |
20756 |
|
T34 |
29 |
|
T1 |
14 |
auto[1] |
auto[0] |
auto[1] |
293508 |
1 |
|
|
T33 |
2883 |
|
T12 |
100 |
|
T15 |
117 |
auto[1] |
auto[1] |
auto[0] |
1998678 |
1 |
|
|
T33 |
21158 |
|
T34 |
14 |
|
T1 |
17 |
auto[1] |
auto[1] |
auto[1] |
296457 |
1 |
|
|
T33 |
2913 |
|
T34 |
1 |
|
T12 |
193 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6685261 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57543 |
auto[1] |
4603756 |
1 |
|
|
T33 |
49142 |
|
T34 |
50 |
|
T1 |
13 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10696389 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100746 |
auto[1] |
592628 |
1 |
|
|
T33 |
5939 |
|
T1 |
2 |
|
T12 |
306 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6680261 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57313 |
auto[1] |
4608756 |
1 |
|
|
T33 |
49372 |
|
T34 |
30 |
|
T1 |
33 |