Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6686633 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59212 |
| auto[1] |
4602384 |
1 |
|
|
T33 |
47473 |
|
T34 |
39 |
|
T1 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10704182 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
101737 |
| auto[1] |
584835 |
1 |
|
|
T33 |
4948 |
|
T34 |
1 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6726823 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
63718 |
| auto[1] |
4562194 |
1 |
|
|
T33 |
42967 |
|
T34 |
32 |
|
T1 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1989779 |
1 |
|
|
T33 |
18658 |
|
T34 |
26 |
|
T1 |
33 |
| auto[1] |
auto[0] |
auto[1] |
292418 |
1 |
|
|
T33 |
2460 |
|
T34 |
1 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1987580 |
1 |
|
|
T33 |
19361 |
|
T34 |
5 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[1] |
292417 |
1 |
|
|
T33 |
2488 |
|
T1 |
1 |
|
T12 |
165 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |