Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6686483 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58290 |
| auto[1] |
4602534 |
1 |
|
|
T33 |
48395 |
|
T34 |
24 |
|
T1 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10697044 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
101244 |
| auto[1] |
591973 |
1 |
|
|
T33 |
5441 |
|
T1 |
3 |
|
T12 |
290 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6687725 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60321 |
| auto[1] |
4601292 |
1 |
|
|
T33 |
46364 |
|
T34 |
47 |
|
T1 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2000893 |
1 |
|
|
T33 |
20075 |
|
T34 |
37 |
|
T1 |
23 |
| auto[1] |
auto[0] |
auto[1] |
294268 |
1 |
|
|
T33 |
2633 |
|
T1 |
2 |
|
T12 |
160 |
| auto[1] |
auto[1] |
auto[0] |
2008426 |
1 |
|
|
T33 |
20848 |
|
T34 |
10 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[1] |
297705 |
1 |
|
|
T33 |
2808 |
|
T1 |
1 |
|
T12 |
130 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |