Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6703601 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57924 |
| auto[1] |
4585416 |
1 |
|
|
T33 |
48761 |
|
T34 |
39 |
|
T1 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10697012 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
101243 |
| auto[1] |
592005 |
1 |
|
|
T33 |
5442 |
|
T34 |
1 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6694872 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60971 |
| auto[1] |
4594145 |
1 |
|
|
T33 |
45714 |
|
T34 |
15 |
|
T1 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2004812 |
1 |
|
|
T33 |
19894 |
|
T34 |
10 |
|
T1 |
16 |
| auto[1] |
auto[0] |
auto[1] |
296376 |
1 |
|
|
T33 |
2641 |
|
T1 |
1 |
|
T12 |
169 |
| auto[1] |
auto[1] |
auto[0] |
1997328 |
1 |
|
|
T33 |
20378 |
|
T34 |
4 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[1] |
295629 |
1 |
|
|
T33 |
2801 |
|
T34 |
1 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |