Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6684804 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58507 |
| auto[1] |
4604213 |
1 |
|
|
T33 |
48178 |
|
T34 |
58 |
|
T1 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9369562 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
78820 |
| auto[1] |
1919455 |
1 |
|
|
T33 |
27865 |
|
T34 |
6 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6686326 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
61026 |
| auto[1] |
4602691 |
1 |
|
|
T33 |
45659 |
|
T34 |
17 |
|
T1 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1338061 |
1 |
|
|
T33 |
9003 |
|
T34 |
2 |
|
T1 |
14 |
| auto[1] |
auto[0] |
auto[1] |
960333 |
1 |
|
|
T33 |
14095 |
|
T34 |
6 |
|
T12 |
437 |
| auto[1] |
auto[1] |
auto[0] |
1345175 |
1 |
|
|
T33 |
8791 |
|
T34 |
9 |
|
T1 |
13 |
| auto[1] |
auto[1] |
auto[1] |
959122 |
1 |
|
|
T33 |
13770 |
|
T1 |
1 |
|
T12 |
425 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |