Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6679301 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59106 |
| auto[1] |
4609716 |
1 |
|
|
T33 |
47579 |
|
T34 |
26 |
|
T1 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9368207 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
76363 |
| auto[1] |
1920810 |
1 |
|
|
T33 |
30322 |
|
T34 |
15 |
|
T1 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6686699 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57800 |
| auto[1] |
4602318 |
1 |
|
|
T33 |
48885 |
|
T34 |
23 |
|
T1 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1337753 |
1 |
|
|
T33 |
9471 |
|
T34 |
4 |
|
T1 |
6 |
| auto[1] |
auto[0] |
auto[1] |
957825 |
1 |
|
|
T33 |
14834 |
|
T34 |
10 |
|
T1 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1343755 |
1 |
|
|
T33 |
9092 |
|
T34 |
4 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
962985 |
1 |
|
|
T33 |
15488 |
|
T34 |
5 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |