Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6675997 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59217 |
| auto[1] |
4613020 |
1 |
|
|
T33 |
47468 |
|
T34 |
55 |
|
T1 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9364994 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
75082 |
| auto[1] |
1924023 |
1 |
|
|
T33 |
31603 |
|
T34 |
12 |
|
T1 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6681748 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
55813 |
| auto[1] |
4607269 |
1 |
|
|
T33 |
50872 |
|
T34 |
23 |
|
T1 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1340239 |
1 |
|
|
T33 |
9922 |
|
T1 |
11 |
|
T12 |
391 |
| auto[1] |
auto[0] |
auto[1] |
962352 |
1 |
|
|
T33 |
16800 |
|
T34 |
2 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1343007 |
1 |
|
|
T33 |
9347 |
|
T34 |
11 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[1] |
961671 |
1 |
|
|
T33 |
14803 |
|
T34 |
10 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |