Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6699049 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60191 |
| auto[1] |
4589968 |
1 |
|
|
T33 |
46494 |
|
T34 |
32 |
|
T1 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9377767 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
77414 |
| auto[1] |
1911250 |
1 |
|
|
T33 |
29271 |
|
T34 |
2 |
|
T12 |
811 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6698263 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59549 |
| auto[1] |
4590754 |
1 |
|
|
T33 |
47136 |
|
T34 |
19 |
|
T1 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1351842 |
1 |
|
|
T33 |
9047 |
|
T34 |
15 |
|
T1 |
9 |
| auto[1] |
auto[0] |
auto[1] |
962790 |
1 |
|
|
T33 |
15151 |
|
T34 |
1 |
|
T12 |
361 |
| auto[1] |
auto[1] |
auto[0] |
1327662 |
1 |
|
|
T33 |
8818 |
|
T34 |
2 |
|
T12 |
444 |
| auto[1] |
auto[1] |
auto[1] |
948460 |
1 |
|
|
T33 |
14120 |
|
T34 |
1 |
|
T12 |
450 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |