Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6671961 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59766 |
| auto[1] |
4617056 |
1 |
|
|
T33 |
46919 |
|
T34 |
48 |
|
T1 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9377749 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
78362 |
| auto[1] |
1911268 |
1 |
|
|
T33 |
28323 |
|
T1 |
4 |
|
T12 |
770 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6703692 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60048 |
| auto[1] |
4585325 |
1 |
|
|
T33 |
46637 |
|
T34 |
6 |
|
T1 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1332903 |
1 |
|
|
T33 |
9368 |
|
T34 |
5 |
|
T1 |
15 |
| auto[1] |
auto[0] |
auto[1] |
952057 |
1 |
|
|
T33 |
14426 |
|
T1 |
3 |
|
T12 |
359 |
| auto[1] |
auto[1] |
auto[0] |
1341154 |
1 |
|
|
T33 |
8946 |
|
T34 |
1 |
|
T1 |
10 |
| auto[1] |
auto[1] |
auto[1] |
959211 |
1 |
|
|
T33 |
13897 |
|
T1 |
1 |
|
T12 |
411 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |