Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6703237 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58703 |
| auto[1] |
4585780 |
1 |
|
|
T33 |
47982 |
|
T34 |
57 |
|
T1 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9378262 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
76290 |
| auto[1] |
1910755 |
1 |
|
|
T33 |
30395 |
|
T34 |
1 |
|
T1 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6704720 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57919 |
| auto[1] |
4584297 |
1 |
|
|
T33 |
48766 |
|
T34 |
11 |
|
T1 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1339555 |
1 |
|
|
T33 |
9236 |
|
T1 |
12 |
|
T12 |
398 |
| auto[1] |
auto[0] |
auto[1] |
951655 |
1 |
|
|
T33 |
15394 |
|
T1 |
11 |
|
T12 |
385 |
| auto[1] |
auto[1] |
auto[0] |
1333987 |
1 |
|
|
T33 |
9135 |
|
T34 |
10 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
959100 |
1 |
|
|
T33 |
15001 |
|
T34 |
1 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |