Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6687249 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57646 |
| auto[1] |
4601768 |
1 |
|
|
T33 |
49039 |
|
T34 |
40 |
|
T1 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9362930 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
75684 |
| auto[1] |
1926087 |
1 |
|
|
T33 |
31001 |
|
T34 |
7 |
|
T1 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6684593 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57649 |
| auto[1] |
4604424 |
1 |
|
|
T33 |
49036 |
|
T34 |
28 |
|
T1 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1334595 |
1 |
|
|
T33 |
8848 |
|
T34 |
11 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
960009 |
1 |
|
|
T33 |
15506 |
|
T34 |
6 |
|
T1 |
23 |
| auto[1] |
auto[1] |
auto[0] |
1343742 |
1 |
|
|
T33 |
9187 |
|
T34 |
10 |
|
T12 |
293 |
| auto[1] |
auto[1] |
auto[1] |
966078 |
1 |
|
|
T33 |
15495 |
|
T34 |
1 |
|
T12 |
331 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |