Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6694669 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58770 |
| auto[1] |
4594348 |
1 |
|
|
T33 |
47915 |
|
T34 |
22 |
|
T1 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9375991 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
77367 |
| auto[1] |
1913026 |
1 |
|
|
T33 |
29318 |
|
T34 |
4 |
|
T1 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6695870 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60166 |
| auto[1] |
4593147 |
1 |
|
|
T33 |
46519 |
|
T34 |
21 |
|
T1 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1344293 |
1 |
|
|
T33 |
8744 |
|
T34 |
11 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
955693 |
1 |
|
|
T33 |
14508 |
|
T34 |
4 |
|
T1 |
17 |
| auto[1] |
auto[1] |
auto[0] |
1335828 |
1 |
|
|
T33 |
8457 |
|
T34 |
6 |
|
T12 |
479 |
| auto[1] |
auto[1] |
auto[1] |
957333 |
1 |
|
|
T33 |
14810 |
|
T1 |
10 |
|
T12 |
537 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |