Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6694860 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59145 |
| auto[1] |
4594157 |
1 |
|
|
T33 |
47540 |
|
T34 |
55 |
|
T1 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9372470 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
75778 |
| auto[1] |
1916547 |
1 |
|
|
T33 |
30907 |
|
T34 |
9 |
|
T1 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6684784 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
56426 |
| auto[1] |
4604233 |
1 |
|
|
T33 |
50259 |
|
T34 |
15 |
|
T1 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1334064 |
1 |
|
|
T33 |
9854 |
|
T34 |
5 |
|
T1 |
3 |
| auto[1] |
auto[0] |
auto[1] |
954853 |
1 |
|
|
T33 |
16001 |
|
T34 |
3 |
|
T1 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1353622 |
1 |
|
|
T33 |
9498 |
|
T34 |
1 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[1] |
961694 |
1 |
|
|
T33 |
14906 |
|
T34 |
6 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |