Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6723318 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57543 |
| auto[1] |
4565699 |
1 |
|
|
T33 |
49142 |
|
T34 |
51 |
|
T1 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9365004 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
76393 |
| auto[1] |
1924013 |
1 |
|
|
T33 |
30292 |
|
T34 |
10 |
|
T1 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6671754 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57290 |
| auto[1] |
4617263 |
1 |
|
|
T33 |
49395 |
|
T34 |
21 |
|
T1 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1356513 |
1 |
|
|
T33 |
9492 |
|
T1 |
14 |
|
T12 |
404 |
| auto[1] |
auto[0] |
auto[1] |
965027 |
1 |
|
|
T33 |
14728 |
|
T34 |
5 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1336737 |
1 |
|
|
T33 |
9611 |
|
T34 |
11 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[1] |
958986 |
1 |
|
|
T33 |
15564 |
|
T34 |
5 |
|
T12 |
417 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |