Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6684401 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57760 |
| auto[1] |
4604616 |
1 |
|
|
T33 |
48925 |
|
T34 |
63 |
|
T12 |
1475 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10697675 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100851 |
| auto[1] |
591342 |
1 |
|
|
T33 |
5834 |
|
T34 |
2 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6684011 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58080 |
| auto[1] |
4605006 |
1 |
|
|
T33 |
48605 |
|
T34 |
34 |
|
T1 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2011033 |
1 |
|
|
T33 |
20847 |
|
T34 |
4 |
|
T1 |
30 |
| auto[1] |
auto[0] |
auto[1] |
295778 |
1 |
|
|
T33 |
2878 |
|
T1 |
2 |
|
T12 |
149 |
| auto[1] |
auto[1] |
auto[0] |
2002631 |
1 |
|
|
T33 |
21924 |
|
T34 |
28 |
|
T12 |
676 |
| auto[1] |
auto[1] |
auto[1] |
295564 |
1 |
|
|
T33 |
2956 |
|
T34 |
2 |
|
T12 |
166 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |