Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6698149 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
56854 |
| auto[1] |
4590868 |
1 |
|
|
T33 |
49831 |
|
T34 |
46 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9384271 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
76696 |
| auto[1] |
1904746 |
1 |
|
|
T33 |
29989 |
|
T34 |
5 |
|
T1 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6723626 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58471 |
| auto[1] |
4565391 |
1 |
|
|
T33 |
48214 |
|
T34 |
21 |
|
T1 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1326941 |
1 |
|
|
T33 |
8899 |
|
T34 |
5 |
|
T1 |
2 |
| auto[1] |
auto[0] |
auto[1] |
953984 |
1 |
|
|
T33 |
14151 |
|
T34 |
3 |
|
T1 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1333704 |
1 |
|
|
T33 |
9326 |
|
T34 |
11 |
|
T12 |
396 |
| auto[1] |
auto[1] |
auto[1] |
950762 |
1 |
|
|
T33 |
15838 |
|
T34 |
2 |
|
T12 |
409 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |