Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6681848 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58070 |
| auto[1] |
4607169 |
1 |
|
|
T33 |
48615 |
|
T34 |
22 |
|
T1 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9375707 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
76655 |
| auto[1] |
1913310 |
1 |
|
|
T33 |
30030 |
|
T34 |
7 |
|
T1 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6704336 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57354 |
| auto[1] |
4584681 |
1 |
|
|
T33 |
49331 |
|
T34 |
23 |
|
T1 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1340141 |
1 |
|
|
T33 |
9538 |
|
T34 |
11 |
|
T1 |
15 |
| auto[1] |
auto[0] |
auto[1] |
956319 |
1 |
|
|
T33 |
14874 |
|
T34 |
7 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1331230 |
1 |
|
|
T33 |
9763 |
|
T34 |
5 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[1] |
956991 |
1 |
|
|
T33 |
15156 |
|
T12 |
349 |
|
T15 |
226 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |