Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6673864 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60023 |
| auto[1] |
4615153 |
1 |
|
|
T33 |
46662 |
|
T34 |
51 |
|
T1 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9377758 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
77857 |
| auto[1] |
1911259 |
1 |
|
|
T33 |
28828 |
|
T34 |
14 |
|
T12 |
686 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6703254 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
60444 |
| auto[1] |
4585763 |
1 |
|
|
T33 |
46241 |
|
T34 |
20 |
|
T1 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1329080 |
1 |
|
|
T33 |
8751 |
|
T34 |
5 |
|
T1 |
8 |
| auto[1] |
auto[0] |
auto[1] |
954236 |
1 |
|
|
T33 |
14248 |
|
T34 |
6 |
|
T12 |
222 |
| auto[1] |
auto[1] |
auto[0] |
1345424 |
1 |
|
|
T33 |
8662 |
|
T34 |
1 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[1] |
957023 |
1 |
|
|
T33 |
14580 |
|
T34 |
8 |
|
T12 |
464 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |