Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6663434 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
59280 |
| auto[1] |
4625583 |
1 |
|
|
T33 |
47405 |
|
T34 |
31 |
|
T1 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10700381 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100779 |
| auto[1] |
588636 |
1 |
|
|
T33 |
5906 |
|
T1 |
1 |
|
T12 |
319 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6706996 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
57352 |
| auto[1] |
4582021 |
1 |
|
|
T33 |
49333 |
|
T34 |
30 |
|
T1 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1986138 |
1 |
|
|
T33 |
22113 |
|
T34 |
26 |
|
T1 |
28 |
| auto[1] |
auto[0] |
auto[1] |
293149 |
1 |
|
|
T33 |
3100 |
|
T12 |
193 |
|
T15 |
74 |
| auto[1] |
auto[1] |
auto[0] |
2007247 |
1 |
|
|
T33 |
21314 |
|
T34 |
4 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
295487 |
1 |
|
|
T33 |
2806 |
|
T1 |
1 |
|
T12 |
126 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |