Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6692862 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58652 |
| auto[1] |
4596155 |
1 |
|
|
T33 |
48033 |
|
T34 |
26 |
|
T1 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10697532 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
100979 |
| auto[1] |
591485 |
1 |
|
|
T33 |
5706 |
|
T34 |
1 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6688528 |
1 |
|
|
T31 |
39638 |
|
T32 |
45766 |
|
T33 |
58650 |
| auto[1] |
4600489 |
1 |
|
|
T33 |
48035 |
|
T34 |
15 |
|
T1 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2008477 |
1 |
|
|
T33 |
21986 |
|
T34 |
9 |
|
T1 |
27 |
| auto[1] |
auto[0] |
auto[1] |
295714 |
1 |
|
|
T33 |
2958 |
|
T34 |
1 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2000527 |
1 |
|
|
T33 |
20343 |
|
T34 |
5 |
|
T12 |
651 |
| auto[1] |
auto[1] |
auto[1] |
295771 |
1 |
|
|
T33 |
2748 |
|
T12 |
159 |
|
T15 |
127 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |