Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 939
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T760 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3559218397 Mar 28 12:53:05 PM PDT 24 Mar 28 12:53:06 PM PDT 24 11898013 ps
T761 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1874478129 Mar 28 12:52:38 PM PDT 24 Mar 28 12:52:39 PM PDT 24 256252693 ps
T762 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4240629558 Mar 28 12:52:53 PM PDT 24 Mar 28 12:52:56 PM PDT 24 85233847 ps
T763 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2353401111 Mar 28 12:52:44 PM PDT 24 Mar 28 12:52:45 PM PDT 24 64131392 ps
T764 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.992728346 Mar 28 12:53:00 PM PDT 24 Mar 28 12:53:04 PM PDT 24 58498672 ps
T765 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3939139223 Mar 28 12:52:44 PM PDT 24 Mar 28 12:52:45 PM PDT 24 22808435 ps
T48 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.200951356 Mar 28 12:52:47 PM PDT 24 Mar 28 12:52:48 PM PDT 24 193370987 ps
T766 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3656054158 Mar 28 12:52:36 PM PDT 24 Mar 28 12:52:37 PM PDT 24 38169081 ps
T767 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.4146729978 Mar 28 12:52:44 PM PDT 24 Mar 28 12:52:45 PM PDT 24 137978166 ps
T768 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4195380405 Mar 28 12:52:36 PM PDT 24 Mar 28 12:52:36 PM PDT 24 32669253 ps
T769 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.138972869 Mar 28 12:53:13 PM PDT 24 Mar 28 12:53:14 PM PDT 24 158073012 ps
T92 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.608906114 Mar 28 12:52:51 PM PDT 24 Mar 28 12:52:53 PM PDT 24 58737827 ps
T770 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3904164528 Mar 28 12:53:09 PM PDT 24 Mar 28 12:53:10 PM PDT 24 34143606 ps
T771 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3530081506 Mar 28 12:52:56 PM PDT 24 Mar 28 12:52:58 PM PDT 24 42251406 ps
T772 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.987445612 Mar 28 12:52:45 PM PDT 24 Mar 28 12:52:46 PM PDT 24 16361428 ps
T773 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4102608298 Mar 28 12:52:48 PM PDT 24 Mar 28 12:52:51 PM PDT 24 638881869 ps
T51 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2860980288 Mar 28 12:52:39 PM PDT 24 Mar 28 12:52:41 PM PDT 24 100992288 ps
T774 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2129940886 Mar 28 12:53:10 PM PDT 24 Mar 28 12:53:11 PM PDT 24 11814432 ps
T775 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1354043362 Mar 28 12:53:35 PM PDT 24 Mar 28 12:53:36 PM PDT 24 19009722 ps
T776 /workspace/coverage/cover_reg_top/40.gpio_intr_test.666853120 Mar 28 12:53:13 PM PDT 24 Mar 28 12:53:14 PM PDT 24 92774880 ps
T777 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3212282621 Mar 28 12:52:46 PM PDT 24 Mar 28 12:52:47 PM PDT 24 15330361 ps
T778 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3624167257 Mar 28 12:52:44 PM PDT 24 Mar 28 12:52:45 PM PDT 24 146329982 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3673159892 Mar 28 12:52:29 PM PDT 24 Mar 28 12:52:32 PM PDT 24 395877515 ps
T780 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4185187462 Mar 28 12:53:00 PM PDT 24 Mar 28 12:53:05 PM PDT 24 114192357 ps
T781 /workspace/coverage/cover_reg_top/10.gpio_intr_test.894435155 Mar 28 12:52:59 PM PDT 24 Mar 28 12:53:01 PM PDT 24 36373017 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1916316934 Mar 28 12:52:36 PM PDT 24 Mar 28 12:52:37 PM PDT 24 30952643 ps
T783 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.976686841 Mar 28 12:52:32 PM PDT 24 Mar 28 12:52:33 PM PDT 24 314778697 ps
T784 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2703605137 Mar 28 12:52:58 PM PDT 24 Mar 28 12:53:02 PM PDT 24 905638125 ps
T785 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1319225889 Mar 28 12:52:44 PM PDT 24 Mar 28 12:52:45 PM PDT 24 14650768 ps
T93 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2237185310 Mar 28 12:52:43 PM PDT 24 Mar 28 12:52:47 PM PDT 24 1335976551 ps
T94 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1527987761 Mar 28 12:52:55 PM PDT 24 Mar 28 12:52:56 PM PDT 24 13924719 ps
T786 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2805067145 Mar 28 12:52:54 PM PDT 24 Mar 28 12:52:56 PM PDT 24 25951195 ps
T787 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3033231254 Mar 28 12:53:09 PM PDT 24 Mar 28 12:53:09 PM PDT 24 16189906 ps
T788 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3906912326 Mar 28 12:53:13 PM PDT 24 Mar 28 12:53:14 PM PDT 24 94569909 ps
T95 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.287258166 Mar 28 12:52:26 PM PDT 24 Mar 28 12:52:27 PM PDT 24 48393011 ps
T789 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.824038915 Mar 28 12:52:47 PM PDT 24 Mar 28 12:52:48 PM PDT 24 215527044 ps
T790 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4117881309 Mar 28 12:53:01 PM PDT 24 Mar 28 12:53:05 PM PDT 24 52221978 ps
T791 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1742926584 Mar 28 12:53:00 PM PDT 24 Mar 28 12:53:04 PM PDT 24 18241872 ps
T792 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3318782179 Mar 28 12:52:33 PM PDT 24 Mar 28 12:52:34 PM PDT 24 104740794 ps
T793 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1141092602 Mar 28 12:52:50 PM PDT 24 Mar 28 12:52:51 PM PDT 24 39207958 ps
T794 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2423806720 Mar 28 12:52:30 PM PDT 24 Mar 28 12:52:31 PM PDT 24 134504746 ps
T795 /workspace/coverage/cover_reg_top/36.gpio_intr_test.647828497 Mar 28 12:53:07 PM PDT 24 Mar 28 12:53:08 PM PDT 24 173823467 ps
T796 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1614771313 Mar 28 12:53:10 PM PDT 24 Mar 28 12:53:11 PM PDT 24 18404606 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.390896760 Mar 28 12:52:33 PM PDT 24 Mar 28 12:52:34 PM PDT 24 57960112 ps
T798 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1237428679 Mar 28 12:53:11 PM PDT 24 Mar 28 12:53:15 PM PDT 24 167442748 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4078779209 Mar 28 12:52:30 PM PDT 24 Mar 28 12:52:33 PM PDT 24 52809753 ps
T800 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2690001664 Mar 28 12:52:53 PM PDT 24 Mar 28 12:52:55 PM PDT 24 65472798 ps
T801 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1517055473 Mar 28 12:53:13 PM PDT 24 Mar 28 12:53:14 PM PDT 24 75603336 ps
T802 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2115965890 Mar 28 12:53:11 PM PDT 24 Mar 28 12:53:12 PM PDT 24 37915201 ps
T803 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4015675047 Mar 28 12:52:48 PM PDT 24 Mar 28 12:52:48 PM PDT 24 46042689 ps
T804 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2072502781 Mar 28 12:52:41 PM PDT 24 Mar 28 12:52:42 PM PDT 24 78028098 ps
T805 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3739922146 Mar 28 12:52:34 PM PDT 24 Mar 28 12:52:35 PM PDT 24 33318557 ps
T806 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2378211721 Mar 28 12:52:54 PM PDT 24 Mar 28 12:52:56 PM PDT 24 43679042 ps
T807 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3933793874 Mar 28 12:53:08 PM PDT 24 Mar 28 12:53:11 PM PDT 24 167856650 ps
T808 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2258803689 Mar 28 12:53:12 PM PDT 24 Mar 28 12:53:12 PM PDT 24 35355448 ps
T809 /workspace/coverage/cover_reg_top/21.gpio_intr_test.890797221 Mar 28 12:53:09 PM PDT 24 Mar 28 12:53:10 PM PDT 24 28709407 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2696984303 Mar 28 12:53:05 PM PDT 24 Mar 28 12:53:06 PM PDT 24 94647195 ps
T811 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1916706272 Mar 28 12:53:02 PM PDT 24 Mar 28 12:53:05 PM PDT 24 32144017 ps
T812 /workspace/coverage/cover_reg_top/0.gpio_intr_test.279699179 Mar 28 12:52:36 PM PDT 24 Mar 28 12:52:37 PM PDT 24 38844606 ps
T813 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3464746096 Mar 28 12:52:56 PM PDT 24 Mar 28 12:52:59 PM PDT 24 64078176 ps
T814 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2005681681 Mar 28 12:52:34 PM PDT 24 Mar 28 12:52:35 PM PDT 24 1047284985 ps
T815 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4222920836 Mar 28 12:52:34 PM PDT 24 Mar 28 12:52:35 PM PDT 24 141168540 ps
T816 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1293041788 Mar 28 12:53:02 PM PDT 24 Mar 28 12:53:05 PM PDT 24 20680718 ps
T817 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3325807168 Mar 28 12:53:11 PM PDT 24 Mar 28 12:53:12 PM PDT 24 38619366 ps
T818 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2611203844 Mar 28 12:52:31 PM PDT 24 Mar 28 12:52:32 PM PDT 24 37715716 ps
T819 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.327293343 Mar 28 12:52:32 PM PDT 24 Mar 28 12:52:32 PM PDT 24 16623115 ps
T820 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3224698939 Mar 28 12:52:54 PM PDT 24 Mar 28 12:52:56 PM PDT 24 179106953 ps
T821 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1611288225 Mar 28 12:53:05 PM PDT 24 Mar 28 12:53:06 PM PDT 24 133512278 ps
T822 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3792656359 Mar 28 12:52:36 PM PDT 24 Mar 28 12:52:37 PM PDT 24 62363825 ps
T823 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1621468632 Mar 28 12:52:50 PM PDT 24 Mar 28 12:52:50 PM PDT 24 18522483 ps
T96 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3149815549 Mar 28 12:52:45 PM PDT 24 Mar 28 12:52:45 PM PDT 24 15090622 ps
T824 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3575118500 Mar 28 12:53:05 PM PDT 24 Mar 28 12:53:06 PM PDT 24 68733970 ps
T825 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3478817592 Mar 28 12:52:36 PM PDT 24 Mar 28 12:52:37 PM PDT 24 16690290 ps
T826 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1130543794 Mar 28 12:53:14 PM PDT 24 Mar 28 12:53:15 PM PDT 24 22415238 ps
T827 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3778758826 Mar 28 12:52:46 PM PDT 24 Mar 28 12:52:47 PM PDT 24 31329235 ps
T828 /workspace/coverage/cover_reg_top/46.gpio_intr_test.352326411 Mar 28 12:53:06 PM PDT 24 Mar 28 12:53:08 PM PDT 24 36479843 ps
T829 /workspace/coverage/cover_reg_top/26.gpio_intr_test.558366060 Mar 28 12:53:15 PM PDT 24 Mar 28 12:53:15 PM PDT 24 29007704 ps
T830 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3412946071 Mar 28 12:53:10 PM PDT 24 Mar 28 12:53:10 PM PDT 24 24905063 ps
T831 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1700581123 Mar 28 12:53:06 PM PDT 24 Mar 28 12:53:08 PM PDT 24 28653084 ps
T832 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.157737937 Mar 28 12:52:36 PM PDT 24 Mar 28 12:52:38 PM PDT 24 296817218 ps
T833 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1017993216 Mar 28 12:52:35 PM PDT 24 Mar 28 12:52:37 PM PDT 24 245285187 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3165016183 Mar 28 12:53:02 PM PDT 24 Mar 28 12:53:05 PM PDT 24 72522878 ps
T835 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3148685671 Mar 28 12:52:47 PM PDT 24 Mar 28 12:52:48 PM PDT 24 113691389 ps
T836 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2013126446 Mar 28 12:52:55 PM PDT 24 Mar 28 12:52:57 PM PDT 24 33496237 ps
T837 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3169117550 Mar 28 12:53:09 PM PDT 24 Mar 28 12:53:10 PM PDT 24 31537836 ps
T838 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1245940161 Mar 28 12:52:47 PM PDT 24 Mar 28 12:52:47 PM PDT 24 15555097 ps
T97 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.763425101 Mar 28 12:52:53 PM PDT 24 Mar 28 12:52:54 PM PDT 24 18700193 ps
T839 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2899549330 Mar 28 12:52:50 PM PDT 24 Mar 28 12:52:51 PM PDT 24 73229463 ps
T98 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2756212934 Mar 28 12:52:36 PM PDT 24 Mar 28 12:52:36 PM PDT 24 25126689 ps
T840 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3675639890 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 29511144 ps
T841 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1339852919 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:01 PM PDT 24 57927280 ps
T842 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.365191438 Mar 28 12:49:15 PM PDT 24 Mar 28 12:49:17 PM PDT 24 68310113 ps
T843 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2538517202 Mar 28 12:49:15 PM PDT 24 Mar 28 12:49:16 PM PDT 24 183418090 ps
T844 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1568455265 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:03 PM PDT 24 36995637 ps
T845 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.317609332 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:17 PM PDT 24 427411696 ps
T846 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1368883935 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:20 PM PDT 24 46532054 ps
T847 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2122838443 Mar 28 12:49:23 PM PDT 24 Mar 28 12:49:24 PM PDT 24 68780309 ps
T848 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2938613209 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:18 PM PDT 24 215830276 ps
T849 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.782794116 Mar 28 12:49:22 PM PDT 24 Mar 28 12:49:23 PM PDT 24 47413228 ps
T850 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539288857 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:03 PM PDT 24 89666637 ps
T851 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4189054349 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:18 PM PDT 24 142741173 ps
T852 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.992767931 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 382063019 ps
T853 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2700523408 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:17 PM PDT 24 40019367 ps
T854 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3586430101 Mar 28 12:48:57 PM PDT 24 Mar 28 12:48:58 PM PDT 24 73849834 ps
T855 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1819124665 Mar 28 12:49:03 PM PDT 24 Mar 28 12:49:04 PM PDT 24 149894014 ps
T856 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.10731713 Mar 28 12:49:15 PM PDT 24 Mar 28 12:49:17 PM PDT 24 55647561 ps
T857 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3006486917 Mar 28 12:48:57 PM PDT 24 Mar 28 12:48:58 PM PDT 24 82105822 ps
T858 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1179655248 Mar 28 12:48:58 PM PDT 24 Mar 28 12:48:59 PM PDT 24 87718130 ps
T859 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3732512568 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:02 PM PDT 24 79655497 ps
T860 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1353174181 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:19 PM PDT 24 127547109 ps
T861 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2049413321 Mar 28 12:48:59 PM PDT 24 Mar 28 12:49:00 PM PDT 24 36812499 ps
T862 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2960311897 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:18 PM PDT 24 88553087 ps
T863 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2338754384 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 328729093 ps
T864 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4187169295 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 66559029 ps
T865 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1392446981 Mar 28 12:49:02 PM PDT 24 Mar 28 12:49:03 PM PDT 24 79611156 ps
T866 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2078785334 Mar 28 12:48:58 PM PDT 24 Mar 28 12:48:59 PM PDT 24 92467648 ps
T867 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1246087491 Mar 28 12:48:58 PM PDT 24 Mar 28 12:48:59 PM PDT 24 296037934 ps
T868 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3625528518 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:03 PM PDT 24 60207456 ps
T869 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1943227023 Mar 28 12:49:22 PM PDT 24 Mar 28 12:49:23 PM PDT 24 41853635 ps
T870 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.5625399 Mar 28 12:49:02 PM PDT 24 Mar 28 12:49:03 PM PDT 24 60106449 ps
T871 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3353623850 Mar 28 12:48:58 PM PDT 24 Mar 28 12:48:59 PM PDT 24 35787002 ps
T872 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1881210193 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:19 PM PDT 24 55644080 ps
T873 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3000118279 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 132272758 ps
T874 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4241230977 Mar 28 12:49:15 PM PDT 24 Mar 28 12:49:16 PM PDT 24 19109166 ps
T875 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1533644349 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 251581279 ps
T876 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1393259202 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 57785651 ps
T877 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1921693875 Mar 28 12:49:04 PM PDT 24 Mar 28 12:49:05 PM PDT 24 132413057 ps
T878 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2557542422 Mar 28 12:49:20 PM PDT 24 Mar 28 12:49:21 PM PDT 24 140405394 ps
T879 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.70419545 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:01 PM PDT 24 34981615 ps
T880 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999394854 Mar 28 12:48:59 PM PDT 24 Mar 28 12:49:00 PM PDT 24 186549337 ps
T881 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1749825369 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:01 PM PDT 24 157570500 ps
T882 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.545812475 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 26140583 ps
T883 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1803441276 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 179475040 ps
T884 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2643076506 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:17 PM PDT 24 65503376 ps
T885 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1389073250 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 103642325 ps
T886 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3605231953 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:03 PM PDT 24 288004205 ps
T887 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.772830333 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 66872045 ps
T888 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3932880834 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:17 PM PDT 24 318665525 ps
T889 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2835323552 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 573089660 ps
T890 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3927396652 Mar 28 12:49:23 PM PDT 24 Mar 28 12:49:24 PM PDT 24 130188310 ps
T891 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.867370333 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:02 PM PDT 24 52269367 ps
T892 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2975341391 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 37443163 ps
T893 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4198373595 Mar 28 12:49:02 PM PDT 24 Mar 28 12:49:03 PM PDT 24 133019325 ps
T894 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3837345678 Mar 28 12:49:03 PM PDT 24 Mar 28 12:49:04 PM PDT 24 136092381 ps
T895 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.975977900 Mar 28 12:49:06 PM PDT 24 Mar 28 12:49:07 PM PDT 24 36083642 ps
T896 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2404650621 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:01 PM PDT 24 207052283 ps
T897 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3706087739 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:18 PM PDT 24 360572843 ps
T898 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2001192706 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:19 PM PDT 24 96807261 ps
T899 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2117393561 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:18 PM PDT 24 46512477 ps
T900 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1548222999 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:18 PM PDT 24 56052795 ps
T901 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4021713788 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:17 PM PDT 24 37627032 ps
T902 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4000214082 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:17 PM PDT 24 30636091 ps
T903 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3947926895 Mar 28 12:49:13 PM PDT 24 Mar 28 12:49:14 PM PDT 24 243716448 ps
T904 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1551545821 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:19 PM PDT 24 253020530 ps
T905 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2896203090 Mar 28 12:49:03 PM PDT 24 Mar 28 12:49:05 PM PDT 24 231045325 ps
T906 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4218573699 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:17 PM PDT 24 79361095 ps
T907 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2880372356 Mar 28 12:49:20 PM PDT 24 Mar 28 12:49:21 PM PDT 24 295987965 ps
T908 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3616733235 Mar 28 12:49:02 PM PDT 24 Mar 28 12:49:04 PM PDT 24 114207043 ps
T909 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1613419527 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:01 PM PDT 24 25456085 ps
T910 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3877720874 Mar 28 12:49:05 PM PDT 24 Mar 28 12:49:06 PM PDT 24 47310888 ps
T911 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3105335679 Mar 28 12:49:02 PM PDT 24 Mar 28 12:49:04 PM PDT 24 461688567 ps
T912 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.989546620 Mar 28 12:48:58 PM PDT 24 Mar 28 12:48:59 PM PDT 24 169704706 ps
T913 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4097934405 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:21 PM PDT 24 267067509 ps
T914 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1277059672 Mar 28 12:49:22 PM PDT 24 Mar 28 12:49:23 PM PDT 24 264288491 ps
T915 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.460395174 Mar 28 12:49:06 PM PDT 24 Mar 28 12:49:07 PM PDT 24 56275384 ps
T916 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1210359843 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:01 PM PDT 24 75977385 ps
T917 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1018191341 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:18 PM PDT 24 150784642 ps
T918 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.855817098 Mar 28 12:49:20 PM PDT 24 Mar 28 12:49:21 PM PDT 24 61100630 ps
T919 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3103211544 Mar 28 12:49:14 PM PDT 24 Mar 28 12:49:15 PM PDT 24 83830494 ps
T920 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2122533844 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 64159872 ps
T921 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.379112357 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:02 PM PDT 24 110589525 ps
T922 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1711504369 Mar 28 12:48:59 PM PDT 24 Mar 28 12:49:01 PM PDT 24 39678003 ps
T923 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2458365615 Mar 28 12:49:03 PM PDT 24 Mar 28 12:49:04 PM PDT 24 139264078 ps
T924 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.463785504 Mar 28 12:48:59 PM PDT 24 Mar 28 12:49:00 PM PDT 24 56523131 ps
T925 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.814617228 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:02 PM PDT 24 92657089 ps
T926 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3166610201 Mar 28 12:49:03 PM PDT 24 Mar 28 12:49:05 PM PDT 24 195007427 ps
T927 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1377097591 Mar 28 12:49:14 PM PDT 24 Mar 28 12:49:15 PM PDT 24 378838767 ps
T928 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.590682085 Mar 28 12:49:15 PM PDT 24 Mar 28 12:49:16 PM PDT 24 88379185 ps
T929 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.264042322 Mar 28 12:48:59 PM PDT 24 Mar 28 12:49:00 PM PDT 24 67376658 ps
T930 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2754332053 Mar 28 12:49:00 PM PDT 24 Mar 28 12:49:02 PM PDT 24 60933906 ps
T931 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1580229065 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 56921038 ps
T932 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1579675563 Mar 28 12:48:57 PM PDT 24 Mar 28 12:48:58 PM PDT 24 121370441 ps
T933 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.435309048 Mar 28 12:49:02 PM PDT 24 Mar 28 12:49:04 PM PDT 24 507245077 ps
T934 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3900547308 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:03 PM PDT 24 276410474 ps
T935 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.218030388 Mar 28 12:49:04 PM PDT 24 Mar 28 12:49:06 PM PDT 24 739259838 ps
T936 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2441330185 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:19 PM PDT 24 23292416 ps
T937 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2774436385 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 58484910 ps
T938 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.44730477 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 161068541 ps
T939 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1548411454 Mar 28 12:49:01 PM PDT 24 Mar 28 12:49:02 PM PDT 24 138779395 ps

Test location /workspace/coverage/default/43.gpio_full_random.2180651918
Short name T34
Test name
Test status
Simulation time 276075810 ps
CPU time 1.1 seconds
Started Mar 28 02:30:31 PM PDT 24
Finished Mar 28 02:30:32 PM PDT 24
Peak memory 198040 kb
Host smart-a66c0884-87f7-4134-ba0b-e998af39a06a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180651918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2180651918
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1813545676
Short name T14
Test name
Test status
Simulation time 574658244 ps
CPU time 3.83 seconds
Started Mar 28 02:29:04 PM PDT 24
Finished Mar 28 02:29:08 PM PDT 24
Peak memory 198044 kb
Host smart-b04df954-c2e5-42fa-b2bd-e485655cc637
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813545676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1813545676
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3457630112
Short name T36
Test name
Test status
Simulation time 34256966941 ps
CPU time 245.14 seconds
Started Mar 28 02:26:17 PM PDT 24
Finished Mar 28 02:30:22 PM PDT 24
Peak memory 198292 kb
Host smart-b6b7b2ad-cc3f-45b0-a514-e6cc4efaeee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3457630112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3457630112
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3368002314
Short name T2
Test name
Test status
Simulation time 124682936194 ps
CPU time 218.47 seconds
Started Mar 28 02:29:01 PM PDT 24
Finished Mar 28 02:32:40 PM PDT 24
Peak memory 198248 kb
Host smart-6a57f2cb-95c4-4440-a7ed-dcafeb310eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368002314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3368002314
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1967180584
Short name T28
Test name
Test status
Simulation time 49352104 ps
CPU time 0.8 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:48 PM PDT 24
Peak memory 213768 kb
Host smart-006e8ba2-41c0-4084-90dc-94ffb0c10115
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967180584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1967180584
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2003096175
Short name T77
Test name
Test status
Simulation time 181962280032 ps
CPU time 1073 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:47:39 PM PDT 24
Peak memory 198244 kb
Host smart-2e89cb92-e562-4fa6-988c-1afb9a83c38c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2003096175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2003096175
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3797782801
Short name T50
Test name
Test status
Simulation time 421917602 ps
CPU time 1.44 seconds
Started Mar 28 12:52:53 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 197772 kb
Host smart-35c86156-f9ef-4973-ad5b-078ab3acf397
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797782801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3797782801
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2787128926
Short name T58
Test name
Test status
Simulation time 236641775 ps
CPU time 1.7 seconds
Started Mar 28 02:23:32 PM PDT 24
Finished Mar 28 02:23:34 PM PDT 24
Peak memory 196732 kb
Host smart-edcc931b-c7ae-4fbc-9e26-c7d5e7e12948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787128926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2787128926
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3164758516
Short name T44
Test name
Test status
Simulation time 12592943 ps
CPU time 0.55 seconds
Started Mar 28 02:26:29 PM PDT 24
Finished Mar 28 02:26:30 PM PDT 24
Peak memory 193980 kb
Host smart-348d8b04-b761-42e3-859a-2d50d69abcad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164758516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3164758516
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3066060948
Short name T84
Test name
Test status
Simulation time 86719315 ps
CPU time 0.67 seconds
Started Mar 28 12:52:29 PM PDT 24
Finished Mar 28 12:52:30 PM PDT 24
Peak memory 194400 kb
Host smart-b117f2f7-4757-4611-97ad-f8c768f2ef5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066060948 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3066060948
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.763425101
Short name T97
Test name
Test status
Simulation time 18700193 ps
CPU time 0.59 seconds
Started Mar 28 12:52:53 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 194372 kb
Host smart-6024c001-a248-4dd1-af3a-495e8738ff85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763425101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.763425101
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.200951356
Short name T48
Test name
Test status
Simulation time 193370987 ps
CPU time 1.48 seconds
Started Mar 28 12:52:47 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 197724 kb
Host smart-8c2bba71-c50a-4977-a943-743801708f3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200951356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.200951356
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.608906114
Short name T92
Test name
Test status
Simulation time 58737827 ps
CPU time 0.74 seconds
Started Mar 28 12:52:51 PM PDT 24
Finished Mar 28 12:52:53 PM PDT 24
Peak memory 196340 kb
Host smart-6647bd8e-9b1c-466b-a16e-39a31815fd4e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608906114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.608906114
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3673159892
Short name T779
Test name
Test status
Simulation time 395877515 ps
CPU time 2.47 seconds
Started Mar 28 12:52:29 PM PDT 24
Finished Mar 28 12:52:32 PM PDT 24
Peak memory 196564 kb
Host smart-a7f9db20-ea16-4c0f-a4ad-690902a70616
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673159892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3673159892
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1160340945
Short name T106
Test name
Test status
Simulation time 13923009 ps
CPU time 0.63 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 195088 kb
Host smart-b5eb5e78-0693-49a0-8371-680972bf6220
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160340945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1160340945
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3318782179
Short name T792
Test name
Test status
Simulation time 104740794 ps
CPU time 1.01 seconds
Started Mar 28 12:52:33 PM PDT 24
Finished Mar 28 12:52:34 PM PDT 24
Peak memory 197728 kb
Host smart-fe1d411f-38b0-4929-8630-be6dca0dab46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318782179 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3318782179
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3212282621
Short name T777
Test name
Test status
Simulation time 15330361 ps
CPU time 0.61 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:47 PM PDT 24
Peak memory 195144 kb
Host smart-57d2eee9-aff8-4620-a6c6-8d5a11b0f8b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212282621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3212282621
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.279699179
Short name T812
Test name
Test status
Simulation time 38844606 ps
CPU time 0.65 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 193324 kb
Host smart-0071a341-77f3-4095-9542-0173df372b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279699179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.279699179
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4078779209
Short name T799
Test name
Test status
Simulation time 52809753 ps
CPU time 2.67 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:52:33 PM PDT 24
Peak memory 197796 kb
Host smart-1e4d6a60-3093-4633-b840-eb73b1eecf27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078779209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4078779209
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.192985163
Short name T719
Test name
Test status
Simulation time 142483728 ps
CPU time 0.89 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:52:34 PM PDT 24
Peak memory 197024 kb
Host smart-90cc9215-d606-4b87-a18e-3a70077408d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192985163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.192985163
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1721077087
Short name T89
Test name
Test status
Simulation time 70421938 ps
CPU time 0.67 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:32 PM PDT 24
Peak memory 193928 kb
Host smart-3686797e-da04-4340-a753-852cd7f6325a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721077087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1721077087
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.157737937
Short name T832
Test name
Test status
Simulation time 296817218 ps
CPU time 2.38 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:38 PM PDT 24
Peak memory 197644 kb
Host smart-2fe7e59e-fa2d-4a7e-9196-23fb2a592c5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157737937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.157737937
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3478817592
Short name T825
Test name
Test status
Simulation time 16690290 ps
CPU time 0.64 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 194996 kb
Host smart-ba391f25-0bf7-40c0-bac5-4358f5c4224f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478817592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3478817592
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3792656359
Short name T822
Test name
Test status
Simulation time 62363825 ps
CPU time 0.93 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 197584 kb
Host smart-d7c0b958-6ac8-419b-9c36-5c195aaeecd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792656359 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3792656359
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.287258166
Short name T95
Test name
Test status
Simulation time 48393011 ps
CPU time 0.61 seconds
Started Mar 28 12:52:26 PM PDT 24
Finished Mar 28 12:52:27 PM PDT 24
Peak memory 193060 kb
Host smart-05b02480-8b86-4fca-bb9b-b466fe700b5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287258166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.287258166
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.696925495
Short name T757
Test name
Test status
Simulation time 16587198 ps
CPU time 0.58 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 194016 kb
Host smart-87878846-f964-4be0-a8c6-a3b697a09300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696925495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.696925495
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2423806720
Short name T794
Test name
Test status
Simulation time 134504746 ps
CPU time 0.84 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:52:31 PM PDT 24
Peak memory 196164 kb
Host smart-49898b56-e8b7-4637-b478-6d8de74e7f5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423806720 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2423806720
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4288207475
Short name T715
Test name
Test status
Simulation time 510002560 ps
CPU time 2.4 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:34 PM PDT 24
Peak memory 197720 kb
Host smart-d1957254-0b8b-449a-a9ba-b3a5906d9b1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288207475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.4288207475
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2005681681
Short name T814
Test name
Test status
Simulation time 1047284985 ps
CPU time 1.42 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 197652 kb
Host smart-dfa8bf28-3f00-4e71-9987-45bfeb32188c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005681681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2005681681
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2690001664
Short name T800
Test name
Test status
Simulation time 65472798 ps
CPU time 1.61 seconds
Started Mar 28 12:52:53 PM PDT 24
Finished Mar 28 12:52:55 PM PDT 24
Peak memory 197736 kb
Host smart-fecfd2af-455f-47f9-b556-cd806c9e06c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690001664 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2690001664
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.894435155
Short name T781
Test name
Test status
Simulation time 36373017 ps
CPU time 0.54 seconds
Started Mar 28 12:52:59 PM PDT 24
Finished Mar 28 12:53:01 PM PDT 24
Peak memory 193284 kb
Host smart-0bdeec95-356d-490f-af38-febc52a8f84f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894435155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.894435155
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1621468632
Short name T823
Test name
Test status
Simulation time 18522483 ps
CPU time 0.62 seconds
Started Mar 28 12:52:50 PM PDT 24
Finished Mar 28 12:52:50 PM PDT 24
Peak memory 194232 kb
Host smart-4b5e4fda-1be3-4f14-8e88-15db63180f90
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621468632 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1621468632
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4240629558
Short name T762
Test name
Test status
Simulation time 85233847 ps
CPU time 2.05 seconds
Started Mar 28 12:52:53 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 197784 kb
Host smart-9c0023c7-bb8f-43f4-865a-d4031f81d2a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240629558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4240629558
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2378211721
Short name T806
Test name
Test status
Simulation time 43679042 ps
CPU time 1.02 seconds
Started Mar 28 12:52:54 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 197740 kb
Host smart-de7b3c57-e1d3-47d0-a3ee-d06be0b6d66e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378211721 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2378211721
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.992728346
Short name T764
Test name
Test status
Simulation time 58498672 ps
CPU time 0.63 seconds
Started Mar 28 12:53:00 PM PDT 24
Finished Mar 28 12:53:04 PM PDT 24
Peak memory 195004 kb
Host smart-d5cac805-088c-4ac6-9eac-6ec32a87446a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992728346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.992728346
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2805067145
Short name T786
Test name
Test status
Simulation time 25951195 ps
CPU time 0.59 seconds
Started Mar 28 12:52:54 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 193344 kb
Host smart-e0001f5f-372f-47d6-878e-2d0e00df0404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805067145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2805067145
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3432870636
Short name T85
Test name
Test status
Simulation time 54928055 ps
CPU time 0.72 seconds
Started Mar 28 12:52:50 PM PDT 24
Finished Mar 28 12:52:50 PM PDT 24
Peak memory 195940 kb
Host smart-b860cadb-96df-47c2-a52d-a568cf93815e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432870636 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3432870636
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2703605137
Short name T784
Test name
Test status
Simulation time 905638125 ps
CPU time 2.54 seconds
Started Mar 28 12:52:58 PM PDT 24
Finished Mar 28 12:53:02 PM PDT 24
Peak memory 197796 kb
Host smart-55112105-b0b8-426e-ba51-29f617da07aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703605137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2703605137
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.556516839
Short name T39
Test name
Test status
Simulation time 46885290 ps
CPU time 0.87 seconds
Started Mar 28 12:52:55 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 196964 kb
Host smart-3b3863b0-c2b5-4760-a68e-fbbc4320a3a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556516839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.556516839
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.512660406
Short name T759
Test name
Test status
Simulation time 36617742 ps
CPU time 0.96 seconds
Started Mar 28 12:52:55 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 197656 kb
Host smart-e1e4c6ba-6174-4924-aebe-6eccd364f6ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512660406 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.512660406
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1357038130
Short name T741
Test name
Test status
Simulation time 32413626 ps
CPU time 0.61 seconds
Started Mar 28 12:52:55 PM PDT 24
Finished Mar 28 12:52:57 PM PDT 24
Peak memory 195128 kb
Host smart-04fd17a7-85da-43ff-9349-616a101c5973
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357038130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1357038130
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2261570668
Short name T727
Test name
Test status
Simulation time 14939564 ps
CPU time 0.6 seconds
Started Mar 28 12:52:56 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 194000 kb
Host smart-3fefc874-a2f8-47f4-883c-8f823163fa82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261570668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2261570668
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4086903057
Short name T104
Test name
Test status
Simulation time 46386005 ps
CPU time 0.62 seconds
Started Mar 28 12:52:53 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 194528 kb
Host smart-8757b0a4-e80d-42fb-8735-4b85753e82aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086903057 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4086903057
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3024865188
Short name T712
Test name
Test status
Simulation time 475282904 ps
CPU time 2.37 seconds
Started Mar 28 12:52:52 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 197788 kb
Host smart-fa0ed992-d9b4-487f-9e63-ff6e4d736de9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024865188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3024865188
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3224698939
Short name T820
Test name
Test status
Simulation time 179106953 ps
CPU time 0.9 seconds
Started Mar 28 12:52:54 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 197620 kb
Host smart-db487918-7d8b-4200-bb0c-46243fe32277
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224698939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3224698939
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1232716312
Short name T742
Test name
Test status
Simulation time 43271219 ps
CPU time 1.44 seconds
Started Mar 28 12:52:54 PM PDT 24
Finished Mar 28 12:52:57 PM PDT 24
Peak memory 197704 kb
Host smart-6cc76ae1-6afa-4a09-aba9-8eddf634e72b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232716312 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1232716312
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1742926584
Short name T791
Test name
Test status
Simulation time 18241872 ps
CPU time 0.62 seconds
Started Mar 28 12:53:00 PM PDT 24
Finished Mar 28 12:53:04 PM PDT 24
Peak memory 195096 kb
Host smart-d38847e2-6674-4a65-abbb-7ab6f613df91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742926584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1742926584
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1439677231
Short name T717
Test name
Test status
Simulation time 14245045 ps
CPU time 0.57 seconds
Started Mar 28 12:52:54 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 193436 kb
Host smart-e9b8fd6b-5555-42ec-9934-0722f70e6cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439677231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1439677231
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3422712785
Short name T100
Test name
Test status
Simulation time 33710420 ps
CPU time 0.87 seconds
Started Mar 28 12:53:02 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 195908 kb
Host smart-1b5f2124-5109-49c5-b106-165fd96c302a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422712785 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3422712785
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3464746096
Short name T813
Test name
Test status
Simulation time 64078176 ps
CPU time 1.7 seconds
Started Mar 28 12:52:56 PM PDT 24
Finished Mar 28 12:52:59 PM PDT 24
Peak memory 197772 kb
Host smart-63a2afb7-d789-4da4-9b72-d75efc86fa85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464746096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3464746096
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1611288225
Short name T821
Test name
Test status
Simulation time 133512278 ps
CPU time 0.86 seconds
Started Mar 28 12:53:05 PM PDT 24
Finished Mar 28 12:53:06 PM PDT 24
Peak memory 197268 kb
Host smart-f5c6d7c0-36c7-4262-91e4-f44568870131
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611288225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1611288225
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.42088376
Short name T713
Test name
Test status
Simulation time 86455846 ps
CPU time 0.77 seconds
Started Mar 28 12:53:00 PM PDT 24
Finished Mar 28 12:53:04 PM PDT 24
Peak memory 197524 kb
Host smart-3c16bb89-31eb-4ec6-b852-d33ad685bc37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42088376 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.42088376
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1527987761
Short name T94
Test name
Test status
Simulation time 13924719 ps
CPU time 0.58 seconds
Started Mar 28 12:52:55 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 194228 kb
Host smart-0e4e4585-7a4d-48fe-8ab7-67425e1567d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527987761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1527987761
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4015675047
Short name T803
Test name
Test status
Simulation time 46042689 ps
CPU time 0.56 seconds
Started Mar 28 12:52:48 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 194056 kb
Host smart-d8fd777b-7ea3-4607-b9ab-36b9785d06fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015675047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4015675047
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3176216950
Short name T101
Test name
Test status
Simulation time 43826178 ps
CPU time 0.87 seconds
Started Mar 28 12:53:02 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 197552 kb
Host smart-e543623d-9cc7-41ba-a583-01a8560b4cdf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176216950 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3176216950
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.168913424
Short name T751
Test name
Test status
Simulation time 55518725 ps
CPU time 2.61 seconds
Started Mar 28 12:52:50 PM PDT 24
Finished Mar 28 12:52:52 PM PDT 24
Peak memory 197816 kb
Host smart-828fe2e2-2f6e-4b27-9551-d2414277597a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168913424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.168913424
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4159221998
Short name T52
Test name
Test status
Simulation time 42483225 ps
CPU time 0.83 seconds
Started Mar 28 12:52:57 PM PDT 24
Finished Mar 28 12:52:59 PM PDT 24
Peak memory 196664 kb
Host smart-0601d39d-aecd-43dd-8e6d-d50ef86d5cff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159221998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4159221998
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2755415706
Short name T752
Test name
Test status
Simulation time 49391192 ps
CPU time 0.82 seconds
Started Mar 28 12:52:57 PM PDT 24
Finished Mar 28 12:52:59 PM PDT 24
Peak memory 197648 kb
Host smart-edbb1dee-bcf7-4807-a2be-a273b94cc557
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755415706 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2755415706
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.691087919
Short name T90
Test name
Test status
Simulation time 34579302 ps
CPU time 0.63 seconds
Started Mar 28 12:52:55 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 195252 kb
Host smart-ea2487b6-481a-4372-afd9-4bf176bf17eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691087919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.691087919
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3530081506
Short name T771
Test name
Test status
Simulation time 42251406 ps
CPU time 0.6 seconds
Started Mar 28 12:52:56 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 193428 kb
Host smart-9ff56fdb-1fa9-4a13-9c57-397b435c1834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530081506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3530081506
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2898194686
Short name T755
Test name
Test status
Simulation time 40815249 ps
CPU time 0.72 seconds
Started Mar 28 12:52:52 PM PDT 24
Finished Mar 28 12:52:53 PM PDT 24
Peak memory 194708 kb
Host smart-05923b37-7ac4-408a-baa2-231464e9ceaa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898194686 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2898194686
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.728256448
Short name T746
Test name
Test status
Simulation time 113801132 ps
CPU time 1.59 seconds
Started Mar 28 12:52:50 PM PDT 24
Finished Mar 28 12:52:52 PM PDT 24
Peak memory 197800 kb
Host smart-243d48e4-14cb-47ab-9a77-012975daeaff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728256448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.728256448
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3303059166
Short name T41
Test name
Test status
Simulation time 104438948 ps
CPU time 1.09 seconds
Started Mar 28 12:53:01 PM PDT 24
Finished Mar 28 12:53:04 PM PDT 24
Peak memory 197724 kb
Host smart-6d6c06d9-bae1-443b-8d18-0fc13ff8b126
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303059166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3303059166
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2013126446
Short name T836
Test name
Test status
Simulation time 33496237 ps
CPU time 0.74 seconds
Started Mar 28 12:52:55 PM PDT 24
Finished Mar 28 12:52:57 PM PDT 24
Peak memory 197664 kb
Host smart-bd8a8ce0-662a-4360-b51c-3e61e2fd1d79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013126446 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2013126446
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1141092602
Short name T793
Test name
Test status
Simulation time 39207958 ps
CPU time 0.64 seconds
Started Mar 28 12:52:50 PM PDT 24
Finished Mar 28 12:52:51 PM PDT 24
Peak memory 195308 kb
Host smart-7207bbad-0efd-4fa5-9a8f-0b3bea482efc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141092602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1141092602
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3412946071
Short name T830
Test name
Test status
Simulation time 24905063 ps
CPU time 0.65 seconds
Started Mar 28 12:53:10 PM PDT 24
Finished Mar 28 12:53:10 PM PDT 24
Peak memory 193408 kb
Host smart-657d64c9-064f-4c76-95f8-9d96fa82592e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412946071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3412946071
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3165016183
Short name T834
Test name
Test status
Simulation time 72522878 ps
CPU time 0.73 seconds
Started Mar 28 12:53:02 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 194468 kb
Host smart-f0277d60-8985-4fb2-bda8-c5c0881fd027
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165016183 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3165016183
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.862017162
Short name T716
Test name
Test status
Simulation time 109277733 ps
CPU time 2.86 seconds
Started Mar 28 12:53:01 PM PDT 24
Finished Mar 28 12:53:07 PM PDT 24
Peak memory 197792 kb
Host smart-ea261220-fc71-4a1e-ab98-3323ca37375b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862017162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.862017162
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2899549330
Short name T839
Test name
Test status
Simulation time 73229463 ps
CPU time 1.12 seconds
Started Mar 28 12:52:50 PM PDT 24
Finished Mar 28 12:52:51 PM PDT 24
Peak memory 197792 kb
Host smart-8800e432-2706-4a68-bbcf-ec7b81117712
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899549330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2899549330
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1700581123
Short name T831
Test name
Test status
Simulation time 28653084 ps
CPU time 0.93 seconds
Started Mar 28 12:53:06 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 197584 kb
Host smart-23a54fa9-4649-4ca4-9ba6-6039da18a93d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700581123 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1700581123
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.881333154
Short name T736
Test name
Test status
Simulation time 13757079 ps
CPU time 0.6 seconds
Started Mar 28 12:53:06 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 194540 kb
Host smart-d3fc787c-9bcc-4ec9-a564-3b2a4cc48d53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881333154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.881333154
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3575118500
Short name T824
Test name
Test status
Simulation time 68733970 ps
CPU time 0.64 seconds
Started Mar 28 12:53:05 PM PDT 24
Finished Mar 28 12:53:06 PM PDT 24
Peak memory 194004 kb
Host smart-b83bb6d6-2ebe-4ddb-99d8-f11282a31829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575118500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3575118500
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2026686971
Short name T753
Test name
Test status
Simulation time 40037460 ps
CPU time 0.88 seconds
Started Mar 28 12:53:05 PM PDT 24
Finished Mar 28 12:53:06 PM PDT 24
Peak memory 196036 kb
Host smart-ff91f243-e635-4f24-9a0d-212a724f497c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026686971 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2026686971
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1237428679
Short name T798
Test name
Test status
Simulation time 167442748 ps
CPU time 3.48 seconds
Started Mar 28 12:53:11 PM PDT 24
Finished Mar 28 12:53:15 PM PDT 24
Peak memory 197756 kb
Host smart-6dc3f51e-2d77-4713-abdd-9601392d5536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237428679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1237428679
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4025948285
Short name T49
Test name
Test status
Simulation time 436329015 ps
CPU time 1.38 seconds
Started Mar 28 12:53:13 PM PDT 24
Finished Mar 28 12:53:15 PM PDT 24
Peak memory 197720 kb
Host smart-3a9d7874-3a9f-418a-9105-fb04220d6845
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025948285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.4025948285
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2043913079
Short name T722
Test name
Test status
Simulation time 112642947 ps
CPU time 0.75 seconds
Started Mar 28 12:53:06 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 197488 kb
Host smart-1bb0ebc5-ca8d-4bd1-800f-a0e0e6a264ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043913079 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2043913079
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2115965890
Short name T802
Test name
Test status
Simulation time 37915201 ps
CPU time 0.59 seconds
Started Mar 28 12:53:11 PM PDT 24
Finished Mar 28 12:53:12 PM PDT 24
Peak memory 194404 kb
Host smart-c73555fd-23c2-4167-9a0f-7d0ea19d3da9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115965890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2115965890
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.568163528
Short name T735
Test name
Test status
Simulation time 13559020 ps
CPU time 0.64 seconds
Started Mar 28 12:53:10 PM PDT 24
Finished Mar 28 12:53:11 PM PDT 24
Peak memory 193356 kb
Host smart-824f4a25-b4c0-4f1a-b725-7666b19e41f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568163528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.568163528
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4114519353
Short name T102
Test name
Test status
Simulation time 36450764 ps
CPU time 0.82 seconds
Started Mar 28 12:53:02 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 196016 kb
Host smart-deca5543-aa62-4bb1-97d0-d58c04703aba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114519353 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4114519353
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2696984303
Short name T810
Test name
Test status
Simulation time 94647195 ps
CPU time 1.16 seconds
Started Mar 28 12:53:05 PM PDT 24
Finished Mar 28 12:53:06 PM PDT 24
Peak memory 197604 kb
Host smart-e974afc6-4e1c-4473-a426-f40d9d9e77ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696984303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2696984303
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.138972869
Short name T769
Test name
Test status
Simulation time 158073012 ps
CPU time 1.11 seconds
Started Mar 28 12:53:13 PM PDT 24
Finished Mar 28 12:53:14 PM PDT 24
Peak memory 197692 kb
Host smart-058a5aeb-da61-4e98-9a8a-520d6b886bbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138972869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.138972869
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1391954224
Short name T723
Test name
Test status
Simulation time 22045489 ps
CPU time 0.69 seconds
Started Mar 28 12:53:03 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 197700 kb
Host smart-2889e038-dbfc-433a-973f-ac9534926b73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391954224 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1391954224
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3005094742
Short name T747
Test name
Test status
Simulation time 51036794 ps
CPU time 0.63 seconds
Started Mar 28 12:53:04 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 195132 kb
Host smart-9be7b722-b7fc-4851-b115-be68e7d507f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005094742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3005094742
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.969540023
Short name T745
Test name
Test status
Simulation time 41016694 ps
CPU time 0.64 seconds
Started Mar 28 12:53:11 PM PDT 24
Finished Mar 28 12:53:12 PM PDT 24
Peak memory 193532 kb
Host smart-b131f339-dc94-4081-a582-4b7bf2e74ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969540023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.969540023
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3908473472
Short name T749
Test name
Test status
Simulation time 53659216 ps
CPU time 0.76 seconds
Started Mar 28 12:53:03 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 195996 kb
Host smart-baa74f37-c875-4128-a269-03b809fe11d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908473472 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3908473472
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3933793874
Short name T807
Test name
Test status
Simulation time 167856650 ps
CPU time 3.07 seconds
Started Mar 28 12:53:08 PM PDT 24
Finished Mar 28 12:53:11 PM PDT 24
Peak memory 197700 kb
Host smart-c8bcfb50-d865-4b81-b23c-95086b6e66ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933793874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3933793874
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.887492220
Short name T40
Test name
Test status
Simulation time 149210589 ps
CPU time 0.89 seconds
Started Mar 28 12:53:10 PM PDT 24
Finished Mar 28 12:53:11 PM PDT 24
Peak memory 196660 kb
Host smart-f864d58c-0d43-41d3-90c4-1bb2af44b3e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887492220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.887492220
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4222920836
Short name T815
Test name
Test status
Simulation time 141168540 ps
CPU time 0.63 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 194056 kb
Host smart-020e518e-5344-4e05-83d0-23f8467e6437
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222920836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4222920836
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2237185310
Short name T93
Test name
Test status
Simulation time 1335976551 ps
CPU time 3.31 seconds
Started Mar 28 12:52:43 PM PDT 24
Finished Mar 28 12:52:47 PM PDT 24
Peak memory 197768 kb
Host smart-007f4d7d-eec7-49f3-ac54-14edc57bf799
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237185310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2237185310
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.327293343
Short name T819
Test name
Test status
Simulation time 16623115 ps
CPU time 0.64 seconds
Started Mar 28 12:52:32 PM PDT 24
Finished Mar 28 12:52:32 PM PDT 24
Peak memory 194808 kb
Host smart-e83b41c5-2d43-4d32-8468-45e5e694b4d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327293343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.327293343
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2611203844
Short name T818
Test name
Test status
Simulation time 37715716 ps
CPU time 0.91 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:32 PM PDT 24
Peak memory 197724 kb
Host smart-5ecfc1d6-a52e-47f3-bba1-f9f0b7ea4549
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611203844 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2611203844
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1916316934
Short name T782
Test name
Test status
Simulation time 30952643 ps
CPU time 0.6 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 192908 kb
Host smart-1d83d1fd-a28d-4cbb-b82e-383346bd384f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916316934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1916316934
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3104365762
Short name T711
Test name
Test status
Simulation time 24173500 ps
CPU time 0.61 seconds
Started Mar 28 12:52:38 PM PDT 24
Finished Mar 28 12:52:39 PM PDT 24
Peak memory 193496 kb
Host smart-c10f58e5-7f30-4af5-94a9-4588f4803a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104365762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3104365762
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3739922146
Short name T805
Test name
Test status
Simulation time 33318557 ps
CPU time 0.82 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 195968 kb
Host smart-42b6dc3d-9af0-4e1f-b57b-2366cd4145ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739922146 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3739922146
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.390896760
Short name T797
Test name
Test status
Simulation time 57960112 ps
CPU time 1.28 seconds
Started Mar 28 12:52:33 PM PDT 24
Finished Mar 28 12:52:34 PM PDT 24
Peak memory 197812 kb
Host smart-274a0c59-8f61-45b0-99ab-4cad51fef457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390896760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.390896760
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.976686841
Short name T783
Test name
Test status
Simulation time 314778697 ps
CPU time 1.15 seconds
Started Mar 28 12:52:32 PM PDT 24
Finished Mar 28 12:52:33 PM PDT 24
Peak memory 197772 kb
Host smart-e9562eae-d753-448f-97a5-76fda28dfa42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976686841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.976686841
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3325807168
Short name T817
Test name
Test status
Simulation time 38619366 ps
CPU time 0.62 seconds
Started Mar 28 12:53:11 PM PDT 24
Finished Mar 28 12:53:12 PM PDT 24
Peak memory 193556 kb
Host smart-d5d80135-2402-4c88-a80e-423ca3908c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325807168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3325807168
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.890797221
Short name T809
Test name
Test status
Simulation time 28709407 ps
CPU time 0.64 seconds
Started Mar 28 12:53:09 PM PDT 24
Finished Mar 28 12:53:10 PM PDT 24
Peak memory 193448 kb
Host smart-9c0fb374-0cc7-4173-94fc-a57d35f2d906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890797221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.890797221
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2993930502
Short name T728
Test name
Test status
Simulation time 48171978 ps
CPU time 0.62 seconds
Started Mar 28 12:53:12 PM PDT 24
Finished Mar 28 12:53:12 PM PDT 24
Peak memory 193504 kb
Host smart-26658512-c720-4efe-810b-efff095cafbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993930502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2993930502
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3904164528
Short name T770
Test name
Test status
Simulation time 34143606 ps
CPU time 0.58 seconds
Started Mar 28 12:53:09 PM PDT 24
Finished Mar 28 12:53:10 PM PDT 24
Peak memory 193444 kb
Host smart-2bdfb51f-a38f-49bd-aee2-b4849a2aa5dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904164528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3904164528
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3559218397
Short name T760
Test name
Test status
Simulation time 11898013 ps
CPU time 0.63 seconds
Started Mar 28 12:53:05 PM PDT 24
Finished Mar 28 12:53:06 PM PDT 24
Peak memory 194056 kb
Host smart-ac3eb931-8122-47dd-97a4-48b1fbba1074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559218397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3559218397
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3906912326
Short name T788
Test name
Test status
Simulation time 94569909 ps
CPU time 0.59 seconds
Started Mar 28 12:53:13 PM PDT 24
Finished Mar 28 12:53:14 PM PDT 24
Peak memory 193400 kb
Host smart-0d0043f6-12c3-4aeb-b138-c38a58e2d2ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906912326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3906912326
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.558366060
Short name T829
Test name
Test status
Simulation time 29007704 ps
CPU time 0.63 seconds
Started Mar 28 12:53:15 PM PDT 24
Finished Mar 28 12:53:15 PM PDT 24
Peak memory 194024 kb
Host smart-89bf40e5-6cbc-4c21-9064-25f4342e5a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558366060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.558366060
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2129940886
Short name T774
Test name
Test status
Simulation time 11814432 ps
CPU time 0.62 seconds
Started Mar 28 12:53:10 PM PDT 24
Finished Mar 28 12:53:11 PM PDT 24
Peak memory 194000 kb
Host smart-12a7ba60-e19b-4887-807e-2a57c3120259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129940886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2129940886
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1293041788
Short name T816
Test name
Test status
Simulation time 20680718 ps
CPU time 0.57 seconds
Started Mar 28 12:53:02 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 193296 kb
Host smart-af2d1656-3984-4cf9-98ca-13f60421ab2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293041788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1293041788
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3169117550
Short name T837
Test name
Test status
Simulation time 31537836 ps
CPU time 0.6 seconds
Started Mar 28 12:53:09 PM PDT 24
Finished Mar 28 12:53:10 PM PDT 24
Peak memory 193444 kb
Host smart-6588e412-0604-4665-bc52-e6f35e412f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169117550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3169117550
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1195922460
Short name T88
Test name
Test status
Simulation time 48182379 ps
CPU time 0.84 seconds
Started Mar 28 12:52:38 PM PDT 24
Finished Mar 28 12:52:39 PM PDT 24
Peak memory 196200 kb
Host smart-3d092c76-51c1-4374-b818-311734dc51ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195922460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1195922460
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4185187462
Short name T780
Test name
Test status
Simulation time 114192357 ps
CPU time 1.61 seconds
Started Mar 28 12:53:00 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 197692 kb
Host smart-cf12ea6e-1c70-425d-a4d3-98e36fb5c2c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185187462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4185187462
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1130543794
Short name T826
Test name
Test status
Simulation time 22415238 ps
CPU time 0.66 seconds
Started Mar 28 12:53:14 PM PDT 24
Finished Mar 28 12:53:15 PM PDT 24
Peak memory 194404 kb
Host smart-8dd20c65-5e84-4b07-a0c0-1bc1a947d660
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130543794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1130543794
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1890994030
Short name T724
Test name
Test status
Simulation time 43997751 ps
CPU time 0.79 seconds
Started Mar 28 12:53:16 PM PDT 24
Finished Mar 28 12:53:17 PM PDT 24
Peak memory 197652 kb
Host smart-1865dc2f-5c50-4973-9e77-8d0cecd9ca69
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890994030 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1890994030
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2842242878
Short name T91
Test name
Test status
Simulation time 35782066 ps
CPU time 0.58 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:45 PM PDT 24
Peak memory 194936 kb
Host smart-adbccce7-c8c5-4b20-b5b9-1cadc36aa4d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842242878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2842242878
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3656054158
Short name T766
Test name
Test status
Simulation time 38169081 ps
CPU time 0.61 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 193424 kb
Host smart-6947664a-1c3d-447e-be83-2b109d2744b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656054158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3656054158
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3939139223
Short name T765
Test name
Test status
Simulation time 22808435 ps
CPU time 0.64 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:45 PM PDT 24
Peak memory 194792 kb
Host smart-15a689ea-f95c-4a29-99f9-785447439646
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939139223 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3939139223
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1523217355
Short name T748
Test name
Test status
Simulation time 115400272 ps
CPU time 1.31 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 197744 kb
Host smart-cae4e13a-87a8-4fbe-8c6c-93a38d9a916e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523217355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1523217355
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.824038915
Short name T789
Test name
Test status
Simulation time 215527044 ps
CPU time 1.5 seconds
Started Mar 28 12:52:47 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 197704 kb
Host smart-7a67102f-f1e6-4e67-ac1b-e77f479c4202
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824038915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.824038915
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3940107026
Short name T726
Test name
Test status
Simulation time 19206540 ps
CPU time 0.63 seconds
Started Mar 28 12:53:10 PM PDT 24
Finished Mar 28 12:53:11 PM PDT 24
Peak memory 193412 kb
Host smart-d5f27ecf-6088-4b8a-90a5-e3d0849a0649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940107026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3940107026
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1614771313
Short name T796
Test name
Test status
Simulation time 18404606 ps
CPU time 0.66 seconds
Started Mar 28 12:53:10 PM PDT 24
Finished Mar 28 12:53:11 PM PDT 24
Peak memory 194132 kb
Host smart-9179d46f-9665-46b6-a9e2-0d7ffb034f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614771313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1614771313
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1916706272
Short name T811
Test name
Test status
Simulation time 32144017 ps
CPU time 0.56 seconds
Started Mar 28 12:53:02 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 193444 kb
Host smart-aa8a79a6-e41a-4f72-b987-0475bcccba41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916706272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1916706272
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3535759562
Short name T743
Test name
Test status
Simulation time 124016852 ps
CPU time 0.69 seconds
Started Mar 28 12:53:09 PM PDT 24
Finished Mar 28 12:53:10 PM PDT 24
Peak memory 194064 kb
Host smart-3ea1febe-5469-44a0-86f6-b7c9d018c3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535759562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3535759562
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1569933502
Short name T725
Test name
Test status
Simulation time 40167471 ps
CPU time 0.64 seconds
Started Mar 28 12:53:10 PM PDT 24
Finished Mar 28 12:53:10 PM PDT 24
Peak memory 193472 kb
Host smart-9a769a0b-1a77-4937-bc96-3cdb38a34185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569933502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1569933502
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2258803689
Short name T808
Test name
Test status
Simulation time 35355448 ps
CPU time 0.64 seconds
Started Mar 28 12:53:12 PM PDT 24
Finished Mar 28 12:53:12 PM PDT 24
Peak memory 194128 kb
Host smart-a1b77996-6b73-4137-95ac-826958aca02b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258803689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2258803689
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.647828497
Short name T795
Test name
Test status
Simulation time 173823467 ps
CPU time 0.58 seconds
Started Mar 28 12:53:07 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 194096 kb
Host smart-8b7a1692-0d1d-445a-9f4f-36460ea12d3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647828497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.647828497
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.147877642
Short name T731
Test name
Test status
Simulation time 14305198 ps
CPU time 0.63 seconds
Started Mar 28 12:53:08 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 193452 kb
Host smart-00b39b55-d4f2-43ee-ab71-be94da7be7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147877642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.147877642
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1517055473
Short name T801
Test name
Test status
Simulation time 75603336 ps
CPU time 0.59 seconds
Started Mar 28 12:53:13 PM PDT 24
Finished Mar 28 12:53:14 PM PDT 24
Peak memory 193364 kb
Host smart-aa4063ed-dd91-4156-b0fd-458259a9cbf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517055473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1517055473
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1528134363
Short name T744
Test name
Test status
Simulation time 42660097 ps
CPU time 0.59 seconds
Started Mar 28 12:53:03 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 193392 kb
Host smart-fae5e574-9fe7-464f-8d7d-30a69d0dd0f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528134363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1528134363
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2353401111
Short name T763
Test name
Test status
Simulation time 64131392 ps
CPU time 0.86 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:45 PM PDT 24
Peak memory 196556 kb
Host smart-74cb7616-c9cb-40fa-ac9c-4efd988a41cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353401111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2353401111
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3354899857
Short name T107
Test name
Test status
Simulation time 34789270 ps
CPU time 1.35 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:38 PM PDT 24
Peak memory 196476 kb
Host smart-a0a9ae58-b1dc-411b-bf4d-441e454147e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354899857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3354899857
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3999708776
Short name T83
Test name
Test status
Simulation time 36804929 ps
CPU time 0.6 seconds
Started Mar 28 12:52:45 PM PDT 24
Finished Mar 28 12:52:46 PM PDT 24
Peak memory 194048 kb
Host smart-ffe8cd5e-9865-4fbb-b45b-aaa143c3bcd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999708776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3999708776
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2472992335
Short name T718
Test name
Test status
Simulation time 33915831 ps
CPU time 0.91 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 197608 kb
Host smart-6a5c6b4d-8029-4501-8e00-38cf529116e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472992335 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2472992335
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2756212934
Short name T98
Test name
Test status
Simulation time 25126689 ps
CPU time 0.61 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:36 PM PDT 24
Peak memory 194148 kb
Host smart-0d240c40-a160-49b2-a932-2b84eb676498
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756212934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2756212934
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4195380405
Short name T768
Test name
Test status
Simulation time 32669253 ps
CPU time 0.6 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:36 PM PDT 24
Peak memory 193340 kb
Host smart-558fb854-9239-438e-8bb0-dd00cb6a804e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195380405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4195380405
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.627181201
Short name T756
Test name
Test status
Simulation time 13250238 ps
CPU time 0.65 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 195200 kb
Host smart-4d86198b-49a6-4261-8e53-838c246dc936
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627181201 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.627181201
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.525323966
Short name T754
Test name
Test status
Simulation time 111544608 ps
CPU time 2.43 seconds
Started Mar 28 12:52:45 PM PDT 24
Finished Mar 28 12:52:47 PM PDT 24
Peak memory 197712 kb
Host smart-40bc1174-b8be-4e2e-b2f9-ad795c5e2a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525323966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.525323966
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1017993216
Short name T833
Test name
Test status
Simulation time 245285187 ps
CPU time 1.5 seconds
Started Mar 28 12:52:35 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 197780 kb
Host smart-659c4be7-f8bf-4ff9-9e89-3078962470b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017993216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1017993216
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.666853120
Short name T776
Test name
Test status
Simulation time 92774880 ps
CPU time 0.58 seconds
Started Mar 28 12:53:13 PM PDT 24
Finished Mar 28 12:53:14 PM PDT 24
Peak memory 193376 kb
Host smart-e7a33926-f3ba-4ba6-95a2-f9a35b4243e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666853120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.666853120
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2976470830
Short name T732
Test name
Test status
Simulation time 53462201 ps
CPU time 0.66 seconds
Started Mar 28 12:53:09 PM PDT 24
Finished Mar 28 12:53:09 PM PDT 24
Peak memory 193536 kb
Host smart-452a4f3b-e1da-43a7-8e4f-f111002455ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976470830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2976470830
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3400238897
Short name T740
Test name
Test status
Simulation time 18800242 ps
CPU time 0.64 seconds
Started Mar 28 12:53:06 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 194096 kb
Host smart-0058b8a5-b775-413b-af5c-c422e89e55cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400238897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3400238897
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3155666380
Short name T729
Test name
Test status
Simulation time 77893679 ps
CPU time 0.62 seconds
Started Mar 28 12:53:02 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 194164 kb
Host smart-a934fbe2-818f-4e77-90e8-6695ac8430e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155666380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3155666380
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.450933510
Short name T710
Test name
Test status
Simulation time 13261996 ps
CPU time 0.6 seconds
Started Mar 28 12:53:06 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 193388 kb
Host smart-797976b1-7147-45e9-9bd8-6ba1145a6faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450933510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.450933510
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3945153809
Short name T720
Test name
Test status
Simulation time 14784828 ps
CPU time 0.71 seconds
Started Mar 28 12:53:10 PM PDT 24
Finished Mar 28 12:53:10 PM PDT 24
Peak memory 194192 kb
Host smart-fc1a3814-00b0-459a-97fd-d768523ffdfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945153809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3945153809
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.352326411
Short name T828
Test name
Test status
Simulation time 36479843 ps
CPU time 0.61 seconds
Started Mar 28 12:53:06 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 193492 kb
Host smart-7964ff4e-33aa-4396-af0c-ad11fc6a05ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352326411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.352326411
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.579931139
Short name T738
Test name
Test status
Simulation time 69260803 ps
CPU time 0.58 seconds
Started Mar 28 12:53:06 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 193420 kb
Host smart-c68c9ce1-144d-42d3-9ad8-d0597b4f4fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579931139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.579931139
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3033231254
Short name T787
Test name
Test status
Simulation time 16189906 ps
CPU time 0.58 seconds
Started Mar 28 12:53:09 PM PDT 24
Finished Mar 28 12:53:09 PM PDT 24
Peak memory 193424 kb
Host smart-26dc59cb-ce31-4055-8804-0e71cc0c2749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033231254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3033231254
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1354043362
Short name T775
Test name
Test status
Simulation time 19009722 ps
CPU time 0.62 seconds
Started Mar 28 12:53:35 PM PDT 24
Finished Mar 28 12:53:36 PM PDT 24
Peak memory 193484 kb
Host smart-bb236768-e265-4c12-ba83-1ab6726a7fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354043362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1354043362
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.4146729978
Short name T767
Test name
Test status
Simulation time 137978166 ps
CPU time 1.68 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:45 PM PDT 24
Peak memory 197876 kb
Host smart-a4463b3b-4053-4733-ae53-ff5a9efc903f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146729978 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.4146729978
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.987445612
Short name T772
Test name
Test status
Simulation time 16361428 ps
CPU time 0.61 seconds
Started Mar 28 12:52:45 PM PDT 24
Finished Mar 28 12:52:46 PM PDT 24
Peak memory 194356 kb
Host smart-c455956e-5618-42aa-bd1a-07816925ac7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987445612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.987445612
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3793097227
Short name T730
Test name
Test status
Simulation time 23608977 ps
CPU time 0.58 seconds
Started Mar 28 12:52:40 PM PDT 24
Finished Mar 28 12:52:40 PM PDT 24
Peak memory 193344 kb
Host smart-eb660a2d-b410-4384-8976-0d889122569a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793097227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3793097227
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.749659921
Short name T86
Test name
Test status
Simulation time 34799117 ps
CPU time 0.92 seconds
Started Mar 28 12:53:16 PM PDT 24
Finished Mar 28 12:53:17 PM PDT 24
Peak memory 197284 kb
Host smart-c64beaa9-0667-493e-a1d9-ce8b520e840c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749659921 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.749659921
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2743411974
Short name T737
Test name
Test status
Simulation time 185531488 ps
CPU time 1.13 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 197832 kb
Host smart-331021b2-1641-48c2-b4d1-9c52b0a5211c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743411974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2743411974
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3887462628
Short name T46
Test name
Test status
Simulation time 327334333 ps
CPU time 1.42 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:46 PM PDT 24
Peak memory 197652 kb
Host smart-8d818e0f-fb0e-4419-8169-a835225e97b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887462628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3887462628
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.567424515
Short name T734
Test name
Test status
Simulation time 53997071 ps
CPU time 0.87 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 197636 kb
Host smart-a9c39a61-ed33-492d-bad5-e27ef08f5cd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567424515 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.567424515
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3149815549
Short name T96
Test name
Test status
Simulation time 15090622 ps
CPU time 0.64 seconds
Started Mar 28 12:52:45 PM PDT 24
Finished Mar 28 12:52:45 PM PDT 24
Peak memory 194648 kb
Host smart-c478973b-24ae-46df-a0bf-7f309e46f33f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149815549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3149815549
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.218836106
Short name T733
Test name
Test status
Simulation time 34783248 ps
CPU time 0.62 seconds
Started Mar 28 12:52:51 PM PDT 24
Finished Mar 28 12:52:52 PM PDT 24
Peak memory 193332 kb
Host smart-1da64fce-9b4c-4021-85d4-219936a4aad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218836106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.218836106
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4087327751
Short name T87
Test name
Test status
Simulation time 40166479 ps
CPU time 0.86 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 196072 kb
Host smart-1136289e-a7f5-4608-830b-6840ec448a94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087327751 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.4087327751
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1874478129
Short name T761
Test name
Test status
Simulation time 256252693 ps
CPU time 1.05 seconds
Started Mar 28 12:52:38 PM PDT 24
Finished Mar 28 12:52:39 PM PDT 24
Peak memory 197516 kb
Host smart-001eef25-7e8c-4686-8e10-2dd376fc19ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874478129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1874478129
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2860980288
Short name T51
Test name
Test status
Simulation time 100992288 ps
CPU time 1.39 seconds
Started Mar 28 12:52:39 PM PDT 24
Finished Mar 28 12:52:41 PM PDT 24
Peak memory 197716 kb
Host smart-18b54320-1c8e-4e84-9183-144c3b7d7586
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860980288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2860980288
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4117881309
Short name T790
Test name
Test status
Simulation time 52221978 ps
CPU time 1.23 seconds
Started Mar 28 12:53:01 PM PDT 24
Finished Mar 28 12:53:05 PM PDT 24
Peak memory 197800 kb
Host smart-a650c87f-c39a-4ee7-843c-e60ac87bffe4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117881309 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4117881309
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1455395818
Short name T750
Test name
Test status
Simulation time 21881272 ps
CPU time 0.59 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:46 PM PDT 24
Peak memory 195112 kb
Host smart-329e4b76-b583-4f8c-b4f5-5b416fac45d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455395818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1455395818
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3778758826
Short name T827
Test name
Test status
Simulation time 31329235 ps
CPU time 0.64 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:47 PM PDT 24
Peak memory 193316 kb
Host smart-b1fd2cf2-c5b7-4305-acde-e19a3fb3225b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778758826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3778758826
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.764012973
Short name T103
Test name
Test status
Simulation time 491177581 ps
CPU time 0.77 seconds
Started Mar 28 12:52:46 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 195884 kb
Host smart-7374cff0-451a-49f0-9e3d-a852a5051947
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764012973 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.764012973
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.75783095
Short name T714
Test name
Test status
Simulation time 35515966 ps
CPU time 0.99 seconds
Started Mar 28 12:52:37 PM PDT 24
Finished Mar 28 12:52:38 PM PDT 24
Peak memory 197508 kb
Host smart-a275a720-45d9-48ab-9730-90f77dcefec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75783095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.75783095
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2023363784
Short name T758
Test name
Test status
Simulation time 27425382 ps
CPU time 1.1 seconds
Started Mar 28 12:52:37 PM PDT 24
Finished Mar 28 12:52:39 PM PDT 24
Peak memory 197772 kb
Host smart-c5589eaf-0d5e-46c2-844b-bff5917ca9a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023363784 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2023363784
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.237683324
Short name T105
Test name
Test status
Simulation time 13721116 ps
CPU time 0.58 seconds
Started Mar 28 12:52:48 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 193132 kb
Host smart-4f87e547-eb18-41ca-9a7e-9b032a633719
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237683324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.237683324
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1245940161
Short name T838
Test name
Test status
Simulation time 15555097 ps
CPU time 0.58 seconds
Started Mar 28 12:52:47 PM PDT 24
Finished Mar 28 12:52:47 PM PDT 24
Peak memory 194056 kb
Host smart-5e18465a-e56b-493c-bf9a-6b9947b7b481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245940161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1245940161
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2383270795
Short name T99
Test name
Test status
Simulation time 13629991 ps
CPU time 0.66 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 194436 kb
Host smart-2c007149-9158-4624-8b5c-eb883b9ea0d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383270795 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2383270795
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1261476454
Short name T721
Test name
Test status
Simulation time 515312127 ps
CPU time 2.43 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:47 PM PDT 24
Peak memory 197804 kb
Host smart-141b24d6-0997-4be6-a4e3-d638a7363341
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261476454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1261476454
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.81884765
Short name T47
Test name
Test status
Simulation time 301713372 ps
CPU time 1.19 seconds
Started Mar 28 12:52:47 PM PDT 24
Finished Mar 28 12:52:49 PM PDT 24
Peak memory 197704 kb
Host smart-5a01b54d-a6df-4e68-be31-823bb4874bde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81884765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.gpio_tl_intg_err.81884765
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3624167257
Short name T778
Test name
Test status
Simulation time 146329982 ps
CPU time 0.96 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:45 PM PDT 24
Peak memory 197720 kb
Host smart-707668c1-e333-4626-80f3-ee7142bf57a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624167257 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3624167257
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3118231873
Short name T739
Test name
Test status
Simulation time 14052957 ps
CPU time 0.64 seconds
Started Mar 28 12:52:38 PM PDT 24
Finished Mar 28 12:52:39 PM PDT 24
Peak memory 194464 kb
Host smart-581ae208-5a19-4884-a2f8-e1693e3c436b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118231873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3118231873
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1319225889
Short name T785
Test name
Test status
Simulation time 14650768 ps
CPU time 0.62 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:45 PM PDT 24
Peak memory 194196 kb
Host smart-77621240-e61f-4283-b4fc-b6b6abfd11dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319225889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1319225889
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2072502781
Short name T804
Test name
Test status
Simulation time 78028098 ps
CPU time 0.86 seconds
Started Mar 28 12:52:41 PM PDT 24
Finished Mar 28 12:52:42 PM PDT 24
Peak memory 196712 kb
Host smart-72b0e15e-1570-4bb0-899b-5dd132202c0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072502781 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2072502781
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4102608298
Short name T773
Test name
Test status
Simulation time 638881869 ps
CPU time 2.87 seconds
Started Mar 28 12:52:48 PM PDT 24
Finished Mar 28 12:52:51 PM PDT 24
Peak memory 197772 kb
Host smart-f3e18998-f076-404d-9647-a223bb241aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102608298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4102608298
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3148685671
Short name T835
Test name
Test status
Simulation time 113691389 ps
CPU time 1.11 seconds
Started Mar 28 12:52:47 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 197780 kb
Host smart-ec9c6869-4ffd-4c62-b1fe-5c855208695e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148685671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3148685671
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.129762055
Short name T307
Test name
Test status
Simulation time 12500788 ps
CPU time 0.56 seconds
Started Mar 28 02:23:48 PM PDT 24
Finished Mar 28 02:23:49 PM PDT 24
Peak memory 192772 kb
Host smart-4a74fb48-571d-4377-a29e-63bf8aa4110c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129762055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.129762055
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2019963356
Short name T603
Test name
Test status
Simulation time 47073627 ps
CPU time 0.95 seconds
Started Mar 28 02:23:31 PM PDT 24
Finished Mar 28 02:23:32 PM PDT 24
Peak memory 196604 kb
Host smart-0fd6dac2-6833-45b2-b7dc-8f9f3efe578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019963356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2019963356
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2357537842
Short name T338
Test name
Test status
Simulation time 1144441980 ps
CPU time 16.69 seconds
Started Mar 28 02:23:33 PM PDT 24
Finished Mar 28 02:23:49 PM PDT 24
Peak memory 196916 kb
Host smart-db4964ff-7ad8-45ef-8308-685ebf255772
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357537842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2357537842
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.625335868
Short name T204
Test name
Test status
Simulation time 101087856 ps
CPU time 0.67 seconds
Started Mar 28 02:23:33 PM PDT 24
Finished Mar 28 02:23:34 PM PDT 24
Peak memory 194568 kb
Host smart-06127757-bbad-42c9-aacc-2c6f617fe72d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625335868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.625335868
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1722514989
Short name T156
Test name
Test status
Simulation time 82052610 ps
CPU time 1.05 seconds
Started Mar 28 02:23:33 PM PDT 24
Finished Mar 28 02:23:34 PM PDT 24
Peak memory 196184 kb
Host smart-99d76b49-0ac1-4075-abd0-54c7ad8cd13b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722514989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1722514989
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3569475761
Short name T427
Test name
Test status
Simulation time 76058667 ps
CPU time 3.43 seconds
Started Mar 28 02:23:32 PM PDT 24
Finished Mar 28 02:23:36 PM PDT 24
Peak memory 196500 kb
Host smart-488874c0-ac00-4483-a865-f31b6ba79744
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569475761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3569475761
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3572853679
Short name T465
Test name
Test status
Simulation time 219615551 ps
CPU time 1.27 seconds
Started Mar 28 02:23:32 PM PDT 24
Finished Mar 28 02:23:33 PM PDT 24
Peak memory 196076 kb
Host smart-2b796980-e577-4953-82af-297d96a76f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572853679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3572853679
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3104124828
Short name T526
Test name
Test status
Simulation time 24111080 ps
CPU time 0.88 seconds
Started Mar 28 02:23:32 PM PDT 24
Finished Mar 28 02:23:33 PM PDT 24
Peak memory 196632 kb
Host smart-f27b5fad-7d07-486e-bec9-d1d00ebb3768
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104124828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3104124828
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.753123966
Short name T459
Test name
Test status
Simulation time 587019056 ps
CPU time 3.45 seconds
Started Mar 28 02:23:32 PM PDT 24
Finished Mar 28 02:23:36 PM PDT 24
Peak memory 197956 kb
Host smart-cbeb7ddb-8ea4-49b8-a9aa-6457409a1801
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753123966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.753123966
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1241690590
Short name T54
Test name
Test status
Simulation time 45548576 ps
CPU time 0.81 seconds
Started Mar 28 02:23:31 PM PDT 24
Finished Mar 28 02:23:32 PM PDT 24
Peak memory 213704 kb
Host smart-2d69e513-3dba-4d42-98bc-230607231eaa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241690590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1241690590
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1101793095
Short name T76
Test name
Test status
Simulation time 72869068 ps
CPU time 1.18 seconds
Started Mar 28 02:23:30 PM PDT 24
Finished Mar 28 02:23:31 PM PDT 24
Peak memory 195528 kb
Host smart-e8c96770-38e9-455e-ac8f-972f6181c06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101793095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1101793095
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3354654627
Short name T392
Test name
Test status
Simulation time 293565617 ps
CPU time 0.97 seconds
Started Mar 28 02:23:34 PM PDT 24
Finished Mar 28 02:23:35 PM PDT 24
Peak memory 196540 kb
Host smart-8ca6a570-28b1-4f70-995b-c0a7276ba4e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354654627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3354654627
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3846251086
Short name T694
Test name
Test status
Simulation time 23325795244 ps
CPU time 157.19 seconds
Started Mar 28 02:23:31 PM PDT 24
Finished Mar 28 02:26:09 PM PDT 24
Peak memory 198132 kb
Host smart-c8722895-a549-4ed4-98c3-e7543c88126a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846251086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3846251086
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3050666184
Short name T515
Test name
Test status
Simulation time 15516111 ps
CPU time 0.57 seconds
Started Mar 28 02:23:52 PM PDT 24
Finished Mar 28 02:23:52 PM PDT 24
Peak memory 194644 kb
Host smart-fa81865d-cc77-4a50-93b3-702c7c49212b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050666184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3050666184
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3124142791
Short name T331
Test name
Test status
Simulation time 32575456 ps
CPU time 0.76 seconds
Started Mar 28 02:23:50 PM PDT 24
Finished Mar 28 02:23:51 PM PDT 24
Peak memory 195212 kb
Host smart-84e12d58-e048-4d1f-87c2-2c0570874c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124142791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3124142791
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1508984639
Short name T194
Test name
Test status
Simulation time 359431232 ps
CPU time 12.53 seconds
Started Mar 28 02:23:50 PM PDT 24
Finished Mar 28 02:24:03 PM PDT 24
Peak memory 196300 kb
Host smart-ed2308e6-0624-432a-976c-e0a0911f80fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508984639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1508984639
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1966725872
Short name T227
Test name
Test status
Simulation time 174493527 ps
CPU time 0.83 seconds
Started Mar 28 02:23:52 PM PDT 24
Finished Mar 28 02:23:53 PM PDT 24
Peak memory 195936 kb
Host smart-20b2d89d-b16e-45ed-a84b-c12568ae2131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966725872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1966725872
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3284585150
Short name T541
Test name
Test status
Simulation time 36242522 ps
CPU time 1.05 seconds
Started Mar 28 02:23:50 PM PDT 24
Finished Mar 28 02:23:51 PM PDT 24
Peak memory 196008 kb
Host smart-7490c566-9113-4793-8eea-d9f137633ff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284585150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3284585150
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2185026197
Short name T407
Test name
Test status
Simulation time 59306211 ps
CPU time 2.42 seconds
Started Mar 28 02:23:49 PM PDT 24
Finished Mar 28 02:23:52 PM PDT 24
Peak memory 197288 kb
Host smart-028e272f-09f5-4cbf-89e9-01d1df08edab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185026197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2185026197
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2753886454
Short name T346
Test name
Test status
Simulation time 358585561 ps
CPU time 3.29 seconds
Started Mar 28 02:23:50 PM PDT 24
Finished Mar 28 02:23:53 PM PDT 24
Peak memory 198064 kb
Host smart-802d1c23-ad2a-4ea0-b20c-b10809fa2db6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753886454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2753886454
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.706230349
Short name T212
Test name
Test status
Simulation time 91567928 ps
CPU time 0.8 seconds
Started Mar 28 02:23:50 PM PDT 24
Finished Mar 28 02:23:51 PM PDT 24
Peak memory 195436 kb
Host smart-1cc7af69-8679-4407-894f-a8818330a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706230349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.706230349
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2238063917
Short name T451
Test name
Test status
Simulation time 59987650 ps
CPU time 1.46 seconds
Started Mar 28 02:23:49 PM PDT 24
Finished Mar 28 02:23:50 PM PDT 24
Peak memory 197028 kb
Host smart-b87b2740-727e-4e48-8c2a-c08e831d995a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238063917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2238063917
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.667107882
Short name T192
Test name
Test status
Simulation time 73852609 ps
CPU time 1.8 seconds
Started Mar 28 02:23:51 PM PDT 24
Finished Mar 28 02:23:53 PM PDT 24
Peak memory 197992 kb
Host smart-a63aaefb-4000-4ef5-a52a-ac78e3f765e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667107882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.667107882
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1188823041
Short name T53
Test name
Test status
Simulation time 378296950 ps
CPU time 0.89 seconds
Started Mar 28 02:23:52 PM PDT 24
Finished Mar 28 02:23:53 PM PDT 24
Peak memory 213808 kb
Host smart-e3584d57-62b8-4218-b0a0-ce183a62705e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188823041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1188823041
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3860637420
Short name T176
Test name
Test status
Simulation time 54411092 ps
CPU time 1.19 seconds
Started Mar 28 02:23:49 PM PDT 24
Finished Mar 28 02:23:50 PM PDT 24
Peak memory 195768 kb
Host smart-ce9d1f01-22f8-481b-a7b1-74be05fd0914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860637420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3860637420
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2071615578
Short name T666
Test name
Test status
Simulation time 1083387107 ps
CPU time 1.32 seconds
Started Mar 28 02:23:49 PM PDT 24
Finished Mar 28 02:23:51 PM PDT 24
Peak memory 196548 kb
Host smart-cc96c68d-12ce-41f4-8e19-961948faea23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071615578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2071615578
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.199239356
Short name T397
Test name
Test status
Simulation time 6424648472 ps
CPU time 26.11 seconds
Started Mar 28 02:23:50 PM PDT 24
Finished Mar 28 02:24:16 PM PDT 24
Peak memory 191992 kb
Host smart-1bb02cfd-0acd-4f5e-9a5a-022a4dc5c0af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199239356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.199239356
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1837645049
Short name T466
Test name
Test status
Simulation time 31355098 ps
CPU time 0.57 seconds
Started Mar 28 02:26:11 PM PDT 24
Finished Mar 28 02:26:12 PM PDT 24
Peak memory 194020 kb
Host smart-08a113ce-7675-422e-b0c9-59c07910ccfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837645049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1837645049
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3727019928
Short name T193
Test name
Test status
Simulation time 72836619 ps
CPU time 0.75 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 196008 kb
Host smart-23904943-f3f9-49be-81ef-ff925e78545e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727019928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3727019928
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.4088446508
Short name T700
Test name
Test status
Simulation time 401448721 ps
CPU time 13.77 seconds
Started Mar 28 02:25:52 PM PDT 24
Finished Mar 28 02:26:07 PM PDT 24
Peak memory 196736 kb
Host smart-23a2a105-9c36-4390-80c0-0da1695b7211
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088446508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.4088446508
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2642957367
Short name T684
Test name
Test status
Simulation time 92948521 ps
CPU time 0.86 seconds
Started Mar 28 02:25:56 PM PDT 24
Finished Mar 28 02:25:57 PM PDT 24
Peak memory 196208 kb
Host smart-f24c9f92-6d00-4722-b9ef-c4fcce87344e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642957367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2642957367
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1937702084
Short name T484
Test name
Test status
Simulation time 56416663 ps
CPU time 1.11 seconds
Started Mar 28 02:25:56 PM PDT 24
Finished Mar 28 02:25:57 PM PDT 24
Peak memory 196592 kb
Host smart-1f1ac984-e688-4e7d-bf51-f2db639dff9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937702084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1937702084
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3387070033
Short name T449
Test name
Test status
Simulation time 26035306 ps
CPU time 1.07 seconds
Started Mar 28 02:25:49 PM PDT 24
Finished Mar 28 02:25:50 PM PDT 24
Peak memory 197116 kb
Host smart-8b639272-4cb1-40a6-b60d-f8154f5c250b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387070033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3387070033
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1742680051
Short name T276
Test name
Test status
Simulation time 467650486 ps
CPU time 3.89 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:25:58 PM PDT 24
Peak memory 198056 kb
Host smart-a7ae333e-b588-49aa-a78c-385503cf0c8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742680051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1742680051
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.338599890
Short name T404
Test name
Test status
Simulation time 77116595 ps
CPU time 0.8 seconds
Started Mar 28 02:25:55 PM PDT 24
Finished Mar 28 02:25:56 PM PDT 24
Peak memory 195464 kb
Host smart-877a1988-82f4-4520-bba4-aca41e4c5351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338599890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.338599890
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2751507766
Short name T527
Test name
Test status
Simulation time 188326777 ps
CPU time 1.34 seconds
Started Mar 28 02:25:53 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 197148 kb
Host smart-f559b44f-9a5f-4714-ae8f-aa971f251c56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751507766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2751507766
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1060742661
Short name T623
Test name
Test status
Simulation time 526320390 ps
CPU time 6.11 seconds
Started Mar 28 02:25:55 PM PDT 24
Finished Mar 28 02:26:01 PM PDT 24
Peak memory 198012 kb
Host smart-2f046a67-28b8-4d03-a114-a970ad9a5465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060742661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1060742661
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3095946226
Short name T608
Test name
Test status
Simulation time 41239228 ps
CPU time 1.32 seconds
Started Mar 28 02:25:55 PM PDT 24
Finished Mar 28 02:25:57 PM PDT 24
Peak memory 196792 kb
Host smart-2de1bb7d-9c20-4cfa-983c-1b3138f69e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095946226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3095946226
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.98068698
Short name T261
Test name
Test status
Simulation time 228745035 ps
CPU time 1.23 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 196296 kb
Host smart-30202a50-5612-48f1-99a2-7b0a45881eab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98068698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.98068698
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3591490429
Short name T692
Test name
Test status
Simulation time 23468575411 ps
CPU time 173.97 seconds
Started Mar 28 02:25:57 PM PDT 24
Finished Mar 28 02:28:51 PM PDT 24
Peak memory 198184 kb
Host smart-593ded11-89e7-455e-8be8-b9523c50ae55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591490429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3591490429
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3331092032
Short name T659
Test name
Test status
Simulation time 21164567 ps
CPU time 0.59 seconds
Started Mar 28 02:26:11 PM PDT 24
Finished Mar 28 02:26:12 PM PDT 24
Peak memory 193956 kb
Host smart-9133f058-0bb0-4cee-aa99-a9cf08486c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331092032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3331092032
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1846739321
Short name T494
Test name
Test status
Simulation time 89893132 ps
CPU time 0.74 seconds
Started Mar 28 02:26:12 PM PDT 24
Finished Mar 28 02:26:13 PM PDT 24
Peak memory 194220 kb
Host smart-1e8c32ff-f441-40bf-81f0-6a86ac9c5b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846739321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1846739321
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2108664551
Short name T579
Test name
Test status
Simulation time 3952767769 ps
CPU time 21.36 seconds
Started Mar 28 02:26:11 PM PDT 24
Finished Mar 28 02:26:32 PM PDT 24
Peak memory 196752 kb
Host smart-2eff9641-cc5c-46b6-b0ea-bcd0e6c44025
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108664551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2108664551
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.4096945778
Short name T626
Test name
Test status
Simulation time 284835343 ps
CPU time 1.04 seconds
Started Mar 28 02:26:13 PM PDT 24
Finished Mar 28 02:26:14 PM PDT 24
Peak memory 196580 kb
Host smart-10658381-280b-4f0c-a532-c32636a5ae25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096945778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.4096945778
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2554620612
Short name T136
Test name
Test status
Simulation time 75971884 ps
CPU time 1.34 seconds
Started Mar 28 02:26:12 PM PDT 24
Finished Mar 28 02:26:13 PM PDT 24
Peak memory 197164 kb
Host smart-0ceb4156-b3cb-4b1d-9ea6-511e57e73635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554620612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2554620612
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1147395466
Short name T19
Test name
Test status
Simulation time 76460655 ps
CPU time 2.9 seconds
Started Mar 28 02:26:13 PM PDT 24
Finished Mar 28 02:26:16 PM PDT 24
Peak memory 198040 kb
Host smart-18b79c68-bbb6-40d1-9f39-d173eb6a0956
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147395466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1147395466
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1727068944
Short name T549
Test name
Test status
Simulation time 450551294 ps
CPU time 3.75 seconds
Started Mar 28 02:26:11 PM PDT 24
Finished Mar 28 02:26:15 PM PDT 24
Peak memory 198040 kb
Host smart-6b03b6e1-829c-40db-9176-e55e2e59ddea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727068944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1727068944
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2869155083
Short name T568
Test name
Test status
Simulation time 46048681 ps
CPU time 1.14 seconds
Started Mar 28 02:26:13 PM PDT 24
Finished Mar 28 02:26:14 PM PDT 24
Peak memory 196856 kb
Host smart-ec851e4f-b790-4263-a515-cde3f878a00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869155083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2869155083
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3782066393
Short name T203
Test name
Test status
Simulation time 166215529 ps
CPU time 1.18 seconds
Started Mar 28 02:26:13 PM PDT 24
Finished Mar 28 02:26:15 PM PDT 24
Peak memory 195960 kb
Host smart-9adb0e3b-7eef-4ef1-a4d5-29d456d53dbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782066393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3782066393
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2996074624
Short name T544
Test name
Test status
Simulation time 84855795 ps
CPU time 3.95 seconds
Started Mar 28 02:26:16 PM PDT 24
Finished Mar 28 02:26:20 PM PDT 24
Peak memory 197968 kb
Host smart-066bd4ad-54eb-4acd-8d85-b41df71ed91c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996074624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2996074624
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2417344067
Short name T708
Test name
Test status
Simulation time 139737847 ps
CPU time 1.13 seconds
Started Mar 28 02:26:12 PM PDT 24
Finished Mar 28 02:26:14 PM PDT 24
Peak memory 195748 kb
Host smart-f95b4fe4-7eef-42b1-92b2-43df0366121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417344067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2417344067
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1380781278
Short name T553
Test name
Test status
Simulation time 758433327 ps
CPU time 1.25 seconds
Started Mar 28 02:26:13 PM PDT 24
Finished Mar 28 02:26:15 PM PDT 24
Peak memory 195556 kb
Host smart-d8e99308-bfe8-48d3-a21d-a606135f6000
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380781278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1380781278
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2628131213
Short name T536
Test name
Test status
Simulation time 4605785306 ps
CPU time 119.14 seconds
Started Mar 28 02:26:11 PM PDT 24
Finished Mar 28 02:28:10 PM PDT 24
Peak memory 198252 kb
Host smart-17757bd6-ca94-4c68-a7e4-ebac47ba27f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628131213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2628131213
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.3915043795
Short name T537
Test name
Test status
Simulation time 25905415305 ps
CPU time 710.48 seconds
Started Mar 28 02:26:15 PM PDT 24
Finished Mar 28 02:38:05 PM PDT 24
Peak memory 198324 kb
Host smart-952c1907-8ab9-4d37-a40f-afa0132c36eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3915043795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.3915043795
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1817217792
Short name T320
Test name
Test status
Simulation time 46250923 ps
CPU time 0.78 seconds
Started Mar 28 02:26:11 PM PDT 24
Finished Mar 28 02:26:12 PM PDT 24
Peak memory 195340 kb
Host smart-d0bfe513-e6b6-44f9-bd7b-9396c35b8eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817217792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1817217792
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2249633955
Short name T390
Test name
Test status
Simulation time 1712835390 ps
CPU time 24.21 seconds
Started Mar 28 02:26:30 PM PDT 24
Finished Mar 28 02:26:54 PM PDT 24
Peak memory 196964 kb
Host smart-4e6dbfe2-d127-418e-84b2-1229a6d25cdb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249633955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2249633955
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.566349907
Short name T557
Test name
Test status
Simulation time 47376996 ps
CPU time 0.63 seconds
Started Mar 28 02:26:31 PM PDT 24
Finished Mar 28 02:26:31 PM PDT 24
Peak memory 194388 kb
Host smart-26828c50-2670-4d49-bdcd-6243cc3fe326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566349907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.566349907
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2115504005
Short name T554
Test name
Test status
Simulation time 175302063 ps
CPU time 1.48 seconds
Started Mar 28 02:26:30 PM PDT 24
Finished Mar 28 02:26:32 PM PDT 24
Peak memory 197036 kb
Host smart-5dad92c5-f55b-4b30-9774-ab560d259421
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115504005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2115504005
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.533343907
Short name T366
Test name
Test status
Simulation time 62818240 ps
CPU time 1.98 seconds
Started Mar 28 02:26:29 PM PDT 24
Finished Mar 28 02:26:31 PM PDT 24
Peak memory 198128 kb
Host smart-db1f8a48-6027-4db1-875f-9dae45807203
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533343907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.533343907
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.238400252
Short name T180
Test name
Test status
Simulation time 47553380 ps
CPU time 1.6 seconds
Started Mar 28 02:26:30 PM PDT 24
Finished Mar 28 02:26:31 PM PDT 24
Peak memory 196492 kb
Host smart-65e2c4a7-aaeb-4f98-a9ae-add57bdbe170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238400252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
238400252
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3880213911
Short name T71
Test name
Test status
Simulation time 57167517 ps
CPU time 0.73 seconds
Started Mar 28 02:26:14 PM PDT 24
Finished Mar 28 02:26:15 PM PDT 24
Peak memory 195368 kb
Host smart-ccab56d7-252e-4288-bce2-c988a00fcabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880213911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3880213911
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3094165443
Short name T214
Test name
Test status
Simulation time 181365967 ps
CPU time 1.25 seconds
Started Mar 28 02:26:12 PM PDT 24
Finished Mar 28 02:26:13 PM PDT 24
Peak memory 197108 kb
Host smart-a9e91889-b950-49b8-b175-b2f6ac93d672
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094165443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3094165443
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1709330062
Short name T148
Test name
Test status
Simulation time 358863146 ps
CPU time 4.27 seconds
Started Mar 28 02:26:31 PM PDT 24
Finished Mar 28 02:26:35 PM PDT 24
Peak memory 197972 kb
Host smart-b60fda30-ce24-46a3-a4ff-3efd617c3945
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709330062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1709330062
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1240473694
Short name T521
Test name
Test status
Simulation time 81524501 ps
CPU time 0.89 seconds
Started Mar 28 02:26:12 PM PDT 24
Finished Mar 28 02:26:13 PM PDT 24
Peak memory 195560 kb
Host smart-f5254fc6-8502-4702-8084-8ac16079c1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240473694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1240473694
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2063478974
Short name T154
Test name
Test status
Simulation time 58893687 ps
CPU time 1.24 seconds
Started Mar 28 02:26:11 PM PDT 24
Finished Mar 28 02:26:13 PM PDT 24
Peak memory 195724 kb
Host smart-719eca6e-c093-4047-a247-46f07cc09914
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063478974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2063478974
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2493965620
Short name T10
Test name
Test status
Simulation time 22677002493 ps
CPU time 70.64 seconds
Started Mar 28 02:26:30 PM PDT 24
Finished Mar 28 02:27:41 PM PDT 24
Peak memory 198192 kb
Host smart-75bad29c-95e3-4ec0-bc0f-898dcdbb882a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493965620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2493965620
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.538979161
Short name T333
Test name
Test status
Simulation time 14118696 ps
CPU time 0.58 seconds
Started Mar 28 02:26:34 PM PDT 24
Finished Mar 28 02:26:35 PM PDT 24
Peak memory 194864 kb
Host smart-f2c5cac1-8d97-4db9-85bc-7760373e67f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538979161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.538979161
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3255906803
Short name T589
Test name
Test status
Simulation time 39240893 ps
CPU time 0.71 seconds
Started Mar 28 02:26:34 PM PDT 24
Finished Mar 28 02:26:35 PM PDT 24
Peak memory 195284 kb
Host smart-5a1a3cf4-84f7-4b0c-b89b-9805b90be161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255906803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3255906803
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3542936636
Short name T498
Test name
Test status
Simulation time 208739439 ps
CPU time 11.38 seconds
Started Mar 28 02:26:29 PM PDT 24
Finished Mar 28 02:26:41 PM PDT 24
Peak memory 195548 kb
Host smart-df10a6b6-d0cf-4340-b8c8-d4778156e5d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542936636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3542936636
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.338950062
Short name T620
Test name
Test status
Simulation time 135412879 ps
CPU time 0.99 seconds
Started Mar 28 02:26:31 PM PDT 24
Finished Mar 28 02:26:32 PM PDT 24
Peak memory 196116 kb
Host smart-f9d6f7fc-d261-419e-b2aa-0df7cf4a92c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338950062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.338950062
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2388142908
Short name T355
Test name
Test status
Simulation time 92228973 ps
CPU time 1.32 seconds
Started Mar 28 02:26:28 PM PDT 24
Finished Mar 28 02:26:29 PM PDT 24
Peak memory 198000 kb
Host smart-b67899a8-df0c-4c97-bfff-c6fac934d597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388142908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2388142908
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3077863902
Short name T599
Test name
Test status
Simulation time 215713367 ps
CPU time 3.24 seconds
Started Mar 28 02:26:30 PM PDT 24
Finished Mar 28 02:26:34 PM PDT 24
Peak memory 198088 kb
Host smart-639c9cef-ef7c-4871-8bcb-462ff12cbc0d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077863902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3077863902
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3600714741
Short name T680
Test name
Test status
Simulation time 94509436 ps
CPU time 0.82 seconds
Started Mar 28 02:26:31 PM PDT 24
Finished Mar 28 02:26:32 PM PDT 24
Peak memory 194420 kb
Host smart-1e20cd36-3604-49ff-8c8a-14e7dfc78f22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600714741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3600714741
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2895498493
Short name T130
Test name
Test status
Simulation time 141912571 ps
CPU time 1.32 seconds
Started Mar 28 02:26:30 PM PDT 24
Finished Mar 28 02:26:32 PM PDT 24
Peak memory 197996 kb
Host smart-21c93319-156e-4f22-9bb2-cfaa301a826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895498493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2895498493
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.897153689
Short name T627
Test name
Test status
Simulation time 84872555 ps
CPU time 1.17 seconds
Started Mar 28 02:26:31 PM PDT 24
Finished Mar 28 02:26:32 PM PDT 24
Peak memory 196076 kb
Host smart-afa9b2ad-bf97-4a88-a0f2-cc3d0bb32faf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897153689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.897153689
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4133179928
Short name T299
Test name
Test status
Simulation time 780867937 ps
CPU time 3.59 seconds
Started Mar 28 02:26:33 PM PDT 24
Finished Mar 28 02:26:37 PM PDT 24
Peak memory 197964 kb
Host smart-8ca12a4c-7b1e-4eda-b825-79ed5574c8f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133179928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4133179928
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3898010949
Short name T431
Test name
Test status
Simulation time 33731260 ps
CPU time 1.16 seconds
Started Mar 28 02:26:33 PM PDT 24
Finished Mar 28 02:26:34 PM PDT 24
Peak memory 195784 kb
Host smart-129f0455-0594-4c0e-836e-4bc638aa7790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898010949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3898010949
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1635136852
Short name T327
Test name
Test status
Simulation time 208493515 ps
CPU time 1.24 seconds
Started Mar 28 02:26:29 PM PDT 24
Finished Mar 28 02:26:30 PM PDT 24
Peak memory 195648 kb
Host smart-5b0ad39f-1b28-453a-a140-bdc35dcd12c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635136852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1635136852
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1508270160
Short name T3
Test name
Test status
Simulation time 16731277518 ps
CPU time 50.16 seconds
Started Mar 28 02:26:29 PM PDT 24
Finished Mar 28 02:27:19 PM PDT 24
Peak memory 198100 kb
Host smart-57138b9e-2254-41ad-b875-b28a88545cdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508270160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1508270160
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1438985745
Short name T597
Test name
Test status
Simulation time 15247941 ps
CPU time 0.62 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:26:53 PM PDT 24
Peak memory 193964 kb
Host smart-5890a116-e936-4f88-a98f-e631d76fbd46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438985745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1438985745
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2437380222
Short name T401
Test name
Test status
Simulation time 53641556 ps
CPU time 0.73 seconds
Started Mar 28 02:26:29 PM PDT 24
Finished Mar 28 02:26:30 PM PDT 24
Peak memory 194968 kb
Host smart-48408a25-6b5a-4171-9612-de6d72f0e9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437380222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2437380222
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3718053561
Short name T330
Test name
Test status
Simulation time 909566763 ps
CPU time 25.65 seconds
Started Mar 28 02:26:51 PM PDT 24
Finished Mar 28 02:27:17 PM PDT 24
Peak memory 196928 kb
Host smart-54e8d53c-2239-4fe1-9fd8-cb645e29e1f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718053561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3718053561
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.250308312
Short name T343
Test name
Test status
Simulation time 87332860 ps
CPU time 1.05 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:55 PM PDT 24
Peak memory 196680 kb
Host smart-a90052e4-4458-42de-92e2-5ef87d1b82f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250308312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.250308312
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2397420216
Short name T415
Test name
Test status
Simulation time 281022785 ps
CPU time 0.79 seconds
Started Mar 28 02:26:34 PM PDT 24
Finished Mar 28 02:26:35 PM PDT 24
Peak memory 195504 kb
Host smart-9ecd35e0-cb41-4d0c-b117-361c393d99b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397420216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2397420216
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1589472772
Short name T152
Test name
Test status
Simulation time 173812092 ps
CPU time 1.96 seconds
Started Mar 28 02:26:29 PM PDT 24
Finished Mar 28 02:26:31 PM PDT 24
Peak memory 198156 kb
Host smart-237326bd-f87b-483d-a361-9b72806ffcef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589472772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1589472772
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.893431347
Short name T501
Test name
Test status
Simulation time 71880947 ps
CPU time 2.21 seconds
Started Mar 28 02:26:32 PM PDT 24
Finished Mar 28 02:26:34 PM PDT 24
Peak memory 197276 kb
Host smart-87bd2d5e-5acd-472f-abe0-0aba78a3813b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893431347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
893431347
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2170720622
Short name T370
Test name
Test status
Simulation time 101411855 ps
CPU time 1.15 seconds
Started Mar 28 02:26:30 PM PDT 24
Finished Mar 28 02:26:31 PM PDT 24
Peak memory 196104 kb
Host smart-0d82ebbf-f791-42e2-8f5c-e9548e4ff206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170720622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2170720622
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4118550388
Short name T452
Test name
Test status
Simulation time 149495233 ps
CPU time 1.49 seconds
Started Mar 28 02:26:30 PM PDT 24
Finished Mar 28 02:26:32 PM PDT 24
Peak memory 196996 kb
Host smart-12f36133-558e-4c29-839b-9a06d3c7fffd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118550388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4118550388
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1579471088
Short name T387
Test name
Test status
Simulation time 197680452 ps
CPU time 3.5 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:58 PM PDT 24
Peak memory 197996 kb
Host smart-79cb34c9-d12c-4213-be83-018aaa8019ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579471088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1579471088
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2817807880
Short name T310
Test name
Test status
Simulation time 187163415 ps
CPU time 1.05 seconds
Started Mar 28 02:26:31 PM PDT 24
Finished Mar 28 02:26:32 PM PDT 24
Peak memory 197336 kb
Host smart-83697840-ec66-42f7-a79f-c1ea51f9260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817807880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2817807880
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.571194985
Short name T360
Test name
Test status
Simulation time 140748513 ps
CPU time 1.31 seconds
Started Mar 28 02:26:29 PM PDT 24
Finished Mar 28 02:26:31 PM PDT 24
Peak memory 196544 kb
Host smart-a52b68a0-7b8f-48e4-98c2-99e727b110b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571194985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.571194985
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3740356413
Short name T364
Test name
Test status
Simulation time 37729210866 ps
CPU time 129.12 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:29:03 PM PDT 24
Peak memory 198164 kb
Host smart-47c5afa2-cd8d-4b25-8688-5b6f729efce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740356413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3740356413
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3927913960
Short name T38
Test name
Test status
Simulation time 36646169680 ps
CPU time 611.67 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:37:06 PM PDT 24
Peak memory 198320 kb
Host smart-351322d8-39fb-4a45-9305-cf5fe2187789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3927913960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3927913960
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2072918160
Short name T209
Test name
Test status
Simulation time 29688191 ps
CPU time 0.6 seconds
Started Mar 28 02:27:00 PM PDT 24
Finished Mar 28 02:27:01 PM PDT 24
Peak memory 193956 kb
Host smart-f515524e-99e6-446f-bca4-613f98761967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072918160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2072918160
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1055448634
Short name T353
Test name
Test status
Simulation time 250514741 ps
CPU time 1.04 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:26:54 PM PDT 24
Peak memory 195920 kb
Host smart-61cc77ee-6153-4734-b239-437005d901f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055448634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1055448634
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.384823652
Short name T699
Test name
Test status
Simulation time 2009002795 ps
CPU time 28.98 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:27:22 PM PDT 24
Peak memory 196936 kb
Host smart-d38e8831-8177-41f4-b551-b977c338f5ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384823652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.384823652
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.154569525
Short name T264
Test name
Test status
Simulation time 46492928 ps
CPU time 0.89 seconds
Started Mar 28 02:26:58 PM PDT 24
Finished Mar 28 02:26:59 PM PDT 24
Peak memory 196044 kb
Host smart-8391cac6-78fb-4c57-a3ce-8c2650bb970b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154569525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.154569525
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3774962545
Short name T18
Test name
Test status
Simulation time 696459811 ps
CPU time 1.02 seconds
Started Mar 28 02:26:57 PM PDT 24
Finished Mar 28 02:26:59 PM PDT 24
Peak memory 196024 kb
Host smart-7b53561e-7a7b-429c-a45d-b811eb1c8b8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774962545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3774962545
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.561024686
Short name T512
Test name
Test status
Simulation time 75750198 ps
CPU time 3.31 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:57 PM PDT 24
Peak memory 198104 kb
Host smart-ad7c804d-113d-49af-b814-f5d49ddfd982
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561024686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.561024686
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2470182204
Short name T647
Test name
Test status
Simulation time 445515597 ps
CPU time 2.89 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:26:55 PM PDT 24
Peak memory 198104 kb
Host smart-73d8493d-6a5b-4fc9-80c8-da201c3ff5a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470182204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2470182204
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.348519617
Short name T195
Test name
Test status
Simulation time 25432147 ps
CPU time 0.73 seconds
Started Mar 28 02:26:54 PM PDT 24
Finished Mar 28 02:26:56 PM PDT 24
Peak memory 194400 kb
Host smart-1b8dfe0f-e0e7-4cab-a18c-7d6ca8ecff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348519617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.348519617
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.910088496
Short name T606
Test name
Test status
Simulation time 57780722 ps
CPU time 1.22 seconds
Started Mar 28 02:26:51 PM PDT 24
Finished Mar 28 02:26:52 PM PDT 24
Peak memory 197088 kb
Host smart-07cb5534-acb8-44ae-82aa-7f45e4c1fce1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910088496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.910088496
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3077542800
Short name T314
Test name
Test status
Simulation time 58363386 ps
CPU time 1.5 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:55 PM PDT 24
Peak memory 198040 kb
Host smart-3ad36834-ce79-49f2-873a-5dd4da58a29f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077542800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3077542800
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.310728221
Short name T421
Test name
Test status
Simulation time 62949628 ps
CPU time 0.83 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:26:53 PM PDT 24
Peak memory 196060 kb
Host smart-c39354fb-6d72-499e-8178-cbca37e3907b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310728221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.310728221
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3318419249
Short name T615
Test name
Test status
Simulation time 119962513 ps
CPU time 1.19 seconds
Started Mar 28 02:26:50 PM PDT 24
Finished Mar 28 02:26:52 PM PDT 24
Peak memory 196308 kb
Host smart-3987e52b-6c23-4d34-ad0b-757b57f3f861
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318419249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3318419249
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2670569209
Short name T313
Test name
Test status
Simulation time 3149742136 ps
CPU time 74.24 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:28:08 PM PDT 24
Peak memory 198184 kb
Host smart-c2b5700f-fd34-41e6-864d-70ef260dbaab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670569209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2670569209
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.84926974
Short name T133
Test name
Test status
Simulation time 98888108 ps
CPU time 0.56 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:26:53 PM PDT 24
Peak memory 193784 kb
Host smart-21e08c60-dc2c-4b70-9020-70bc3a618580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84926974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.84926974
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4264990284
Short name T396
Test name
Test status
Simulation time 39826423 ps
CPU time 0.82 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:54 PM PDT 24
Peak memory 195468 kb
Host smart-66d36f6a-0283-4ec5-8c4c-30a0e2285c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264990284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4264990284
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1776580389
Short name T230
Test name
Test status
Simulation time 2482422940 ps
CPU time 22.97 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:27:16 PM PDT 24
Peak memory 198080 kb
Host smart-1b72e226-b9d7-420f-bbb6-1fdf95fae689
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776580389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1776580389
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.629791682
Short name T1
Test name
Test status
Simulation time 65761854 ps
CPU time 0.93 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:55 PM PDT 24
Peak memory 196152 kb
Host smart-08aed42e-38e0-43f4-8c9a-6a24c829fecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629791682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.629791682
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1454205837
Short name T402
Test name
Test status
Simulation time 225805880 ps
CPU time 1.18 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:55 PM PDT 24
Peak memory 196660 kb
Host smart-e6fa989a-77e3-4d8f-8dad-96953abf7a05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454205837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1454205837
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2152356962
Short name T600
Test name
Test status
Simulation time 294186891 ps
CPU time 3.03 seconds
Started Mar 28 02:26:58 PM PDT 24
Finished Mar 28 02:27:02 PM PDT 24
Peak memory 198100 kb
Host smart-7ee0933a-54b6-4b8a-8b61-409d5d55693b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152356962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2152356962
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2134766174
Short name T378
Test name
Test status
Simulation time 146424491 ps
CPU time 3.36 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:57 PM PDT 24
Peak memory 198060 kb
Host smart-2f3292b0-a0fa-4645-a467-a889d61aa460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134766174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2134766174
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1498135940
Short name T285
Test name
Test status
Simulation time 70316836 ps
CPU time 1.57 seconds
Started Mar 28 02:26:54 PM PDT 24
Finished Mar 28 02:26:57 PM PDT 24
Peak memory 198048 kb
Host smart-203d8556-4490-4e10-9a3c-578bdb13873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498135940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1498135940
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.319056446
Short name T249
Test name
Test status
Simulation time 87688059 ps
CPU time 0.77 seconds
Started Mar 28 02:26:53 PM PDT 24
Finished Mar 28 02:26:54 PM PDT 24
Peak memory 196136 kb
Host smart-cbb2687a-cb51-4adf-8cc3-88e51b5dfc9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319056446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.319056446
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3390316990
Short name T26
Test name
Test status
Simulation time 1103990723 ps
CPU time 4.87 seconds
Started Mar 28 02:26:54 PM PDT 24
Finished Mar 28 02:26:59 PM PDT 24
Peak memory 197684 kb
Host smart-d2b046d2-c37b-45a1-b862-ebb6bf2016ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390316990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3390316990
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.598582303
Short name T137
Test name
Test status
Simulation time 134889532 ps
CPU time 1.26 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:26:54 PM PDT 24
Peak memory 196692 kb
Host smart-6d20a210-7b36-4658-bcc9-3ef0c0f4c146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598582303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.598582303
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1957003866
Short name T499
Test name
Test status
Simulation time 149113902 ps
CPU time 1.11 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:26:53 PM PDT 24
Peak memory 195596 kb
Host smart-dabbbae3-9b46-49fc-89be-c76ae9e09d23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957003866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1957003866
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2221484226
Short name T379
Test name
Test status
Simulation time 6943279601 ps
CPU time 74.66 seconds
Started Mar 28 02:26:52 PM PDT 24
Finished Mar 28 02:28:07 PM PDT 24
Peak memory 198180 kb
Host smart-dc0869ce-195c-47f4-9316-33d148789fb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221484226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2221484226
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1110902515
Short name T650
Test name
Test status
Simulation time 29361698194 ps
CPU time 756.95 seconds
Started Mar 28 02:26:56 PM PDT 24
Finished Mar 28 02:39:34 PM PDT 24
Peak memory 198216 kb
Host smart-7cf71be3-473e-4c83-ab0a-8c2a64be03b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1110902515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1110902515
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1938502132
Short name T691
Test name
Test status
Simulation time 11740975 ps
CPU time 0.58 seconds
Started Mar 28 02:27:16 PM PDT 24
Finished Mar 28 02:27:17 PM PDT 24
Peak memory 193956 kb
Host smart-88e1980e-5955-41ba-aaa5-b5b10aff4215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938502132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1938502132
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.802255141
Short name T17
Test name
Test status
Simulation time 36441569 ps
CPU time 0.75 seconds
Started Mar 28 02:27:12 PM PDT 24
Finished Mar 28 02:27:13 PM PDT 24
Peak memory 195300 kb
Host smart-1c0fd427-a3f2-4d0a-9edc-f164a8c2c071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802255141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.802255141
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2579314129
Short name T233
Test name
Test status
Simulation time 510866606 ps
CPU time 5.45 seconds
Started Mar 28 02:27:09 PM PDT 24
Finished Mar 28 02:27:15 PM PDT 24
Peak memory 196992 kb
Host smart-f3cf1b1b-9abc-4d9e-9434-d1185a2d4365
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579314129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2579314129
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3918572320
Short name T481
Test name
Test status
Simulation time 89231656 ps
CPU time 0.84 seconds
Started Mar 28 02:27:09 PM PDT 24
Finished Mar 28 02:27:10 PM PDT 24
Peak memory 196756 kb
Host smart-8fc2d6c5-5eba-4c85-aae8-1b95d65212ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918572320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3918572320
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1643727543
Short name T282
Test name
Test status
Simulation time 286962079 ps
CPU time 1.22 seconds
Started Mar 28 02:27:09 PM PDT 24
Finished Mar 28 02:27:11 PM PDT 24
Peak memory 196112 kb
Host smart-829468e6-b6b5-41a8-92a7-43a2c5a69e00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643727543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1643727543
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.622858631
Short name T239
Test name
Test status
Simulation time 111140187 ps
CPU time 2.44 seconds
Started Mar 28 02:27:16 PM PDT 24
Finished Mar 28 02:27:18 PM PDT 24
Peak memory 198076 kb
Host smart-896a07b7-7ce5-4371-a5aa-af55c6bd76f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622858631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.622858631
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3406904284
Short name T223
Test name
Test status
Simulation time 247310647 ps
CPU time 1.74 seconds
Started Mar 28 02:27:12 PM PDT 24
Finished Mar 28 02:27:14 PM PDT 24
Peak memory 195796 kb
Host smart-f18b70dd-38b8-4f17-8b7f-0591aa310c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406904284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3406904284
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4241837885
Short name T564
Test name
Test status
Simulation time 133216300 ps
CPU time 0.75 seconds
Started Mar 28 02:27:09 PM PDT 24
Finished Mar 28 02:27:10 PM PDT 24
Peak memory 194480 kb
Host smart-dd185f1e-b5f6-4534-b6ac-b1371a25c48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241837885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4241837885
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4130447729
Short name T351
Test name
Test status
Simulation time 59466512 ps
CPU time 1.17 seconds
Started Mar 28 02:27:10 PM PDT 24
Finished Mar 28 02:27:11 PM PDT 24
Peak memory 196092 kb
Host smart-946e3810-6657-499f-b4f2-05cdc9746ac5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130447729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4130447729
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.940081486
Short name T456
Test name
Test status
Simulation time 218244885 ps
CPU time 1.83 seconds
Started Mar 28 02:27:09 PM PDT 24
Finished Mar 28 02:27:11 PM PDT 24
Peak memory 197972 kb
Host smart-51e330f9-ab52-4080-9494-62c3d94ade89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940081486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.940081486
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2964133442
Short name T477
Test name
Test status
Simulation time 119069758 ps
CPU time 1.27 seconds
Started Mar 28 02:27:11 PM PDT 24
Finished Mar 28 02:27:13 PM PDT 24
Peak memory 196324 kb
Host smart-fd8da2ee-d3bf-4e46-9b53-4b2650bb3550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964133442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2964133442
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3999721532
Short name T678
Test name
Test status
Simulation time 545351154 ps
CPU time 1.15 seconds
Started Mar 28 02:27:08 PM PDT 24
Finished Mar 28 02:27:09 PM PDT 24
Peak memory 196496 kb
Host smart-ad24a949-20dd-4457-8355-8622e4badc1f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999721532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3999721532
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.4285772337
Short name T4
Test name
Test status
Simulation time 48997594316 ps
CPU time 128.02 seconds
Started Mar 28 02:27:12 PM PDT 24
Finished Mar 28 02:29:21 PM PDT 24
Peak memory 198124 kb
Host smart-ec2bb6f6-fa0a-4c87-8935-3401a6bf6c29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285772337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.4285772337
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2224306317
Short name T237
Test name
Test status
Simulation time 15250596 ps
CPU time 0.59 seconds
Started Mar 28 02:27:16 PM PDT 24
Finished Mar 28 02:27:17 PM PDT 24
Peak memory 194144 kb
Host smart-4a57ae88-8f40-43a6-80cb-d24e02b72765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224306317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2224306317
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3547355559
Short name T414
Test name
Test status
Simulation time 33106028 ps
CPU time 0.89 seconds
Started Mar 28 02:27:12 PM PDT 24
Finished Mar 28 02:27:13 PM PDT 24
Peak memory 195996 kb
Host smart-958b68f7-f889-4dde-8634-83655cf94a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547355559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3547355559
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3395536175
Short name T565
Test name
Test status
Simulation time 632700805 ps
CPU time 18.83 seconds
Started Mar 28 02:27:10 PM PDT 24
Finished Mar 28 02:27:30 PM PDT 24
Peak memory 196584 kb
Host smart-211f1126-81f2-4cad-aca3-8edde259dda0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395536175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3395536175
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2692904802
Short name T624
Test name
Test status
Simulation time 198174089 ps
CPU time 0.87 seconds
Started Mar 28 02:27:10 PM PDT 24
Finished Mar 28 02:27:11 PM PDT 24
Peak memory 196928 kb
Host smart-34a683df-4484-4cab-861f-30b990706e70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692904802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2692904802
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2647536071
Short name T217
Test name
Test status
Simulation time 71844112 ps
CPU time 1.13 seconds
Started Mar 28 02:27:09 PM PDT 24
Finished Mar 28 02:27:11 PM PDT 24
Peak memory 196772 kb
Host smart-6dc3d99c-8d68-48e6-9633-42f30e22730c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647536071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2647536071
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.774921660
Short name T640
Test name
Test status
Simulation time 128281139 ps
CPU time 1.45 seconds
Started Mar 28 02:27:14 PM PDT 24
Finished Mar 28 02:27:15 PM PDT 24
Peak memory 196652 kb
Host smart-e7115167-360d-4678-a7e2-61a7babd6e00
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774921660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.774921660
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3666549747
Short name T135
Test name
Test status
Simulation time 48362876 ps
CPU time 1.48 seconds
Started Mar 28 02:27:08 PM PDT 24
Finished Mar 28 02:27:10 PM PDT 24
Peak memory 196520 kb
Host smart-aaab7c52-13cb-4264-b273-65c2168ebcb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666549747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3666549747
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1995622139
Short name T642
Test name
Test status
Simulation time 23295810 ps
CPU time 0.81 seconds
Started Mar 28 02:27:09 PM PDT 24
Finished Mar 28 02:27:10 PM PDT 24
Peak memory 195324 kb
Host smart-9af6e19d-622f-4a15-a6fa-1286a8332d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995622139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1995622139
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2186584057
Short name T437
Test name
Test status
Simulation time 205525969 ps
CPU time 1.3 seconds
Started Mar 28 02:27:10 PM PDT 24
Finished Mar 28 02:27:11 PM PDT 24
Peak memory 196640 kb
Host smart-88d8c536-9a3a-4a53-ab37-b8472d231ffc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186584057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2186584057
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.911219096
Short name T634
Test name
Test status
Simulation time 490458089 ps
CPU time 2.29 seconds
Started Mar 28 02:27:10 PM PDT 24
Finished Mar 28 02:27:13 PM PDT 24
Peak memory 197972 kb
Host smart-e7420099-bac1-4b07-8dd0-5808157e8443
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911219096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.911219096
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1990105567
Short name T302
Test name
Test status
Simulation time 57192866 ps
CPU time 0.91 seconds
Started Mar 28 02:27:16 PM PDT 24
Finished Mar 28 02:27:17 PM PDT 24
Peak memory 196564 kb
Host smart-8be2cdc1-5030-401a-b830-e6752efdf8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990105567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1990105567
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.591004282
Short name T542
Test name
Test status
Simulation time 465860237 ps
CPU time 1.51 seconds
Started Mar 28 02:27:10 PM PDT 24
Finished Mar 28 02:27:13 PM PDT 24
Peak memory 196724 kb
Host smart-9446dfa1-6fb5-43cd-ae40-6e770c7fdad5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591004282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.591004282
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3708530356
Short name T265
Test name
Test status
Simulation time 11762125768 ps
CPU time 155.45 seconds
Started Mar 28 02:27:09 PM PDT 24
Finished Mar 28 02:29:45 PM PDT 24
Peak memory 198132 kb
Host smart-407f5a27-4cdf-4b13-98cc-b9d4d18bde85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708530356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3708530356
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2565272190
Short name T64
Test name
Test status
Simulation time 15153283639 ps
CPU time 382.1 seconds
Started Mar 28 02:27:10 PM PDT 24
Finished Mar 28 02:33:34 PM PDT 24
Peak memory 198324 kb
Host smart-7e42cd35-6e73-49d5-88c4-55da0cf41c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2565272190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2565272190
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.936818312
Short name T443
Test name
Test status
Simulation time 31508772 ps
CPU time 0.57 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 193928 kb
Host smart-da12dd13-7ace-4721-9cc3-0fa2ac10973c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936818312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.936818312
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2748862522
Short name T132
Test name
Test status
Simulation time 91364285 ps
CPU time 0.82 seconds
Started Mar 28 02:27:28 PM PDT 24
Finished Mar 28 02:27:29 PM PDT 24
Peak memory 195460 kb
Host smart-6d4ebed7-b52b-4596-9601-ea83ab62a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748862522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2748862522
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.841095069
Short name T533
Test name
Test status
Simulation time 138048135 ps
CPU time 4.99 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:35 PM PDT 24
Peak memory 196744 kb
Host smart-b717b348-6ea4-4a4d-80ad-d8e337b3805b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841095069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.841095069
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.259308378
Short name T304
Test name
Test status
Simulation time 29125501 ps
CPU time 0.65 seconds
Started Mar 28 02:27:27 PM PDT 24
Finished Mar 28 02:27:28 PM PDT 24
Peak memory 194672 kb
Host smart-0bf8c26c-6a0e-454a-9c86-4c06cff5aeea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259308378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.259308378
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.135521657
Short name T175
Test name
Test status
Simulation time 168369392 ps
CPU time 1.14 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:31 PM PDT 24
Peak memory 195676 kb
Host smart-515447bd-ba78-4332-b1e4-40f17fda7567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135521657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.135521657
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.677190006
Short name T657
Test name
Test status
Simulation time 192206785 ps
CPU time 2.26 seconds
Started Mar 28 02:27:27 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 198136 kb
Host smart-986676b2-3f9c-45ba-812e-b132ddae0679
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677190006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.677190006
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3575846050
Short name T231
Test name
Test status
Simulation time 365532459 ps
CPU time 2.34 seconds
Started Mar 28 02:27:28 PM PDT 24
Finished Mar 28 02:27:31 PM PDT 24
Peak memory 197276 kb
Host smart-e5307378-30ee-4d69-8767-97fee31135f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575846050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3575846050
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3675934676
Short name T200
Test name
Test status
Simulation time 49831150 ps
CPU time 1.18 seconds
Started Mar 28 02:27:31 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 196724 kb
Host smart-9570b332-ca1b-49b1-a710-06f4dba51951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675934676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3675934676
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2327076081
Short name T399
Test name
Test status
Simulation time 87523603 ps
CPU time 0.85 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 194720 kb
Host smart-01061d8b-18f5-42c7-afe5-cebb07be88c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327076081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2327076081
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1381578933
Short name T598
Test name
Test status
Simulation time 86813616 ps
CPU time 1.72 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 197868 kb
Host smart-2ee46f01-4483-4968-a96a-11a12ddb9ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381578933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1381578933
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3563301632
Short name T668
Test name
Test status
Simulation time 58319686 ps
CPU time 1.25 seconds
Started Mar 28 02:27:11 PM PDT 24
Finished Mar 28 02:27:13 PM PDT 24
Peak memory 196216 kb
Host smart-c2c2375c-ea02-4ab5-a0ac-197bda12535d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563301632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3563301632
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.711444735
Short name T270
Test name
Test status
Simulation time 83141985 ps
CPU time 1.1 seconds
Started Mar 28 02:27:16 PM PDT 24
Finished Mar 28 02:27:18 PM PDT 24
Peak memory 196448 kb
Host smart-70517492-7724-4252-a2f2-70ed3aeaecfa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711444735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.711444735
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3718392007
Short name T61
Test name
Test status
Simulation time 53648020105 ps
CPU time 70.38 seconds
Started Mar 28 02:27:28 PM PDT 24
Finished Mar 28 02:28:39 PM PDT 24
Peak memory 198220 kb
Host smart-9ff8d6a8-ca57-4e70-ae21-1c24c9001170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718392007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3718392007
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1150552785
Short name T68
Test name
Test status
Simulation time 21418675731 ps
CPU time 656.9 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:38:28 PM PDT 24
Peak memory 198224 kb
Host smart-6a6ba239-be08-465b-9e8b-8ec17faf37d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1150552785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1150552785
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3397894786
Short name T576
Test name
Test status
Simulation time 14328074 ps
CPU time 0.6 seconds
Started Mar 28 02:24:25 PM PDT 24
Finished Mar 28 02:24:26 PM PDT 24
Peak memory 193828 kb
Host smart-382e8966-4e60-4b52-8331-10310ac7e1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397894786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3397894786
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3096787136
Short name T322
Test name
Test status
Simulation time 165458943 ps
CPU time 0.97 seconds
Started Mar 28 02:24:07 PM PDT 24
Finished Mar 28 02:24:08 PM PDT 24
Peak memory 197184 kb
Host smart-d03df4fa-cf9e-4ac3-9ba3-836876d36e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096787136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3096787136
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.241261924
Short name T655
Test name
Test status
Simulation time 3172510354 ps
CPU time 20.39 seconds
Started Mar 28 02:24:07 PM PDT 24
Finished Mar 28 02:24:27 PM PDT 24
Peak memory 196652 kb
Host smart-3afa07d6-3620-42c8-ab8d-89b575b33919
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241261924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.241261924
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2334038171
Short name T543
Test name
Test status
Simulation time 52110940 ps
CPU time 0.8 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:24:25 PM PDT 24
Peak memory 195976 kb
Host smart-7b967b6e-07ba-4317-bc64-f60ec778b18a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334038171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2334038171
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2069114011
Short name T671
Test name
Test status
Simulation time 177506414 ps
CPU time 1.29 seconds
Started Mar 28 02:24:07 PM PDT 24
Finished Mar 28 02:24:08 PM PDT 24
Peak memory 195788 kb
Host smart-64b97aac-5ce1-4b53-912d-2bbfa85af092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069114011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2069114011
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.589944446
Short name T486
Test name
Test status
Simulation time 74863654 ps
CPU time 3.27 seconds
Started Mar 28 02:24:04 PM PDT 24
Finished Mar 28 02:24:08 PM PDT 24
Peak memory 197924 kb
Host smart-8e1cfbda-9619-4adb-8de8-bda0b5a16160
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589944446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.589944446
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1888380733
Short name T145
Test name
Test status
Simulation time 131513593 ps
CPU time 0.91 seconds
Started Mar 28 02:24:08 PM PDT 24
Finished Mar 28 02:24:09 PM PDT 24
Peak memory 194516 kb
Host smart-a339712d-47fd-4f86-aeee-dae90477d01b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888380733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1888380733
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.683997793
Short name T187
Test name
Test status
Simulation time 59822521 ps
CPU time 0.73 seconds
Started Mar 28 02:24:06 PM PDT 24
Finished Mar 28 02:24:07 PM PDT 24
Peak memory 196180 kb
Host smart-88bef56f-3bfe-444d-996d-af71a13964d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683997793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.683997793
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.256048582
Short name T662
Test name
Test status
Simulation time 23032613 ps
CPU time 0.91 seconds
Started Mar 28 02:24:07 PM PDT 24
Finished Mar 28 02:24:08 PM PDT 24
Peak memory 195824 kb
Host smart-7eb0ea0d-b6ed-40db-8dc5-dfe9ebb8617c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256048582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.256048582
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2496723648
Short name T371
Test name
Test status
Simulation time 261592237 ps
CPU time 1.69 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:24:26 PM PDT 24
Peak memory 197960 kb
Host smart-67b69a59-82ee-4cdf-a959-83df51565974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496723648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2496723648
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1296411207
Short name T42
Test name
Test status
Simulation time 591966297 ps
CPU time 0.96 seconds
Started Mar 28 02:24:26 PM PDT 24
Finished Mar 28 02:24:27 PM PDT 24
Peak memory 214904 kb
Host smart-4da781fb-bb6a-4e40-ae5e-87d3b7163aab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296411207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1296411207
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.338571041
Short name T125
Test name
Test status
Simulation time 238817349 ps
CPU time 1.27 seconds
Started Mar 28 02:24:07 PM PDT 24
Finished Mar 28 02:24:08 PM PDT 24
Peak memory 196452 kb
Host smart-a8f4405b-ac70-4eac-8a2d-4ab9cc3e57bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338571041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.338571041
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1113119121
Short name T513
Test name
Test status
Simulation time 216940995 ps
CPU time 1.12 seconds
Started Mar 28 02:24:08 PM PDT 24
Finished Mar 28 02:24:10 PM PDT 24
Peak memory 195604 kb
Host smart-ca9420a2-38a0-4699-9cee-5b681adf9c10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113119121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1113119121
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2597988278
Short name T555
Test name
Test status
Simulation time 9007201628 ps
CPU time 100.56 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:26:05 PM PDT 24
Peak memory 198164 kb
Host smart-0170654a-50f4-410d-8b09-0b5b5922ba2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597988278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2597988278
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.675544190
Short name T66
Test name
Test status
Simulation time 408178480833 ps
CPU time 358.86 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:30:23 PM PDT 24
Peak memory 206440 kb
Host smart-d23d2722-0008-4482-ad01-87ff7c77ce72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=675544190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.675544190
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.342290556
Short name T493
Test name
Test status
Simulation time 77684695 ps
CPU time 0.57 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 195596 kb
Host smart-99636f98-d88a-442d-9e25-0be8aa12578f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342290556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.342290556
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2017002567
Short name T286
Test name
Test status
Simulation time 15781765 ps
CPU time 0.59 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:30 PM PDT 24
Peak memory 194576 kb
Host smart-29061e21-f9eb-4a70-be19-b30776cafb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017002567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2017002567
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.993097859
Short name T361
Test name
Test status
Simulation time 4674596906 ps
CPU time 6.97 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:37 PM PDT 24
Peak memory 196600 kb
Host smart-29a07453-aeb2-4906-a11a-941b16b70184
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993097859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.993097859
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1032685489
Short name T704
Test name
Test status
Simulation time 58428804 ps
CPU time 1.01 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:31 PM PDT 24
Peak memory 197828 kb
Host smart-4036e9e4-5a5c-4076-b014-67f0b1996420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032685489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1032685489
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3608884789
Short name T417
Test name
Test status
Simulation time 96828570 ps
CPU time 1.44 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:31 PM PDT 24
Peak memory 197160 kb
Host smart-4c831266-48bf-4b37-842e-628a8f1d7260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608884789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3608884789
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.171980242
Short name T292
Test name
Test status
Simulation time 68668837 ps
CPU time 2.64 seconds
Started Mar 28 02:27:26 PM PDT 24
Finished Mar 28 02:27:29 PM PDT 24
Peak memory 198132 kb
Host smart-e82a5efd-410a-41f5-90b7-14a26f085285
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171980242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.171980242
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2546485312
Short name T522
Test name
Test status
Simulation time 414959042 ps
CPU time 3.12 seconds
Started Mar 28 02:27:31 PM PDT 24
Finished Mar 28 02:27:36 PM PDT 24
Peak memory 195816 kb
Host smart-f2ba847e-cd23-4a5e-b509-382aa72df08a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546485312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2546485312
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.417040219
Short name T301
Test name
Test status
Simulation time 58440887 ps
CPU time 1.01 seconds
Started Mar 28 02:27:26 PM PDT 24
Finished Mar 28 02:27:28 PM PDT 24
Peak memory 195980 kb
Host smart-1b705e30-9011-4613-8e2f-011d1eeff093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417040219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.417040219
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3840957632
Short name T461
Test name
Test status
Simulation time 137447128 ps
CPU time 1.31 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 198136 kb
Host smart-1494e47d-0139-4198-b257-ab2751166140
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840957632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3840957632
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.840442820
Short name T473
Test name
Test status
Simulation time 267654089 ps
CPU time 4.67 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:35 PM PDT 24
Peak memory 197464 kb
Host smart-ce688406-1fb8-4208-ab21-72e8ea5f7c82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840442820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.840442820
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.307011297
Short name T126
Test name
Test status
Simulation time 145092120 ps
CPU time 0.95 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 194276 kb
Host smart-7b1a0a4e-4f44-4ba3-8335-e2bd772b56ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307011297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.307011297
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3517649496
Short name T170
Test name
Test status
Simulation time 71878568 ps
CPU time 0.75 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 195984 kb
Host smart-ce2f51fb-e342-45ae-8100-8f8f51fe0723
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517649496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3517649496
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.870074583
Short name T551
Test name
Test status
Simulation time 15483215416 ps
CPU time 40.04 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:28:10 PM PDT 24
Peak memory 197932 kb
Host smart-ac280182-d423-4965-b195-d0098d2c413d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870074583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.870074583
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1903949199
Short name T120
Test name
Test status
Simulation time 12953632 ps
CPU time 0.57 seconds
Started Mar 28 02:27:47 PM PDT 24
Finished Mar 28 02:27:48 PM PDT 24
Peak memory 193756 kb
Host smart-24efcd00-6c9d-4249-ae34-65da19f41561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903949199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1903949199
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.267855662
Short name T583
Test name
Test status
Simulation time 122145434 ps
CPU time 0.87 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:31 PM PDT 24
Peak memory 196564 kb
Host smart-adc9d2df-609b-46e8-8b8d-4a9b2def50fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267855662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.267855662
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1274426431
Short name T607
Test name
Test status
Simulation time 1761282784 ps
CPU time 24.7 seconds
Started Mar 28 02:27:28 PM PDT 24
Finished Mar 28 02:27:53 PM PDT 24
Peak memory 196944 kb
Host smart-c6a4dee2-9dd0-4883-a64f-154aa18faa21
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274426431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1274426431
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1139123151
Short name T476
Test name
Test status
Simulation time 55812216 ps
CPU time 0.69 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:46 PM PDT 24
Peak memory 195564 kb
Host smart-7ea84a46-f0c4-4186-8a85-2994f7a4dbcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139123151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1139123151
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1489461149
Short name T587
Test name
Test status
Simulation time 154134602 ps
CPU time 1.38 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:31 PM PDT 24
Peak memory 197168 kb
Host smart-3104eca6-b0eb-4508-8ded-dd941682b1eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489461149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1489461149
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4081243213
Short name T224
Test name
Test status
Simulation time 81473578 ps
CPU time 3.34 seconds
Started Mar 28 02:27:30 PM PDT 24
Finished Mar 28 02:27:34 PM PDT 24
Peak memory 198084 kb
Host smart-2dcad0c3-e35a-4259-ace7-40e56e6385b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081243213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4081243213
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3321825698
Short name T159
Test name
Test status
Simulation time 612973370 ps
CPU time 3.83 seconds
Started Mar 28 02:27:42 PM PDT 24
Finished Mar 28 02:27:46 PM PDT 24
Peak memory 198040 kb
Host smart-71da3d0c-b0ba-4fd6-abca-886d41760edc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321825698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3321825698
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3975960536
Short name T460
Test name
Test status
Simulation time 185605291 ps
CPU time 0.71 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:31 PM PDT 24
Peak memory 195436 kb
Host smart-0c7a999c-0c5f-4f6b-84ce-e4ae7de23623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975960536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3975960536
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1853033781
Short name T490
Test name
Test status
Simulation time 84804363 ps
CPU time 1.12 seconds
Started Mar 28 02:27:29 PM PDT 24
Finished Mar 28 02:27:31 PM PDT 24
Peak memory 196688 kb
Host smart-4c419dbc-9ab2-4481-bda0-05b529eb4330
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853033781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1853033781
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3414334941
Short name T516
Test name
Test status
Simulation time 353897633 ps
CPU time 4.4 seconds
Started Mar 28 02:27:47 PM PDT 24
Finished Mar 28 02:27:51 PM PDT 24
Peak memory 197900 kb
Host smart-5e5618ba-8589-42d0-9130-a622cf76a198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414334941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3414334941
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3589603218
Short name T117
Test name
Test status
Simulation time 95894375 ps
CPU time 0.78 seconds
Started Mar 28 02:27:26 PM PDT 24
Finished Mar 28 02:27:27 PM PDT 24
Peak memory 195168 kb
Host smart-3c45625e-f8af-40b9-ab7c-9530864b2ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589603218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3589603218
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2637953260
Short name T503
Test name
Test status
Simulation time 25903441 ps
CPU time 0.9 seconds
Started Mar 28 02:27:31 PM PDT 24
Finished Mar 28 02:27:32 PM PDT 24
Peak memory 195268 kb
Host smart-2b4fa051-61d8-45a4-9632-3f6a02150501
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637953260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2637953260
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1003315893
Short name T21
Test name
Test status
Simulation time 289723645503 ps
CPU time 192.33 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:30:59 PM PDT 24
Peak memory 198184 kb
Host smart-1e9bb347-241e-47aa-9676-840b017b364d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003315893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1003315893
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3803926540
Short name T354
Test name
Test status
Simulation time 14901355 ps
CPU time 0.56 seconds
Started Mar 28 02:27:48 PM PDT 24
Finished Mar 28 02:27:49 PM PDT 24
Peak memory 193956 kb
Host smart-1c269a46-018a-43b2-a5c7-5f3a75786a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803926540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3803926540
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.34632997
Short name T74
Test name
Test status
Simulation time 147124960 ps
CPU time 0.85 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 195328 kb
Host smart-bb809e9d-56f1-4fe2-9dec-0714609cbb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34632997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.34632997
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3574046289
Short name T82
Test name
Test status
Simulation time 523724086 ps
CPU time 6.37 seconds
Started Mar 28 02:27:48 PM PDT 24
Finished Mar 28 02:27:54 PM PDT 24
Peak memory 196860 kb
Host smart-24bd37e8-944a-4e16-982d-f5c8964f2f65
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574046289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3574046289
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1388371334
Short name T277
Test name
Test status
Simulation time 231433673 ps
CPU time 0.95 seconds
Started Mar 28 02:27:48 PM PDT 24
Finished Mar 28 02:27:49 PM PDT 24
Peak memory 197776 kb
Host smart-1c8b19c7-c20b-4c10-83b6-174718ae4729
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388371334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1388371334
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.554638070
Short name T143
Test name
Test status
Simulation time 37451968 ps
CPU time 1.15 seconds
Started Mar 28 02:27:45 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 196052 kb
Host smart-793d4341-33b5-4189-8f2d-ff8baeb886f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554638070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.554638070
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1968940339
Short name T388
Test name
Test status
Simulation time 132910800 ps
CPU time 2.35 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:48 PM PDT 24
Peak memory 198056 kb
Host smart-02778a77-ab5a-472f-ac18-5d0f1e2f5d57
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968940339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1968940339
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3888214910
Short name T260
Test name
Test status
Simulation time 135337882 ps
CPU time 2.74 seconds
Started Mar 28 02:27:50 PM PDT 24
Finished Mar 28 02:27:53 PM PDT 24
Peak memory 197864 kb
Host smart-10a4ab8e-19dc-4d74-9a2e-2c09f66c01f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888214910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3888214910
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1536963214
Short name T479
Test name
Test status
Simulation time 48162378 ps
CPU time 1.31 seconds
Started Mar 28 02:27:48 PM PDT 24
Finished Mar 28 02:27:49 PM PDT 24
Peak memory 197136 kb
Host smart-ebc60ec0-cf30-4a12-9742-669a01a9b4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536963214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1536963214
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.458914414
Short name T113
Test name
Test status
Simulation time 208439271 ps
CPU time 1.25 seconds
Started Mar 28 02:27:47 PM PDT 24
Finished Mar 28 02:27:49 PM PDT 24
Peak memory 196644 kb
Host smart-e5f8ca4b-4f1e-42b9-b730-c58deaf42953
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458914414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.458914414
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.208670880
Short name T616
Test name
Test status
Simulation time 590324718 ps
CPU time 4.72 seconds
Started Mar 28 02:27:48 PM PDT 24
Finished Mar 28 02:27:53 PM PDT 24
Peak memory 197968 kb
Host smart-04c601dd-05a6-4bf2-9693-daefbaed22de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208670880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.208670880
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.784472266
Short name T190
Test name
Test status
Simulation time 55781792 ps
CPU time 1.12 seconds
Started Mar 28 02:27:45 PM PDT 24
Finished Mar 28 02:27:46 PM PDT 24
Peak memory 196304 kb
Host smart-f447f423-22e4-4065-bfea-2b9f2e8de441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784472266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.784472266
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2834545759
Short name T123
Test name
Test status
Simulation time 42463729 ps
CPU time 0.68 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 194920 kb
Host smart-4c94e99b-1b3c-4d23-83f1-c0c005384d59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834545759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2834545759
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.17459923
Short name T408
Test name
Test status
Simulation time 130238548844 ps
CPU time 81.17 seconds
Started Mar 28 02:27:47 PM PDT 24
Finished Mar 28 02:29:08 PM PDT 24
Peak memory 192048 kb
Host smart-2e243edf-edd6-4f4c-ab64-0eec608a5c5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17459923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gp
io_stress_all.17459923
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1911087579
Short name T664
Test name
Test status
Simulation time 37812911507 ps
CPU time 1154.38 seconds
Started Mar 28 02:27:47 PM PDT 24
Finished Mar 28 02:47:01 PM PDT 24
Peak memory 198320 kb
Host smart-10b46ea5-a66f-4b59-9a2f-d885f8ea4ce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1911087579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1911087579
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2929177525
Short name T480
Test name
Test status
Simulation time 18970756 ps
CPU time 0.53 seconds
Started Mar 28 02:28:20 PM PDT 24
Finished Mar 28 02:28:21 PM PDT 24
Peak memory 192796 kb
Host smart-f0da3ddc-8d28-49b3-911c-f04006b2918f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929177525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2929177525
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2589230161
Short name T505
Test name
Test status
Simulation time 36983828 ps
CPU time 0.67 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 194196 kb
Host smart-13d71aed-54db-458f-8076-b7a2439a7777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589230161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2589230161
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.232842248
Short name T169
Test name
Test status
Simulation time 981461874 ps
CPU time 13.02 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:59 PM PDT 24
Peak memory 197220 kb
Host smart-51d17e13-9b6a-461d-a6af-f5f40926dc2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232842248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.232842248
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3614824730
Short name T345
Test name
Test status
Simulation time 483518486 ps
CPU time 0.88 seconds
Started Mar 28 02:27:47 PM PDT 24
Finished Mar 28 02:27:48 PM PDT 24
Peak memory 196040 kb
Host smart-f63a6762-3b78-4b7a-a6a6-d048818e94b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614824730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3614824730
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3369384497
Short name T172
Test name
Test status
Simulation time 162498346 ps
CPU time 0.83 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 195620 kb
Host smart-96377dbb-7586-4ca6-90c2-4c76c848f101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369384497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3369384497
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2659469217
Short name T248
Test name
Test status
Simulation time 146466063 ps
CPU time 1.62 seconds
Started Mar 28 02:27:45 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 196672 kb
Host smart-e8e641fd-84d5-4d85-a264-0178847f4042
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659469217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2659469217
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.327919102
Short name T377
Test name
Test status
Simulation time 356575353 ps
CPU time 1.73 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:48 PM PDT 24
Peak memory 195980 kb
Host smart-d6298574-2ba3-43fb-86e8-7c488f270eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327919102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
327919102
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1596973508
Short name T269
Test name
Test status
Simulation time 43180762 ps
CPU time 0.78 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 195472 kb
Host smart-057ab981-ad47-4f45-98e2-20202b435ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596973508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1596973508
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2723466902
Short name T398
Test name
Test status
Simulation time 165976948 ps
CPU time 0.84 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 196196 kb
Host smart-240594c3-a818-4873-9da7-d0fecdcae0cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723466902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2723466902
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4116432686
Short name T295
Test name
Test status
Simulation time 586920095 ps
CPU time 2.44 seconds
Started Mar 28 02:27:48 PM PDT 24
Finished Mar 28 02:27:50 PM PDT 24
Peak memory 197984 kb
Host smart-6c8a7552-74ca-4629-8875-7a6edf458a93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116432686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4116432686
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1334849357
Short name T470
Test name
Test status
Simulation time 228228807 ps
CPU time 1.14 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 195892 kb
Host smart-de64607e-9adb-41d8-8935-408f68f9fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334849357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1334849357
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3513683924
Short name T116
Test name
Test status
Simulation time 53278643 ps
CPU time 1.08 seconds
Started Mar 28 02:27:46 PM PDT 24
Finished Mar 28 02:27:47 PM PDT 24
Peak memory 195812 kb
Host smart-4c358973-0ecd-4df0-8268-95a0e788353b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513683924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3513683924
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.204022372
Short name T646
Test name
Test status
Simulation time 59549885975 ps
CPU time 90.61 seconds
Started Mar 28 02:27:49 PM PDT 24
Finished Mar 28 02:29:20 PM PDT 24
Peak memory 198160 kb
Host smart-d86b83b3-842b-4039-bf78-52fdeb8e54dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204022372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.204022372
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.576303868
Short name T575
Test name
Test status
Simulation time 68869705 ps
CPU time 0.57 seconds
Started Mar 28 02:28:16 PM PDT 24
Finished Mar 28 02:28:17 PM PDT 24
Peak memory 193964 kb
Host smart-c511de92-3b7e-4fac-aa47-2bc87215e8fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576303868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.576303868
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3378903753
Short name T213
Test name
Test status
Simulation time 37699207 ps
CPU time 0.9 seconds
Started Mar 28 02:28:16 PM PDT 24
Finished Mar 28 02:28:18 PM PDT 24
Peak memory 196404 kb
Host smart-357f6477-a2d3-42fc-b975-5059ea805238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378903753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3378903753
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.4028624832
Short name T111
Test name
Test status
Simulation time 805499178 ps
CPU time 9.71 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:28 PM PDT 24
Peak memory 198008 kb
Host smart-d58f60e0-a18d-4f08-8b7a-e2db1685b3af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028624832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.4028624832
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3055484717
Short name T412
Test name
Test status
Simulation time 174771123 ps
CPU time 1.05 seconds
Started Mar 28 02:28:17 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 197872 kb
Host smart-d3714f45-b159-45ff-a17b-4a08ed9fec5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055484717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3055484717
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1357257141
Short name T173
Test name
Test status
Simulation time 365530956 ps
CPU time 0.75 seconds
Started Mar 28 02:28:20 PM PDT 24
Finished Mar 28 02:28:21 PM PDT 24
Peak memory 195524 kb
Host smart-9609bc8d-050d-4f5c-bbf8-4ed83d765eae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357257141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1357257141
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3248634879
Short name T69
Test name
Test status
Simulation time 77802468 ps
CPU time 2.79 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:22 PM PDT 24
Peak memory 198052 kb
Host smart-9f851076-0386-4bd0-8adf-628180e913ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248634879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3248634879
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.4208149754
Short name T183
Test name
Test status
Simulation time 290758326 ps
CPU time 3.12 seconds
Started Mar 28 02:28:17 PM PDT 24
Finished Mar 28 02:28:21 PM PDT 24
Peak memory 197224 kb
Host smart-67b44a0c-42e5-49d2-9d23-438385d83341
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208149754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.4208149754
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3446554120
Short name T262
Test name
Test status
Simulation time 34592016 ps
CPU time 0.78 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 196244 kb
Host smart-d4ce8e0d-d2a3-4aab-b493-09405a977fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446554120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3446554120
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.4289903375
Short name T296
Test name
Test status
Simulation time 34827534 ps
CPU time 0.78 seconds
Started Mar 28 02:28:17 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 195556 kb
Host smart-2a8fd14f-ead2-43da-afa5-dff83227992b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289903375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.4289903375
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.700073268
Short name T128
Test name
Test status
Simulation time 404950175 ps
CPU time 4.76 seconds
Started Mar 28 02:28:20 PM PDT 24
Finished Mar 28 02:28:25 PM PDT 24
Peak memory 198004 kb
Host smart-ac6183f8-9b66-425e-bfe1-6f760f2ab7b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700073268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.700073268
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2368346269
Short name T545
Test name
Test status
Simulation time 187613494 ps
CPU time 1.15 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 195768 kb
Host smart-b1669738-64b0-45d4-9e74-58d52cae0649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368346269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2368346269
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3006922576
Short name T495
Test name
Test status
Simulation time 206177552 ps
CPU time 1.12 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 195672 kb
Host smart-769cd8d4-399a-45db-8e8f-765fc711cb66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006922576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3006922576
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.510204229
Short name T140
Test name
Test status
Simulation time 48693345581 ps
CPU time 174.5 seconds
Started Mar 28 02:28:25 PM PDT 24
Finished Mar 28 02:31:20 PM PDT 24
Peak memory 198208 kb
Host smart-bf33c049-c5d1-4496-935a-ea4420683562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510204229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.510204229
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.58315035
Short name T268
Test name
Test status
Simulation time 23147271 ps
CPU time 0.57 seconds
Started Mar 28 02:28:17 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 193868 kb
Host smart-2d9913d1-b7a0-4181-a85a-d9c04ccdf8bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58315035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.58315035
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.532187110
Short name T472
Test name
Test status
Simulation time 41355977 ps
CPU time 0.8 seconds
Started Mar 28 02:28:21 PM PDT 24
Finished Mar 28 02:28:22 PM PDT 24
Peak memory 195976 kb
Host smart-bb684699-6995-4a4c-a3de-fe647f89247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532187110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.532187110
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2668441556
Short name T149
Test name
Test status
Simulation time 692843267 ps
CPU time 8.06 seconds
Started Mar 28 02:28:21 PM PDT 24
Finished Mar 28 02:28:29 PM PDT 24
Peak memory 195528 kb
Host smart-b8eef7b9-0e14-457f-be65-f43828a22bab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668441556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2668441556
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3596111934
Short name T663
Test name
Test status
Simulation time 262225255 ps
CPU time 1.22 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:21 PM PDT 24
Peak memory 196604 kb
Host smart-86bd15ad-85e5-4062-b92e-7bb730c9ada8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596111934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3596111934
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3448355727
Short name T444
Test name
Test status
Simulation time 115473911 ps
CPU time 1.07 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 195972 kb
Host smart-e9636ed9-1e70-410f-a55c-e0dac85947ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448355727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3448355727
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2108483618
Short name T384
Test name
Test status
Simulation time 209847750 ps
CPU time 1.59 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:21 PM PDT 24
Peak memory 196468 kb
Host smart-62fc5381-765a-4717-b081-eb1d107c0c83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108483618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2108483618
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.192723872
Short name T316
Test name
Test status
Simulation time 66877160 ps
CPU time 1.06 seconds
Started Mar 28 02:28:17 PM PDT 24
Finished Mar 28 02:28:18 PM PDT 24
Peak memory 195468 kb
Host smart-36a40b7d-3738-4a7e-93ee-c53fb4eb6b36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192723872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
192723872
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.64870147
Short name T517
Test name
Test status
Simulation time 210445797 ps
CPU time 1.22 seconds
Started Mar 28 02:28:16 PM PDT 24
Finished Mar 28 02:28:17 PM PDT 24
Peak memory 197128 kb
Host smart-6911358d-295d-47f2-ae90-b4d7d62e03cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64870147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.64870147
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3530646528
Short name T341
Test name
Test status
Simulation time 35238124 ps
CPU time 1.21 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 197000 kb
Host smart-f541208e-1045-41a4-968e-c30d47c5f407
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530646528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3530646528
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1313848402
Short name T535
Test name
Test status
Simulation time 945307282 ps
CPU time 3.38 seconds
Started Mar 28 02:28:20 PM PDT 24
Finished Mar 28 02:28:24 PM PDT 24
Peak memory 197992 kb
Host smart-3177fb4c-5ccd-4151-a6af-0af4c77870ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313848402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1313848402
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.226031495
Short name T59
Test name
Test status
Simulation time 351070411 ps
CPU time 1.53 seconds
Started Mar 28 02:28:16 PM PDT 24
Finished Mar 28 02:28:18 PM PDT 24
Peak memory 196832 kb
Host smart-0faaf0e4-d81b-4053-8cae-72fa0520ee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226031495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.226031495
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1897009256
Short name T365
Test name
Test status
Simulation time 35265075 ps
CPU time 0.85 seconds
Started Mar 28 02:28:15 PM PDT 24
Finished Mar 28 02:28:16 PM PDT 24
Peak memory 195956 kb
Host smart-71a677e7-1724-4140-9305-2dd29c6ce290
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897009256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1897009256
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.770951648
Short name T445
Test name
Test status
Simulation time 5662978593 ps
CPU time 89.36 seconds
Started Mar 28 02:28:20 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 198172 kb
Host smart-520661ef-37a8-4612-ae36-293e25a4e937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770951648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.770951648
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1242999196
Short name T383
Test name
Test status
Simulation time 15225216 ps
CPU time 0.59 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 194112 kb
Host smart-cde69696-c2b9-4ef2-98cd-a058243782ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242999196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1242999196
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.574517043
Short name T454
Test name
Test status
Simulation time 23985866 ps
CPU time 0.72 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 195360 kb
Host smart-86caeefd-761a-4f73-84e8-d829fa3520cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574517043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.574517043
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3512362346
Short name T509
Test name
Test status
Simulation time 3045987845 ps
CPU time 26.07 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:45 PM PDT 24
Peak memory 196624 kb
Host smart-90f62dd5-58a2-447b-9ac0-9f558e39386e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512362346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3512362346
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.795251663
Short name T20
Test name
Test status
Simulation time 50867159 ps
CPU time 0.8 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 194848 kb
Host smart-17b60451-599d-42d1-8381-b2873ac26ebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795251663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.795251663
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.620775100
Short name T469
Test name
Test status
Simulation time 1032477644 ps
CPU time 1.3 seconds
Started Mar 28 02:28:21 PM PDT 24
Finished Mar 28 02:28:23 PM PDT 24
Peak memory 195792 kb
Host smart-8395fb7f-c0d7-4fb7-8a7d-798de841b7bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620775100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.620775100
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.184282372
Short name T458
Test name
Test status
Simulation time 149450929 ps
CPU time 1.68 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 198004 kb
Host smart-b0092f5b-5d32-42c1-8d56-9cb9b34d287a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184282372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.184282372
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2115532765
Short name T15
Test name
Test status
Simulation time 914694507 ps
CPU time 2.91 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:21 PM PDT 24
Peak memory 197984 kb
Host smart-efaf74fa-f641-4db0-802a-97ba38d22544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115532765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2115532765
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.111302706
Short name T283
Test name
Test status
Simulation time 45069398 ps
CPU time 0.75 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 195432 kb
Host smart-028b5208-58e8-49ac-a425-7f7f6a9b9812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111302706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.111302706
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1230685978
Short name T215
Test name
Test status
Simulation time 259197704 ps
CPU time 1.1 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 196768 kb
Host smart-a6d7f5cb-e61e-4f9b-9de1-792d5ab8fbee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230685978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1230685978
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.4097942105
Short name T423
Test name
Test status
Simulation time 58375107 ps
CPU time 2.79 seconds
Started Mar 28 02:28:17 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 197956 kb
Host smart-96e00056-d3fd-4ff2-9401-f36e659e16df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097942105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.4097942105
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.920999617
Short name T547
Test name
Test status
Simulation time 96354847 ps
CPU time 1.18 seconds
Started Mar 28 02:28:18 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 196176 kb
Host smart-bffbe998-aaab-47f9-a8fd-34e3295640ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920999617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.920999617
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.192983268
Short name T373
Test name
Test status
Simulation time 25448996 ps
CPU time 0.89 seconds
Started Mar 28 02:28:19 PM PDT 24
Finished Mar 28 02:28:20 PM PDT 24
Peak memory 197184 kb
Host smart-e81316ee-28c3-4084-956e-23f8d238aa74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192983268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.192983268
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2546739235
Short name T250
Test name
Test status
Simulation time 16381982360 ps
CPU time 226.74 seconds
Started Mar 28 02:28:21 PM PDT 24
Finished Mar 28 02:32:08 PM PDT 24
Peak memory 198224 kb
Host smart-c4a3b642-e6da-41a1-bfa3-a1ef0bd643a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546739235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2546739235
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3134844311
Short name T25
Test name
Test status
Simulation time 17988009 ps
CPU time 0.56 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 193936 kb
Host smart-41cdf520-043e-45fc-bf0d-ca7283a65ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134844311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3134844311
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3660703889
Short name T228
Test name
Test status
Simulation time 23649346 ps
CPU time 0.67 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 194840 kb
Host smart-f58178d0-5374-4e44-9dbf-b7f9b1cac5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660703889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3660703889
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1249932981
Short name T118
Test name
Test status
Simulation time 407263314 ps
CPU time 7.7 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:55 PM PDT 24
Peak memory 198004 kb
Host smart-73d86fee-89c9-4e56-8dff-bf0f442038bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249932981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1249932981
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1025586510
Short name T433
Test name
Test status
Simulation time 1154433134 ps
CPU time 1.01 seconds
Started Mar 28 02:28:43 PM PDT 24
Finished Mar 28 02:28:44 PM PDT 24
Peak memory 196520 kb
Host smart-807eb73f-ae41-40ba-87f4-a80f85b8112b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025586510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1025586510
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2389736996
Short name T482
Test name
Test status
Simulation time 94669175 ps
CPU time 1.01 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 196040 kb
Host smart-2ad830a7-d567-4b10-b999-6eafb9155e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389736996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2389736996
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.121580425
Short name T395
Test name
Test status
Simulation time 53776214 ps
CPU time 2.36 seconds
Started Mar 28 02:28:49 PM PDT 24
Finished Mar 28 02:28:52 PM PDT 24
Peak memory 198132 kb
Host smart-168d815b-5586-44ae-8627-fb8b1ea1bd04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121580425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.121580425
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1086274841
Short name T179
Test name
Test status
Simulation time 74170642 ps
CPU time 1.6 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:28:45 PM PDT 24
Peak memory 196044 kb
Host smart-a7e4754d-b88b-4062-9104-b27cf2d3db83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086274841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1086274841
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3832570694
Short name T164
Test name
Test status
Simulation time 84714876 ps
CPU time 1.11 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:48 PM PDT 24
Peak memory 196988 kb
Host smart-09cfca53-c38e-495b-8305-87a8f1483ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832570694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3832570694
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.392179115
Short name T13
Test name
Test status
Simulation time 26443584 ps
CPU time 0.75 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:47 PM PDT 24
Peak memory 195392 kb
Host smart-0a8075b7-2e0c-43bc-aa3a-fee61aa93761
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392179115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.392179115
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3359546005
Short name T464
Test name
Test status
Simulation time 1053852354 ps
CPU time 6.06 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:28:55 PM PDT 24
Peak memory 197916 kb
Host smart-76383196-e293-45cf-8274-ec75339f9844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359546005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3359546005
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2415618933
Short name T428
Test name
Test status
Simulation time 239437556 ps
CPU time 1 seconds
Started Mar 28 02:28:17 PM PDT 24
Finished Mar 28 02:28:19 PM PDT 24
Peak memory 195772 kb
Host smart-6b570a96-77d7-47a0-943f-e26e328a9189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415618933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2415618933
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4070134710
Short name T584
Test name
Test status
Simulation time 32124013 ps
CPU time 1.03 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 196396 kb
Host smart-303d1663-48d2-4b9f-acea-e3fe058bf536
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070134710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4070134710
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1204868783
Short name T33
Test name
Test status
Simulation time 22539032331 ps
CPU time 184.23 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:31:49 PM PDT 24
Peak memory 198092 kb
Host smart-dcc3d2f7-9221-41a2-a3d6-7f2b6fb4e1d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204868783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1204868783
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.4177541469
Short name T63
Test name
Test status
Simulation time 92279305489 ps
CPU time 1109.32 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:47:17 PM PDT 24
Peak memory 198224 kb
Host smart-4b1ed32d-ca2f-457f-8818-aa9fcdfd3143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4177541469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.4177541469
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.721346443
Short name T651
Test name
Test status
Simulation time 15328416 ps
CPU time 0.59 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:28:44 PM PDT 24
Peak memory 194860 kb
Host smart-c8be3226-f104-420a-a2a9-3f227d7a65c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721346443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.721346443
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.762615911
Short name T424
Test name
Test status
Simulation time 77929085 ps
CPU time 0.93 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 196680 kb
Host smart-299919eb-a3d8-4e10-bc5a-c71dba9f2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762615911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.762615911
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3387236520
Short name T202
Test name
Test status
Simulation time 1900994922 ps
CPU time 24.9 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:29:14 PM PDT 24
Peak memory 197996 kb
Host smart-10d52a2f-868e-42ce-9086-77609d1ac352
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387236520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3387236520
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.306334261
Short name T440
Test name
Test status
Simulation time 756573313 ps
CPU time 0.81 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 196424 kb
Host smart-437622cf-3a9c-415f-8f50-586cdc0622ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306334261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.306334261
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3814330223
Short name T467
Test name
Test status
Simulation time 371550507 ps
CPU time 1.41 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 197992 kb
Host smart-c84b097a-83a7-4635-89b9-4995b6881278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814330223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3814330223
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1378314170
Short name T238
Test name
Test status
Simulation time 135897433 ps
CPU time 1.16 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:28:45 PM PDT 24
Peak memory 197888 kb
Host smart-aee2ccda-6399-4a00-904a-c27cf92c8307
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378314170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1378314170
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4233699906
Short name T273
Test name
Test status
Simulation time 362904713 ps
CPU time 2.85 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:28:47 PM PDT 24
Peak memory 197040 kb
Host smart-06d319f7-8d31-493e-b4fd-21130bf75aea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233699906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4233699906
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3028410892
Short name T612
Test name
Test status
Simulation time 42308380 ps
CPU time 0.89 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:48 PM PDT 24
Peak memory 195888 kb
Host smart-a0267ba3-45b6-4032-98f9-4a55b5d530b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028410892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3028410892
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2370533059
Short name T496
Test name
Test status
Simulation time 30839336 ps
CPU time 1.2 seconds
Started Mar 28 02:28:54 PM PDT 24
Finished Mar 28 02:28:55 PM PDT 24
Peak memory 196560 kb
Host smart-30404366-c3e2-499d-986f-f77522c9f607
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370533059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2370533059
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1005699094
Short name T426
Test name
Test status
Simulation time 930220482 ps
CPU time 6.25 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:52 PM PDT 24
Peak memory 197948 kb
Host smart-12be932b-a1e8-4b2c-bf0a-46860c347fd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005699094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1005699094
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2092832618
Short name T682
Test name
Test status
Simulation time 124293720 ps
CPU time 1.2 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 196428 kb
Host smart-5afebbfe-5e1e-4373-862c-8f9c73365515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092832618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2092832618
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2332263743
Short name T352
Test name
Test status
Simulation time 105552226 ps
CPU time 1.38 seconds
Started Mar 28 02:28:43 PM PDT 24
Finished Mar 28 02:28:45 PM PDT 24
Peak memory 197900 kb
Host smart-5db25673-7b60-4775-89d8-99d74c117997
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332263743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2332263743
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.415633556
Short name T300
Test name
Test status
Simulation time 3047664794 ps
CPU time 80.13 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:30:08 PM PDT 24
Peak memory 198000 kb
Host smart-3418a4a5-72cf-42d5-9b8c-b586d5a0036b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415633556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.415633556
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1061310012
Short name T687
Test name
Test status
Simulation time 51626707 ps
CPU time 0.56 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 194848 kb
Host smart-e72f2c2a-bf41-47d0-a15d-e3566419ab3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061310012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1061310012
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3400545005
Short name T357
Test name
Test status
Simulation time 36494200 ps
CPU time 0.96 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:48 PM PDT 24
Peak memory 196464 kb
Host smart-75d3e998-d21b-4437-bed2-72eca6a0c7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400545005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3400545005
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2518555556
Short name T344
Test name
Test status
Simulation time 1983435418 ps
CPU time 17.51 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:29:05 PM PDT 24
Peak memory 196428 kb
Host smart-125cfd23-f03b-4374-a3b6-b769fd4554aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518555556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2518555556
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1596501030
Short name T698
Test name
Test status
Simulation time 227350044 ps
CPU time 0.88 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:47 PM PDT 24
Peak memory 197216 kb
Host smart-1747352c-d9be-476e-950a-09c3e92ff29b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596501030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1596501030
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.500644757
Short name T560
Test name
Test status
Simulation time 77057980 ps
CPU time 1.25 seconds
Started Mar 28 02:28:43 PM PDT 24
Finished Mar 28 02:28:45 PM PDT 24
Peak memory 196648 kb
Host smart-2e2978c3-9950-42de-882e-487d21e6d156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500644757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.500644757
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2601855877
Short name T530
Test name
Test status
Simulation time 48427008 ps
CPU time 2.12 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 198100 kb
Host smart-c0a09e8b-14f8-455c-bee6-f5b10dc25008
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601855877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2601855877
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1764186831
Short name T637
Test name
Test status
Simulation time 99042600 ps
CPU time 1.61 seconds
Started Mar 28 02:28:49 PM PDT 24
Finished Mar 28 02:28:51 PM PDT 24
Peak memory 195816 kb
Host smart-318cfd2b-1212-4e6f-b435-3359ac151417
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764186831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1764186831
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1370949890
Short name T550
Test name
Test status
Simulation time 170283221 ps
CPU time 1.04 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 195804 kb
Host smart-046e03dc-2d3b-4a3d-a4b5-47e0ef0f25a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370949890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1370949890
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1725508359
Short name T438
Test name
Test status
Simulation time 24465833 ps
CPU time 0.67 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:48 PM PDT 24
Peak memory 194212 kb
Host smart-e04f8728-d588-46fe-b1dd-0cd03d181ae5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725508359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1725508359
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1536743332
Short name T245
Test name
Test status
Simulation time 265290538 ps
CPU time 4.7 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:28:54 PM PDT 24
Peak memory 197932 kb
Host smart-d7d86df9-a87c-447e-a850-30c8d298d1b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536743332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1536743332
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.503311397
Short name T347
Test name
Test status
Simulation time 396235572 ps
CPU time 0.92 seconds
Started Mar 28 02:28:43 PM PDT 24
Finished Mar 28 02:28:44 PM PDT 24
Peak memory 195508 kb
Host smart-f0be9467-5e5f-42b0-bcf9-ece0a594985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503311397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.503311397
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3226207886
Short name T166
Test name
Test status
Simulation time 51663339 ps
CPU time 1.05 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:48 PM PDT 24
Peak memory 196508 kb
Host smart-4787ebd3-8ad3-49bb-94b6-aa1cb7245bbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226207886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3226207886
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1628261134
Short name T312
Test name
Test status
Simulation time 28184402281 ps
CPU time 79.75 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:30:06 PM PDT 24
Peak memory 198248 kb
Host smart-e217c6d8-ec83-4a85-87df-a0c9aa38070b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628261134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1628261134
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3420581829
Short name T561
Test name
Test status
Simulation time 28200506 ps
CPU time 0.56 seconds
Started Mar 28 02:24:46 PM PDT 24
Finished Mar 28 02:24:47 PM PDT 24
Peak memory 193940 kb
Host smart-bd46465a-9eed-4a45-9397-d0fb4fc4bc51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420581829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3420581829
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2138137226
Short name T677
Test name
Test status
Simulation time 29410435 ps
CPU time 0.91 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:24:25 PM PDT 24
Peak memory 196592 kb
Host smart-7499a1c4-91c0-43a5-842e-6c5b6fc9cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138137226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2138137226
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.4129342376
Short name T161
Test name
Test status
Simulation time 1481640206 ps
CPU time 11.57 seconds
Started Mar 28 02:24:23 PM PDT 24
Finished Mar 28 02:24:35 PM PDT 24
Peak memory 196812 kb
Host smart-2e13be39-2613-4dee-9455-1c9148e30be8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129342376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.4129342376
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.893636823
Short name T569
Test name
Test status
Simulation time 24650450 ps
CPU time 0.7 seconds
Started Mar 28 02:24:27 PM PDT 24
Finished Mar 28 02:24:28 PM PDT 24
Peak memory 194576 kb
Host smart-e9213749-64cb-40d8-ac7e-a77a6fb3de1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893636823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.893636823
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.334287073
Short name T309
Test name
Test status
Simulation time 57242518 ps
CPU time 0.85 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:24:25 PM PDT 24
Peak memory 196192 kb
Host smart-c17cd233-65c8-41ee-a1b2-9c31f9ed4030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334287073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.334287073
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3359642738
Short name T572
Test name
Test status
Simulation time 153185651 ps
CPU time 3.16 seconds
Started Mar 28 02:24:25 PM PDT 24
Finished Mar 28 02:24:28 PM PDT 24
Peak memory 198052 kb
Host smart-2d85dcae-5e67-4645-8aba-b5739520ec35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359642738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3359642738
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1403897136
Short name T339
Test name
Test status
Simulation time 639217421 ps
CPU time 3.35 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:24:27 PM PDT 24
Peak memory 197256 kb
Host smart-2aadea49-4115-40b0-abaf-8cd825cbce05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403897136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1403897136
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2926302283
Short name T391
Test name
Test status
Simulation time 62361548 ps
CPU time 1.34 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:24:26 PM PDT 24
Peak memory 196000 kb
Host smart-7574bd19-c94a-45a1-92e2-2eee157c17ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926302283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2926302283
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1066252343
Short name T611
Test name
Test status
Simulation time 31101424 ps
CPU time 1.11 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:24:25 PM PDT 24
Peak memory 195760 kb
Host smart-218468a8-801d-4f64-b537-42efae0e045d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066252343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1066252343
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1475663317
Short name T418
Test name
Test status
Simulation time 106831863 ps
CPU time 4.6 seconds
Started Mar 28 02:24:24 PM PDT 24
Finished Mar 28 02:24:29 PM PDT 24
Peak memory 197960 kb
Host smart-38348bf8-82fc-4710-b54d-2916ba0bc62b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475663317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1475663317
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.4166304576
Short name T695
Test name
Test status
Simulation time 210783228 ps
CPU time 0.8 seconds
Started Mar 28 02:24:26 PM PDT 24
Finished Mar 28 02:24:27 PM PDT 24
Peak memory 196104 kb
Host smart-0da9b485-1015-4e4f-bedf-04dcc7cd17ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166304576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.4166304576
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3018065670
Short name T206
Test name
Test status
Simulation time 58280585 ps
CPU time 1.34 seconds
Started Mar 28 02:24:25 PM PDT 24
Finished Mar 28 02:24:27 PM PDT 24
Peak memory 195760 kb
Host smart-9f59fc0f-32d2-4f94-9b4c-cd9001a756f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018065670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3018065670
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1377039523
Short name T280
Test name
Test status
Simulation time 107537169088 ps
CPU time 145.71 seconds
Started Mar 28 02:24:25 PM PDT 24
Finished Mar 28 02:26:51 PM PDT 24
Peak memory 198136 kb
Host smart-7c696949-a529-4d31-ac7c-ac2d0826270d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377039523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1377039523
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.853737394
Short name T389
Test name
Test status
Simulation time 22870769 ps
CPU time 0.58 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:28:45 PM PDT 24
Peak memory 194488 kb
Host smart-ce19a9b1-9c36-4d36-8547-7680705ce14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853737394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.853737394
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2770323813
Short name T291
Test name
Test status
Simulation time 31013236 ps
CPU time 0.86 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:47 PM PDT 24
Peak memory 196636 kb
Host smart-ade61272-fe75-4c2c-a757-4dfcacd996c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770323813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2770323813
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3040708884
Short name T197
Test name
Test status
Simulation time 276661592 ps
CPU time 8.26 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:56 PM PDT 24
Peak memory 197144 kb
Host smart-f3941f62-855c-4670-937d-15cb8aecb71c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040708884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3040708884
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3619574632
Short name T211
Test name
Test status
Simulation time 240767363 ps
CPU time 0.95 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:47 PM PDT 24
Peak memory 197304 kb
Host smart-3054c7dc-4308-4f08-9d08-1fec9c6694bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619574632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3619574632
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1723840765
Short name T582
Test name
Test status
Simulation time 21964140 ps
CPU time 0.65 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:48 PM PDT 24
Peak memory 195096 kb
Host smart-6cebbcbe-baa0-4f31-8cac-621956ab61e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723840765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1723840765
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.910874709
Short name T489
Test name
Test status
Simulation time 298937427 ps
CPU time 3.1 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:51 PM PDT 24
Peak memory 196520 kb
Host smart-b7a207dd-3721-43a0-9583-27575e065ec6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910874709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.910874709
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2377593146
Short name T566
Test name
Test status
Simulation time 582355891 ps
CPU time 3.03 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 197208 kb
Host smart-ca4265dd-218d-4ae7-a389-aece90953251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377593146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2377593146
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2070009604
Short name T435
Test name
Test status
Simulation time 22146316 ps
CPU time 0.94 seconds
Started Mar 28 02:28:54 PM PDT 24
Finished Mar 28 02:28:55 PM PDT 24
Peak memory 195960 kb
Host smart-4f43c62e-2222-4aaa-b8b9-06fb6cd9158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070009604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2070009604
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1250483450
Short name T419
Test name
Test status
Simulation time 53554244 ps
CPU time 1.06 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 196568 kb
Host smart-2678eb8d-9e71-4f9a-8c1e-b5b861347cf2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250483450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1250483450
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.873969375
Short name T186
Test name
Test status
Simulation time 673624567 ps
CPU time 3.11 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:28:51 PM PDT 24
Peak memory 198012 kb
Host smart-bb401513-2be4-4e09-a792-c85dfedfc5a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873969375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.873969375
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.306774098
Short name T667
Test name
Test status
Simulation time 32558224 ps
CPU time 0.79 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:28:50 PM PDT 24
Peak memory 195328 kb
Host smart-806d31a4-9f38-4052-af90-e35169abc28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306774098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.306774098
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.578620629
Short name T147
Test name
Test status
Simulation time 42414866 ps
CPU time 0.79 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:47 PM PDT 24
Peak memory 196092 kb
Host smart-c81cb504-29cd-42bc-8332-635cdc886b1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578620629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.578620629
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3887578678
Short name T491
Test name
Test status
Simulation time 2700088404 ps
CPU time 68.94 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:29:57 PM PDT 24
Peak memory 198112 kb
Host smart-88ee3b5c-9930-44f4-a377-265c92af37b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887578678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3887578678
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2787350150
Short name T510
Test name
Test status
Simulation time 11334727 ps
CPU time 0.56 seconds
Started Mar 28 02:29:02 PM PDT 24
Finished Mar 28 02:29:03 PM PDT 24
Peak memory 194664 kb
Host smart-78ea2821-9f7c-4282-a1b2-4af6ad97d8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787350150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2787350150
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2857892432
Short name T577
Test name
Test status
Simulation time 155813282 ps
CPU time 0.94 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 197188 kb
Host smart-4533efac-f28c-413e-bbf6-c303bd2e3e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857892432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2857892432
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1229055385
Short name T253
Test name
Test status
Simulation time 643077775 ps
CPU time 22.87 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:29:11 PM PDT 24
Peak memory 196688 kb
Host smart-a4fccf60-1aa4-4d3a-89a2-3c2bc3ae1de8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229055385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1229055385
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.629359319
Short name T319
Test name
Test status
Simulation time 59147622 ps
CPU time 0.93 seconds
Started Mar 28 02:29:02 PM PDT 24
Finished Mar 28 02:29:03 PM PDT 24
Peak memory 196144 kb
Host smart-9136d9d2-93be-4873-b8b3-845e94a3e337
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629359319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.629359319
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.431141818
Short name T325
Test name
Test status
Simulation time 73010655 ps
CPU time 1.31 seconds
Started Mar 28 02:28:54 PM PDT 24
Finished Mar 28 02:28:55 PM PDT 24
Peak memory 196568 kb
Host smart-972e5cde-835c-4477-be51-2ab9e6db0e78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431141818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.431141818
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2823700496
Short name T207
Test name
Test status
Simulation time 37632590 ps
CPU time 1.57 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 196456 kb
Host smart-3405e844-345e-43cd-9c4e-9820441eddf7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823700496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2823700496
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3251798511
Short name T12
Test name
Test status
Simulation time 168261577 ps
CPU time 3.45 seconds
Started Mar 28 02:28:53 PM PDT 24
Finished Mar 28 02:28:57 PM PDT 24
Peak memory 195604 kb
Host smart-0bf55036-9c62-4414-a7d2-9fd235547c0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251798511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3251798511
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.308385829
Short name T75
Test name
Test status
Simulation time 107077030 ps
CPU time 1.18 seconds
Started Mar 28 02:28:47 PM PDT 24
Finished Mar 28 02:28:49 PM PDT 24
Peak memory 196792 kb
Host smart-089e630b-3875-461c-abde-448855ea6eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308385829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.308385829
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.662018753
Short name T57
Test name
Test status
Simulation time 19310980 ps
CPU time 0.85 seconds
Started Mar 28 02:28:45 PM PDT 24
Finished Mar 28 02:28:46 PM PDT 24
Peak memory 196112 kb
Host smart-c327b989-f327-4be6-93db-2896b3fe952a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662018753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.662018753
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1285571711
Short name T255
Test name
Test status
Simulation time 700759674 ps
CPU time 2.79 seconds
Started Mar 28 02:28:48 PM PDT 24
Finished Mar 28 02:28:51 PM PDT 24
Peak memory 198008 kb
Host smart-070367ba-d5ac-4477-a71a-65256c550495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285571711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1285571711
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2844017856
Short name T168
Test name
Test status
Simulation time 35449501 ps
CPU time 1.29 seconds
Started Mar 28 02:28:44 PM PDT 24
Finished Mar 28 02:28:45 PM PDT 24
Peak memory 197976 kb
Host smart-fdce1f0e-5965-48a7-b9cd-81fddbb47806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844017856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2844017856
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2141192922
Short name T138
Test name
Test status
Simulation time 138563774 ps
CPU time 1.21 seconds
Started Mar 28 02:28:46 PM PDT 24
Finished Mar 28 02:28:48 PM PDT 24
Peak memory 196572 kb
Host smart-5b3de58b-b6d1-4cd3-966a-da5cfa44d401
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141192922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2141192922
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_alert_test.970936726
Short name T298
Test name
Test status
Simulation time 97365229 ps
CPU time 0.57 seconds
Started Mar 28 02:29:19 PM PDT 24
Finished Mar 28 02:29:19 PM PDT 24
Peak memory 193944 kb
Host smart-b9c28a07-96a0-450d-926d-ce9df5ab442e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970936726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.970936726
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3446406298
Short name T506
Test name
Test status
Simulation time 81336997 ps
CPU time 0.83 seconds
Started Mar 28 02:29:05 PM PDT 24
Finished Mar 28 02:29:06 PM PDT 24
Peak memory 195324 kb
Host smart-05dddd0b-1db2-4705-bd7e-bd30e013bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446406298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3446406298
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1244552584
Short name T548
Test name
Test status
Simulation time 758108565 ps
CPU time 13.16 seconds
Started Mar 28 02:29:05 PM PDT 24
Finished Mar 28 02:29:19 PM PDT 24
Peak memory 196976 kb
Host smart-bf933ef0-f184-4c0c-985c-e140ea959b03
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244552584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1244552584
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3669958116
Short name T706
Test name
Test status
Simulation time 178472704 ps
CPU time 1.01 seconds
Started Mar 28 02:29:07 PM PDT 24
Finished Mar 28 02:29:08 PM PDT 24
Peak memory 196676 kb
Host smart-5533941f-d617-4d1a-ab9a-47dc843cf8e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669958116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3669958116
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.4286719503
Short name T645
Test name
Test status
Simulation time 176369355 ps
CPU time 1.41 seconds
Started Mar 28 02:29:06 PM PDT 24
Finished Mar 28 02:29:08 PM PDT 24
Peak memory 196464 kb
Host smart-bc892204-89b1-489e-abe0-fa605af6f3f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286719503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.4286719503
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2570507155
Short name T171
Test name
Test status
Simulation time 280772708 ps
CPU time 3.1 seconds
Started Mar 28 02:29:05 PM PDT 24
Finished Mar 28 02:29:08 PM PDT 24
Peak memory 198064 kb
Host smart-13b2630b-7080-47a5-b148-239f687f6e90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570507155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2570507155
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3354817097
Short name T411
Test name
Test status
Simulation time 86116111 ps
CPU time 0.99 seconds
Started Mar 28 02:29:03 PM PDT 24
Finished Mar 28 02:29:05 PM PDT 24
Peak memory 195812 kb
Host smart-cfbec3f8-0c9a-475f-b5d4-93c8d87fc17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354817097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3354817097
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2771561006
Short name T681
Test name
Test status
Simulation time 64862474 ps
CPU time 1.42 seconds
Started Mar 28 02:29:04 PM PDT 24
Finished Mar 28 02:29:05 PM PDT 24
Peak memory 198108 kb
Host smart-df8ce57f-7e9b-4323-af0d-b60a42e65acc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771561006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2771561006
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3419294287
Short name T410
Test name
Test status
Simulation time 172700219 ps
CPU time 4.2 seconds
Started Mar 28 02:29:04 PM PDT 24
Finished Mar 28 02:29:08 PM PDT 24
Peak memory 197964 kb
Host smart-579ac1d8-6c24-489a-ab62-cdd5f21ce5d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419294287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3419294287
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1517079925
Short name T332
Test name
Test status
Simulation time 58249262 ps
CPU time 0.97 seconds
Started Mar 28 02:29:04 PM PDT 24
Finished Mar 28 02:29:05 PM PDT 24
Peak memory 196468 kb
Host smart-af9b4b76-c46a-4e28-bde7-072f5fc5d3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517079925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1517079925
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3211776976
Short name T337
Test name
Test status
Simulation time 152960472 ps
CPU time 1.33 seconds
Started Mar 28 02:29:02 PM PDT 24
Finished Mar 28 02:29:04 PM PDT 24
Peak memory 196868 kb
Host smart-ddf81fee-8aeb-4b81-b0b5-5f20ac8c5042
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211776976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3211776976
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.609730694
Short name T6
Test name
Test status
Simulation time 36691762081 ps
CPU time 133.18 seconds
Started Mar 28 02:29:02 PM PDT 24
Finished Mar 28 02:31:16 PM PDT 24
Peak memory 198176 kb
Host smart-c7f6c7f3-1ba6-4bb6-9846-154058226e23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609730694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.609730694
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1620919814
Short name T488
Test name
Test status
Simulation time 96663751748 ps
CPU time 1625.91 seconds
Started Mar 28 02:29:05 PM PDT 24
Finished Mar 28 02:56:11 PM PDT 24
Peak memory 198256 kb
Host smart-227517c0-ec83-446d-a27c-e09ae67cc0c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1620919814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1620919814
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2560710750
Short name T409
Test name
Test status
Simulation time 41025073 ps
CPU time 0.57 seconds
Started Mar 28 02:29:26 PM PDT 24
Finished Mar 28 02:29:27 PM PDT 24
Peak memory 194520 kb
Host smart-f7c1a20f-36b3-421e-a4ef-03c79066d1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560710750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2560710750
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1365361986
Short name T502
Test name
Test status
Simulation time 127451225 ps
CPU time 0.82 seconds
Started Mar 28 02:29:20 PM PDT 24
Finished Mar 28 02:29:21 PM PDT 24
Peak memory 195144 kb
Host smart-85f3d272-a832-498a-ba84-fc5bd79b5063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365361986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1365361986
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2992929063
Short name T56
Test name
Test status
Simulation time 550713052 ps
CPU time 25.32 seconds
Started Mar 28 02:29:23 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 196920 kb
Host smart-202b7ed0-f166-49b9-8810-da395220c21e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992929063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2992929063
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3246131110
Short name T688
Test name
Test status
Simulation time 485118219 ps
CPU time 1.02 seconds
Started Mar 28 02:29:21 PM PDT 24
Finished Mar 28 02:29:22 PM PDT 24
Peak memory 196416 kb
Host smart-079161e8-9dfa-480f-9e2f-11a9ba70ba62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246131110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3246131110
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2696550827
Short name T254
Test name
Test status
Simulation time 52366219 ps
CPU time 1.47 seconds
Started Mar 28 02:29:21 PM PDT 24
Finished Mar 28 02:29:22 PM PDT 24
Peak memory 197144 kb
Host smart-f0a35f30-77d4-4253-965e-05586571adf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696550827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2696550827
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1365801513
Short name T475
Test name
Test status
Simulation time 72639541 ps
CPU time 2.49 seconds
Started Mar 28 02:29:20 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 197792 kb
Host smart-fe2e0fb6-ea68-42e1-b2cd-92958938922f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365801513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1365801513
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3248017398
Short name T478
Test name
Test status
Simulation time 110860817 ps
CPU time 2.94 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:25 PM PDT 24
Peak memory 195760 kb
Host smart-4bee3fe8-b6e9-4655-8efc-96f8e70bcd6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248017398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3248017398
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1368091834
Short name T198
Test name
Test status
Simulation time 24562813 ps
CPU time 1.03 seconds
Started Mar 28 02:29:26 PM PDT 24
Finished Mar 28 02:29:27 PM PDT 24
Peak memory 196736 kb
Host smart-59f2957f-7ed2-4140-8936-f06772f57056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368091834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1368091834
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1001091620
Short name T578
Test name
Test status
Simulation time 120632280 ps
CPU time 0.89 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 196692 kb
Host smart-4f4f7569-2d25-4139-8fd5-a9ead729e501
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001091620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1001091620
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1553959973
Short name T79
Test name
Test status
Simulation time 85230049 ps
CPU time 3.96 seconds
Started Mar 28 02:29:21 PM PDT 24
Finished Mar 28 02:29:25 PM PDT 24
Peak memory 198036 kb
Host smart-4932fa4e-b21f-441e-afad-44e3f08b259e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553959973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1553959973
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.670733487
Short name T636
Test name
Test status
Simulation time 136855483 ps
CPU time 1.34 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 197976 kb
Host smart-afc29290-febb-4e36-b61e-bd67a3125f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670733487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.670733487
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1994157860
Short name T546
Test name
Test status
Simulation time 110193895 ps
CPU time 0.78 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 195232 kb
Host smart-ca42027b-0ae1-4caf-a5d1-3aed3f46a264
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994157860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1994157860
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1192217092
Short name T697
Test name
Test status
Simulation time 4569002220 ps
CPU time 124.6 seconds
Started Mar 28 02:29:21 PM PDT 24
Finished Mar 28 02:31:26 PM PDT 24
Peak memory 198256 kb
Host smart-bdbe7cdd-24a1-4631-820d-58361b2222f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192217092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1192217092
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1815764327
Short name T191
Test name
Test status
Simulation time 38390145 ps
CPU time 0.56 seconds
Started Mar 28 02:29:26 PM PDT 24
Finished Mar 28 02:29:27 PM PDT 24
Peak memory 193940 kb
Host smart-2328e911-83cd-4493-a689-81b682d352f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815764327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1815764327
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3576325757
Short name T11
Test name
Test status
Simulation time 166892273 ps
CPU time 0.89 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 196572 kb
Host smart-07f494d9-8358-4a9c-9a04-71c738c3c686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576325757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3576325757
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2837063429
Short name T571
Test name
Test status
Simulation time 332296208 ps
CPU time 7.69 seconds
Started Mar 28 02:29:26 PM PDT 24
Finished Mar 28 02:29:34 PM PDT 24
Peak memory 196748 kb
Host smart-653896ff-d5ad-4067-8348-10fcd58fc2a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837063429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2837063429
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2513655270
Short name T702
Test name
Test status
Simulation time 27191502 ps
CPU time 0.63 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 195308 kb
Host smart-6b3134ac-581c-4541-ae37-ad6971396ad4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513655270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2513655270
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.688870479
Short name T369
Test name
Test status
Simulation time 124541194 ps
CPU time 0.86 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 196260 kb
Host smart-f3befbe1-7b36-4975-b58d-46bbec3dd338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688870479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.688870479
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1218371967
Short name T447
Test name
Test status
Simulation time 92719602 ps
CPU time 4.02 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:26 PM PDT 24
Peak memory 198064 kb
Host smart-fc79f7a9-13cd-4f7e-96c3-7c7d910b53a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218371967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1218371967
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2743975199
Short name T335
Test name
Test status
Simulation time 92001645 ps
CPU time 2.89 seconds
Started Mar 28 02:29:23 PM PDT 24
Finished Mar 28 02:29:26 PM PDT 24
Peak memory 196996 kb
Host smart-5802b756-53cc-43fe-853a-12c2e0056100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743975199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2743975199
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.899905302
Short name T405
Test name
Test status
Simulation time 108000405 ps
CPU time 0.99 seconds
Started Mar 28 02:29:21 PM PDT 24
Finished Mar 28 02:29:22 PM PDT 24
Peak memory 196648 kb
Host smart-2fcdd385-a61a-4c21-b5e9-5344534041e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899905302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.899905302
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1108061341
Short name T580
Test name
Test status
Simulation time 88073314 ps
CPU time 0.69 seconds
Started Mar 28 02:29:20 PM PDT 24
Finished Mar 28 02:29:21 PM PDT 24
Peak memory 195468 kb
Host smart-ed33ac49-01bf-49c2-b6d8-9d2f3325871e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108061341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1108061341
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.962024567
Short name T649
Test name
Test status
Simulation time 1893810928 ps
CPU time 5.46 seconds
Started Mar 28 02:29:23 PM PDT 24
Finished Mar 28 02:29:29 PM PDT 24
Peak memory 197992 kb
Host smart-9b224d60-3862-474e-bc0b-e78be84d7147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962024567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.962024567
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3261214078
Short name T336
Test name
Test status
Simulation time 79272989 ps
CPU time 1.01 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 195244 kb
Host smart-77f5e6d7-a367-4a3d-a06d-90e835eee121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261214078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3261214078
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2427332238
Short name T329
Test name
Test status
Simulation time 195134073 ps
CPU time 1.5 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:23 PM PDT 24
Peak memory 196804 kb
Host smart-bbc7aa8d-2014-45a8-87d1-aa34245d372a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427332238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2427332238
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1699066037
Short name T174
Test name
Test status
Simulation time 3606026709 ps
CPU time 55.56 seconds
Started Mar 28 02:29:27 PM PDT 24
Finished Mar 28 02:30:22 PM PDT 24
Peak memory 198168 kb
Host smart-5b276a21-a019-4abf-b37a-05f8b2b0787e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699066037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1699066037
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3680117710
Short name T81
Test name
Test status
Simulation time 216763250326 ps
CPU time 857.53 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:43:40 PM PDT 24
Peak memory 198260 kb
Host smart-77b6337d-fb9d-4e7c-aefa-a91a8a895cf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3680117710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3680117710
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1057273211
Short name T45
Test name
Test status
Simulation time 34190218 ps
CPU time 0.6 seconds
Started Mar 28 02:29:29 PM PDT 24
Finished Mar 28 02:29:29 PM PDT 24
Peak memory 194636 kb
Host smart-c0a4e5db-77d1-4f67-ab2f-1612daaf309d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057273211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1057273211
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2972673501
Short name T252
Test name
Test status
Simulation time 17944799 ps
CPU time 0.64 seconds
Started Mar 28 02:29:23 PM PDT 24
Finished Mar 28 02:29:24 PM PDT 24
Peak memory 194640 kb
Host smart-a86b8d03-afbd-4b31-8414-10f7eb2dbb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972673501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2972673501
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.398224637
Short name T422
Test name
Test status
Simulation time 502660356 ps
CPU time 8.14 seconds
Started Mar 28 02:29:24 PM PDT 24
Finished Mar 28 02:29:32 PM PDT 24
Peak memory 196300 kb
Host smart-2b8b37ec-90eb-4c22-ba96-41af09381470
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398224637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.398224637
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3770758427
Short name T376
Test name
Test status
Simulation time 433988628 ps
CPU time 1.15 seconds
Started Mar 28 02:29:27 PM PDT 24
Finished Mar 28 02:29:28 PM PDT 24
Peak memory 196396 kb
Host smart-2d861f85-0e73-4fa6-bcd2-c6a6afd36113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770758427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3770758427
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3154555678
Short name T690
Test name
Test status
Simulation time 52973982 ps
CPU time 1.32 seconds
Started Mar 28 02:29:22 PM PDT 24
Finished Mar 28 02:29:24 PM PDT 24
Peak memory 195852 kb
Host smart-edd29368-9801-4d88-8381-605efab726a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154555678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3154555678
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.69820422
Short name T594
Test name
Test status
Simulation time 168111973 ps
CPU time 3.64 seconds
Started Mar 28 02:29:21 PM PDT 24
Finished Mar 28 02:29:25 PM PDT 24
Peak memory 198068 kb
Host smart-2d342ad7-08dd-4fc3-a74a-b9c5c5816bef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69820422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.gpio_intr_with_filter_rand_intr_event.69820422
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1719395082
Short name T234
Test name
Test status
Simulation time 133421980 ps
CPU time 2.95 seconds
Started Mar 28 02:29:26 PM PDT 24
Finished Mar 28 02:29:29 PM PDT 24
Peak memory 197204 kb
Host smart-6bd5fdb6-8f36-4716-9982-48803c7d0e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719395082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1719395082
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.375919072
Short name T23
Test name
Test status
Simulation time 86724246 ps
CPU time 1.31 seconds
Started Mar 28 02:29:24 PM PDT 24
Finished Mar 28 02:29:25 PM PDT 24
Peak memory 197056 kb
Host smart-40c95128-e5f3-445d-aac3-9994dfe02cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375919072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.375919072
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3678307856
Short name T144
Test name
Test status
Simulation time 34275972 ps
CPU time 0.88 seconds
Started Mar 28 02:29:26 PM PDT 24
Finished Mar 28 02:29:27 PM PDT 24
Peak memory 197408 kb
Host smart-bdb0a635-05ef-46ac-be88-64063d25e099
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678307856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3678307856
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.447946822
Short name T27
Test name
Test status
Simulation time 316154019 ps
CPU time 3.38 seconds
Started Mar 28 02:29:27 PM PDT 24
Finished Mar 28 02:29:30 PM PDT 24
Peak memory 197976 kb
Host smart-f1062212-9227-4be9-8aae-5e05d19cca3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447946822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.447946822
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1463826419
Short name T420
Test name
Test status
Simulation time 289310893 ps
CPU time 1.27 seconds
Started Mar 28 02:29:25 PM PDT 24
Finished Mar 28 02:29:26 PM PDT 24
Peak memory 196812 kb
Host smart-f40a6216-71d4-4d75-a6c5-dba2679e0288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463826419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1463826419
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.340363266
Short name T539
Test name
Test status
Simulation time 80554258 ps
CPU time 1.29 seconds
Started Mar 28 02:29:25 PM PDT 24
Finished Mar 28 02:29:26 PM PDT 24
Peak memory 195508 kb
Host smart-59455e88-31a6-4322-a494-ed93e8c73be9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340363266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.340363266
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1705023004
Short name T279
Test name
Test status
Simulation time 53241585691 ps
CPU time 172.78 seconds
Started Mar 28 02:29:25 PM PDT 24
Finished Mar 28 02:32:18 PM PDT 24
Peak memory 198196 kb
Host smart-8bb4974a-7596-4995-8b6f-cd3bf660fabf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705023004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1705023004
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2117831118
Short name T552
Test name
Test status
Simulation time 748626259482 ps
CPU time 1846.79 seconds
Started Mar 28 02:29:25 PM PDT 24
Finished Mar 28 03:00:12 PM PDT 24
Peak memory 198140 kb
Host smart-4e2cf0cc-2efb-41a8-b5d8-82fdb7445b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2117831118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2117831118
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1001268684
Short name T614
Test name
Test status
Simulation time 59097191 ps
CPU time 0.62 seconds
Started Mar 28 02:29:43 PM PDT 24
Finished Mar 28 02:29:44 PM PDT 24
Peak memory 194200 kb
Host smart-ef199ba9-293a-4e4e-b24a-5f99a1e31069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001268684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1001268684
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2342935374
Short name T705
Test name
Test status
Simulation time 48350256 ps
CPU time 0.81 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:46 PM PDT 24
Peak memory 195304 kb
Host smart-c9cf99f6-de0f-4dbb-8a4e-7f1150677042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342935374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2342935374
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3327449376
Short name T247
Test name
Test status
Simulation time 1422683567 ps
CPU time 10.44 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:56 PM PDT 24
Peak memory 196996 kb
Host smart-34df4067-e164-4f45-9509-52d82b71a9ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327449376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3327449376
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1092952782
Short name T70
Test name
Test status
Simulation time 309245379 ps
CPU time 1.12 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 197868 kb
Host smart-4d4d7eb3-f25c-4c17-9340-1501812bea88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092952782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1092952782
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.683634361
Short name T221
Test name
Test status
Simulation time 210126478 ps
CPU time 1.51 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 197240 kb
Host smart-241afcf9-9c34-4f0b-a9ba-27f92d45e376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683634361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.683634361
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2535900106
Short name T340
Test name
Test status
Simulation time 314472492 ps
CPU time 3.33 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:29:51 PM PDT 24
Peak memory 198032 kb
Host smart-35708135-37be-4b03-8e26-69b43ec429a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535900106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2535900106
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1252787112
Short name T524
Test name
Test status
Simulation time 104605611 ps
CPU time 3.6 seconds
Started Mar 28 02:29:41 PM PDT 24
Finished Mar 28 02:29:46 PM PDT 24
Peak memory 196996 kb
Host smart-3b72dfb5-c675-4d52-a8ce-7d005a842328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252787112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1252787112
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1595373200
Short name T455
Test name
Test status
Simulation time 72201398 ps
CPU time 0.94 seconds
Started Mar 28 02:29:23 PM PDT 24
Finished Mar 28 02:29:24 PM PDT 24
Peak memory 195852 kb
Host smart-3b4a132e-2a0a-4744-98ea-633001341c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595373200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1595373200
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3188464162
Short name T375
Test name
Test status
Simulation time 34095438 ps
CPU time 1.12 seconds
Started Mar 28 02:29:29 PM PDT 24
Finished Mar 28 02:29:30 PM PDT 24
Peak memory 195880 kb
Host smart-18464298-0edf-4ff4-a8ca-37c10f26ab8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188464162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3188464162
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.194678478
Short name T497
Test name
Test status
Simulation time 671221227 ps
CPU time 3.28 seconds
Started Mar 28 02:29:42 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 197940 kb
Host smart-525eb6c9-2c46-4599-b708-665e49cea121
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194678478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.194678478
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3047806999
Short name T436
Test name
Test status
Simulation time 49509906 ps
CPU time 1.23 seconds
Started Mar 28 02:29:27 PM PDT 24
Finished Mar 28 02:29:29 PM PDT 24
Peak memory 196392 kb
Host smart-d86ea48c-b387-40d2-8edf-e8fe36adf925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047806999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3047806999
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.677290766
Short name T29
Test name
Test status
Simulation time 67551026 ps
CPU time 1.2 seconds
Started Mar 28 02:29:27 PM PDT 24
Finished Mar 28 02:29:28 PM PDT 24
Peak memory 195528 kb
Host smart-e120fc9d-5cb6-4f9e-8ad6-ef067fca0a73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677290766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.677290766
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3931702918
Short name T507
Test name
Test status
Simulation time 3157524138 ps
CPU time 37.27 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:30:23 PM PDT 24
Peak memory 198220 kb
Host smart-83a0a35b-7b2f-4c10-98a2-95cfbda26596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931702918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3931702918
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1097862835
Short name T185
Test name
Test status
Simulation time 16613147 ps
CPU time 0.61 seconds
Started Mar 28 02:29:47 PM PDT 24
Finished Mar 28 02:29:48 PM PDT 24
Peak memory 193900 kb
Host smart-72edc2fa-9b51-44b0-a8c4-5f2c0b69afe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097862835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1097862835
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1175338976
Short name T629
Test name
Test status
Simulation time 48526890 ps
CPU time 0.75 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:46 PM PDT 24
Peak memory 195288 kb
Host smart-0b3e5abc-1800-4226-91d4-8174e7320675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175338976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1175338976
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.12816108
Short name T129
Test name
Test status
Simulation time 2639567739 ps
CPU time 18.92 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:30:05 PM PDT 24
Peak memory 196676 kb
Host smart-2bbb5ada-081c-4147-b0b9-9ad311b7bfdb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12816108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress
.12816108
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4090249065
Short name T244
Test name
Test status
Simulation time 57723837 ps
CPU time 0.61 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 194424 kb
Host smart-3d28bc93-2c83-4849-9906-fb29e4e6c462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090249065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4090249065
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2002148715
Short name T628
Test name
Test status
Simulation time 199728489 ps
CPU time 1.49 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 195824 kb
Host smart-f892e94e-2ecd-477b-99c0-0ee02fd3f459
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002148715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2002148715
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1178607070
Short name T362
Test name
Test status
Simulation time 335630809 ps
CPU time 3.59 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:29:50 PM PDT 24
Peak memory 197972 kb
Host smart-22a9845c-c429-4138-8407-4ecb37a5201a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178607070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1178607070
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2689754532
Short name T315
Test name
Test status
Simulation time 93251368 ps
CPU time 2.93 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 198060 kb
Host smart-08c3871a-7f04-4192-b44e-511b47913cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689754532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2689754532
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3165104153
Short name T656
Test name
Test status
Simulation time 50353371 ps
CPU time 0.77 seconds
Started Mar 28 02:29:43 PM PDT 24
Finished Mar 28 02:29:44 PM PDT 24
Peak memory 195540 kb
Host smart-ac04439c-bf69-458d-a0bd-932822a4a5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165104153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3165104153
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3139871929
Short name T403
Test name
Test status
Simulation time 124034909 ps
CPU time 0.87 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:46 PM PDT 24
Peak memory 195584 kb
Host smart-5f0f5c8d-4b0a-4464-88fd-7ed26ab3b27c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139871929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3139871929
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1508557928
Short name T232
Test name
Test status
Simulation time 260121553 ps
CPU time 1.5 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:29:48 PM PDT 24
Peak memory 198036 kb
Host smart-8c509743-a21f-46fe-ac6f-d2604a76898c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508557928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1508557928
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1919551689
Short name T258
Test name
Test status
Simulation time 33118490 ps
CPU time 1.13 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:46 PM PDT 24
Peak memory 195780 kb
Host smart-40e4dd6e-55c1-43d3-b9cf-890448f46415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919551689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1919551689
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.64041744
Short name T308
Test name
Test status
Simulation time 227094955 ps
CPU time 1.09 seconds
Started Mar 28 02:29:43 PM PDT 24
Finished Mar 28 02:29:45 PM PDT 24
Peak memory 195700 kb
Host smart-3e2a21c0-424b-468c-8401-2499dde6c70f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64041744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.64041744
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2031718519
Short name T139
Test name
Test status
Simulation time 53370858888 ps
CPU time 212.72 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:33:19 PM PDT 24
Peak memory 198192 kb
Host smart-d1043d9e-827a-4c2d-aab8-bafd66ae7267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031718519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2031718519
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.414851177
Short name T65
Test name
Test status
Simulation time 41780211066 ps
CPU time 1155.53 seconds
Started Mar 28 02:29:47 PM PDT 24
Finished Mar 28 02:49:03 PM PDT 24
Peak memory 198244 kb
Host smart-9471c964-1a68-4c8f-9abb-7da29e9036f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=414851177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.414851177
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3624629417
Short name T701
Test name
Test status
Simulation time 52674022 ps
CPU time 0.6 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 194160 kb
Host smart-2f6191ef-0dc2-4549-a82c-2765de6ebec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624629417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3624629417
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2262945192
Short name T275
Test name
Test status
Simulation time 54697196 ps
CPU time 0.8 seconds
Started Mar 28 02:29:48 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 195192 kb
Host smart-b2c31f28-2cbd-46c2-8dd5-aec74282bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262945192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2262945192
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.434768941
Short name T266
Test name
Test status
Simulation time 7050931805 ps
CPU time 13.74 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:59 PM PDT 24
Peak memory 196516 kb
Host smart-26f322c8-7120-41e8-a483-47c4289c48d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434768941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.434768941
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2513761640
Short name T679
Test name
Test status
Simulation time 274842934 ps
CPU time 0.97 seconds
Started Mar 28 02:29:47 PM PDT 24
Finished Mar 28 02:29:48 PM PDT 24
Peak memory 197240 kb
Host smart-02f7b49b-4328-4378-b9cc-22568104bbd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513761640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2513761640
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3304361866
Short name T178
Test name
Test status
Simulation time 42309143 ps
CPU time 0.86 seconds
Started Mar 28 02:29:43 PM PDT 24
Finished Mar 28 02:29:44 PM PDT 24
Peak memory 196224 kb
Host smart-cd9e721f-7be0-4ba9-8355-16d85eb9b463
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304361866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3304361866
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2402776595
Short name T430
Test name
Test status
Simulation time 52621342 ps
CPU time 1.18 seconds
Started Mar 28 02:29:48 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 196472 kb
Host smart-c7ad122d-a010-42c5-b2bf-cdb28dd78886
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402776595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2402776595
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2460468762
Short name T122
Test name
Test status
Simulation time 115734237 ps
CPU time 2.21 seconds
Started Mar 28 02:29:48 PM PDT 24
Finished Mar 28 02:29:50 PM PDT 24
Peak memory 195752 kb
Host smart-ef698ee7-7a53-407e-8fdc-4078b5403230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460468762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2460468762
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4034299085
Short name T267
Test name
Test status
Simulation time 32732385 ps
CPU time 1.25 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 196876 kb
Host smart-355cf3c5-63b4-4a00-9e5b-e519e1de2ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034299085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4034299085
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3109844404
Short name T525
Test name
Test status
Simulation time 15572724 ps
CPU time 0.68 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:29:48 PM PDT 24
Peak memory 194320 kb
Host smart-19d815b6-1ef8-4254-b41f-262bf7bf3e28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109844404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3109844404
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3272498030
Short name T534
Test name
Test status
Simulation time 144033549 ps
CPU time 1.98 seconds
Started Mar 28 02:29:48 PM PDT 24
Finished Mar 28 02:29:50 PM PDT 24
Peak memory 197704 kb
Host smart-313d4979-79ea-44d0-8849-b1f3e0e192c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272498030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3272498030
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.896279219
Short name T441
Test name
Test status
Simulation time 48134780 ps
CPU time 1.04 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 196000 kb
Host smart-29c91825-378d-4dbe-bd0a-69391b092139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896279219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.896279219
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1017262900
Short name T483
Test name
Test status
Simulation time 72663151 ps
CPU time 0.85 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 196080 kb
Host smart-1aebb836-476f-49c1-bb0a-2c7567e17dc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017262900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1017262900
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3160705127
Short name T601
Test name
Test status
Simulation time 24161609406 ps
CPU time 101.99 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:31:28 PM PDT 24
Peak memory 198244 kb
Host smart-75992171-bb2c-4b0f-951f-7ffabcf8bef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160705127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3160705127
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.976627640
Short name T613
Test name
Test status
Simulation time 13913866 ps
CPU time 0.57 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:46 PM PDT 24
Peak memory 193864 kb
Host smart-851a7bbc-d6a9-432b-8c89-7af332847618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976627640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.976627640
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.796360335
Short name T595
Test name
Test status
Simulation time 37383276 ps
CPU time 0.78 seconds
Started Mar 28 02:29:47 PM PDT 24
Finished Mar 28 02:29:48 PM PDT 24
Peak memory 194976 kb
Host smart-424bdb82-1353-4ebc-a5b9-5ebdd2156b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796360335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.796360335
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1715533925
Short name T638
Test name
Test status
Simulation time 364650312 ps
CPU time 3.15 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 196416 kb
Host smart-45a1b2e7-3daa-414d-b36a-d1a75187aca4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715533925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1715533925
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1947473508
Short name T321
Test name
Test status
Simulation time 34426424 ps
CPU time 0.71 seconds
Started Mar 28 02:29:50 PM PDT 24
Finished Mar 28 02:29:51 PM PDT 24
Peak memory 194676 kb
Host smart-b2608059-f202-41bf-b82e-651c6f5a0cee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947473508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1947473508
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3311284567
Short name T518
Test name
Test status
Simulation time 86664546 ps
CPU time 1.34 seconds
Started Mar 28 02:29:50 PM PDT 24
Finished Mar 28 02:29:52 PM PDT 24
Peak memory 195892 kb
Host smart-ff5f72c4-0fe1-4005-b9b9-9ea7ed3192ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311284567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3311284567
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3148144342
Short name T559
Test name
Test status
Simulation time 56311406 ps
CPU time 2.33 seconds
Started Mar 28 02:29:50 PM PDT 24
Finished Mar 28 02:29:53 PM PDT 24
Peak memory 198056 kb
Host smart-3034431c-eef6-4548-92f9-9b0968f2b478
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148144342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3148144342
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1337573677
Short name T119
Test name
Test status
Simulation time 176552791 ps
CPU time 3.16 seconds
Started Mar 28 02:29:45 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 195800 kb
Host smart-1d4abfbf-7150-49f4-84fd-653ca5201839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337573677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1337573677
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2278934660
Short name T709
Test name
Test status
Simulation time 27310035 ps
CPU time 0.75 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 195452 kb
Host smart-7f40a95b-ff90-42ec-b810-f0a99d489862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278934660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2278934660
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2375566
Short name T523
Test name
Test status
Simulation time 190553893 ps
CPU time 1.19 seconds
Started Mar 28 02:29:50 PM PDT 24
Finished Mar 28 02:29:51 PM PDT 24
Peak memory 195944 kb
Host smart-23f22003-ec1e-4213-bd38-7cf1c26a9d42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup_p
ulldown.2375566
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3527903087
Short name T287
Test name
Test status
Simulation time 80330279 ps
CPU time 2.63 seconds
Started Mar 28 02:29:50 PM PDT 24
Finished Mar 28 02:29:53 PM PDT 24
Peak memory 197952 kb
Host smart-9a7474ad-9a87-461b-b3a2-e3d4379682b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527903087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3527903087
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1982635995
Short name T532
Test name
Test status
Simulation time 119584609 ps
CPU time 1.07 seconds
Started Mar 28 02:29:48 PM PDT 24
Finished Mar 28 02:29:49 PM PDT 24
Peak memory 195788 kb
Host smart-265db484-5f30-4798-b904-866e6b1b481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982635995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1982635995
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3527197217
Short name T30
Test name
Test status
Simulation time 76678933 ps
CPU time 0.82 seconds
Started Mar 28 02:29:46 PM PDT 24
Finished Mar 28 02:29:47 PM PDT 24
Peak memory 196088 kb
Host smart-03ce65ea-311a-416d-b81e-6c652df380b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527197217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3527197217
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3402565290
Short name T208
Test name
Test status
Simulation time 23649694044 ps
CPU time 155.83 seconds
Started Mar 28 02:29:47 PM PDT 24
Finished Mar 28 02:32:23 PM PDT 24
Peak memory 198116 kb
Host smart-350cd1d4-f2be-41dc-9a8b-83c7f8d22b67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402565290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3402565290
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2824517358
Short name T109
Test name
Test status
Simulation time 45411062 ps
CPU time 0.59 seconds
Started Mar 28 02:24:49 PM PDT 24
Finished Mar 28 02:24:50 PM PDT 24
Peak memory 193932 kb
Host smart-c9eb576a-c352-4c41-91a4-3e4620f11810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824517358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2824517358
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.20666927
Short name T676
Test name
Test status
Simulation time 90359444 ps
CPU time 0.87 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:48 PM PDT 24
Peak memory 195364 kb
Host smart-1fc53740-be9d-4a73-ae2a-cf6dcd41e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20666927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.20666927
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4091396848
Short name T72
Test name
Test status
Simulation time 919631595 ps
CPU time 8.56 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:55 PM PDT 24
Peak memory 196304 kb
Host smart-e7947e10-9549-4616-9320-e4f95c77c20b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091396848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4091396848
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1241200997
Short name T425
Test name
Test status
Simulation time 186020442 ps
CPU time 0.99 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:48 PM PDT 24
Peak memory 195928 kb
Host smart-ef79ae4e-cdda-4427-baf7-5800b549a543
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241200997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1241200997
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1676005477
Short name T674
Test name
Test status
Simulation time 46488773 ps
CPU time 1.05 seconds
Started Mar 28 02:24:49 PM PDT 24
Finished Mar 28 02:24:50 PM PDT 24
Peak memory 196156 kb
Host smart-88c87092-10fe-4c0c-a122-eafe829ab671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676005477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1676005477
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.604112138
Short name T294
Test name
Test status
Simulation time 340594067 ps
CPU time 3.79 seconds
Started Mar 28 02:24:51 PM PDT 24
Finished Mar 28 02:24:55 PM PDT 24
Peak memory 197980 kb
Host smart-a645a1c6-ff67-4f1f-91c7-f95f5e241ac7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604112138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.604112138
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1871995619
Short name T112
Test name
Test status
Simulation time 170186914 ps
CPU time 1.67 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:48 PM PDT 24
Peak memory 196708 kb
Host smart-633412cb-9ffa-4016-b453-2eef901d655d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871995619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1871995619
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3442810564
Short name T356
Test name
Test status
Simulation time 60750231 ps
CPU time 1.61 seconds
Started Mar 28 02:24:46 PM PDT 24
Finished Mar 28 02:24:47 PM PDT 24
Peak memory 197032 kb
Host smart-668cf62b-f849-4c40-b8e3-b3054aa59fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442810564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3442810564
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.4089524827
Short name T210
Test name
Test status
Simulation time 21172259 ps
CPU time 0.9 seconds
Started Mar 28 02:24:46 PM PDT 24
Finished Mar 28 02:24:47 PM PDT 24
Peak memory 196748 kb
Host smart-718cc88d-9251-45f4-b80e-02989ae87082
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089524827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.4089524827
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.145675324
Short name T540
Test name
Test status
Simulation time 61938455 ps
CPU time 3.02 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:50 PM PDT 24
Peak memory 197844 kb
Host smart-ac9797fc-66dd-43e6-ad42-7f1f76b24b6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145675324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.145675324
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.485977222
Short name T43
Test name
Test status
Simulation time 125163872 ps
CPU time 0.77 seconds
Started Mar 28 02:24:48 PM PDT 24
Finished Mar 28 02:24:49 PM PDT 24
Peak memory 213852 kb
Host smart-b6329078-53d7-43dd-80f0-ecf13a60625d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485977222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.485977222
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3279477293
Short name T413
Test name
Test status
Simulation time 87206058 ps
CPU time 0.78 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:48 PM PDT 24
Peak memory 196112 kb
Host smart-e9ad5855-a5b3-45eb-a48d-9d2b5e721cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279477293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3279477293
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.508620066
Short name T60
Test name
Test status
Simulation time 201043658 ps
CPU time 1.53 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:49 PM PDT 24
Peak memory 195472 kb
Host smart-1441971d-0d4b-4f65-9a39-0a6b85a454bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508620066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.508620066
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3726306024
Short name T641
Test name
Test status
Simulation time 19262187936 ps
CPU time 120.16 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:26:47 PM PDT 24
Peak memory 198232 kb
Host smart-f0240e9f-a501-4538-88e2-8cb6d8e3924f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726306024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3726306024
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1556774646
Short name T567
Test name
Test status
Simulation time 48264970 ps
CPU time 0.56 seconds
Started Mar 28 02:29:57 PM PDT 24
Finished Mar 28 02:29:58 PM PDT 24
Peak memory 194644 kb
Host smart-89c32941-535d-4abd-9705-7a494471fadc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556774646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1556774646
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.197925832
Short name T189
Test name
Test status
Simulation time 83779253 ps
CPU time 0.63 seconds
Started Mar 28 02:29:43 PM PDT 24
Finished Mar 28 02:29:44 PM PDT 24
Peak memory 193984 kb
Host smart-cc06711e-1146-4e7f-ba48-8f7c6060abeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197925832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.197925832
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2745407828
Short name T381
Test name
Test status
Simulation time 604520906 ps
CPU time 27.16 seconds
Started Mar 28 02:29:59 PM PDT 24
Finished Mar 28 02:30:26 PM PDT 24
Peak memory 198016 kb
Host smart-cf3e5f89-69ce-48e3-9311-2d6d43d02697
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745407828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2745407828
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2760681031
Short name T492
Test name
Test status
Simulation time 75868616 ps
CPU time 1.12 seconds
Started Mar 28 02:30:00 PM PDT 24
Finished Mar 28 02:30:01 PM PDT 24
Peak memory 196348 kb
Host smart-3b169b92-5276-46ec-8f53-45cc9a6350d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760681031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2760681031
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1889563312
Short name T124
Test name
Test status
Simulation time 18714141 ps
CPU time 0.75 seconds
Started Mar 28 02:29:43 PM PDT 24
Finished Mar 28 02:29:44 PM PDT 24
Peak memory 195520 kb
Host smart-2b3588e3-c0db-4de3-bf1d-e44d12f2a8e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889563312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1889563312
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2448830355
Short name T241
Test name
Test status
Simulation time 62843179 ps
CPU time 2.85 seconds
Started Mar 28 02:30:00 PM PDT 24
Finished Mar 28 02:30:04 PM PDT 24
Peak memory 197984 kb
Host smart-f09816be-99d8-4833-8313-3c6450432491
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448830355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2448830355
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1203008249
Short name T216
Test name
Test status
Simulation time 140134876 ps
CPU time 3.66 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:48 PM PDT 24
Peak memory 197068 kb
Host smart-9907d5e7-3d57-4b49-9219-d2b30cd5f84c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203008249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1203008249
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.495299833
Short name T121
Test name
Test status
Simulation time 66211626 ps
CPU time 0.63 seconds
Started Mar 28 02:29:44 PM PDT 24
Finished Mar 28 02:29:46 PM PDT 24
Peak memory 194980 kb
Host smart-8c2dfaee-a032-4f3b-bd30-e5146c121c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495299833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.495299833
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.49776595
Short name T80
Test name
Test status
Simulation time 761056075 ps
CPU time 1.33 seconds
Started Mar 28 02:29:41 PM PDT 24
Finished Mar 28 02:29:43 PM PDT 24
Peak memory 196644 kb
Host smart-50d4f877-b2c7-4d77-95a2-cfb9f0a81d7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49776595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup_
pulldown.49776595
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2168240643
Short name T7
Test name
Test status
Simulation time 1209365231 ps
CPU time 4.87 seconds
Started Mar 28 02:30:01 PM PDT 24
Finished Mar 28 02:30:07 PM PDT 24
Peak memory 197988 kb
Host smart-e4e4fb99-f634-4853-b0f9-e23020c62d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168240643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2168240643
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2610219215
Short name T165
Test name
Test status
Simulation time 172928141 ps
CPU time 1.59 seconds
Started Mar 28 02:29:42 PM PDT 24
Finished Mar 28 02:29:45 PM PDT 24
Peak memory 198044 kb
Host smart-0c7f08cd-2e97-49a7-8c87-c5e21526ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610219215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2610219215
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2484608018
Short name T686
Test name
Test status
Simulation time 108800015 ps
CPU time 0.81 seconds
Started Mar 28 02:29:43 PM PDT 24
Finished Mar 28 02:29:44 PM PDT 24
Peak memory 195444 kb
Host smart-233bfa4d-c486-4930-be0e-35a36f7c6497
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484608018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2484608018
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.4193539729
Short name T504
Test name
Test status
Simulation time 11079978418 ps
CPU time 45.79 seconds
Started Mar 28 02:30:00 PM PDT 24
Finished Mar 28 02:30:46 PM PDT 24
Peak memory 198140 kb
Host smart-7d8fc94d-d6fe-4e64-86db-8f9e302a2b7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193539729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.4193539729
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2411657535
Short name T605
Test name
Test status
Simulation time 21458489 ps
CPU time 0.55 seconds
Started Mar 28 02:30:03 PM PDT 24
Finished Mar 28 02:30:04 PM PDT 24
Peak memory 193948 kb
Host smart-37ce861e-3e8f-4bbb-8fad-cb15615d97bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411657535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2411657535
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.981154418
Short name T73
Test name
Test status
Simulation time 66756751 ps
CPU time 0.71 seconds
Started Mar 28 02:30:03 PM PDT 24
Finished Mar 28 02:30:04 PM PDT 24
Peak memory 194072 kb
Host smart-2049109e-1935-492e-9e13-2e516121de4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981154418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.981154418
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.661586815
Short name T290
Test name
Test status
Simulation time 547679402 ps
CPU time 15 seconds
Started Mar 28 02:29:58 PM PDT 24
Finished Mar 28 02:30:13 PM PDT 24
Peak memory 196704 kb
Host smart-ba064ef6-20fe-483d-ab94-6bec3f545286
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661586815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.661586815
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2966845306
Short name T306
Test name
Test status
Simulation time 135030135 ps
CPU time 0.94 seconds
Started Mar 28 02:30:00 PM PDT 24
Finished Mar 28 02:30:02 PM PDT 24
Peak memory 196160 kb
Host smart-7d03a0a3-2e58-4b1a-b142-c9906e1c6c19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966845306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2966845306
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3818624364
Short name T115
Test name
Test status
Simulation time 162995813 ps
CPU time 1.36 seconds
Started Mar 28 02:29:58 PM PDT 24
Finished Mar 28 02:30:00 PM PDT 24
Peak memory 196924 kb
Host smart-1a3ea298-bbec-4dfd-8301-a0c6ae65821b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818624364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3818624364
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2202854917
Short name T188
Test name
Test status
Simulation time 72909320 ps
CPU time 3.18 seconds
Started Mar 28 02:29:59 PM PDT 24
Finished Mar 28 02:30:02 PM PDT 24
Peak memory 198068 kb
Host smart-91ff5a8c-e5e7-41ac-8c53-e19f07c2d864
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202854917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2202854917
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.4219610903
Short name T272
Test name
Test status
Simulation time 113157695 ps
CPU time 2.58 seconds
Started Mar 28 02:29:59 PM PDT 24
Finished Mar 28 02:30:02 PM PDT 24
Peak memory 197008 kb
Host smart-19e2f1a5-e7a8-4cb3-96c9-d3709ffcab1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219610903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.4219610903
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.15998844
Short name T368
Test name
Test status
Simulation time 135761471 ps
CPU time 0.9 seconds
Started Mar 28 02:29:59 PM PDT 24
Finished Mar 28 02:30:00 PM PDT 24
Peak memory 196516 kb
Host smart-40ed1c74-c7ad-4487-8483-fdbaa06d2cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15998844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.15998844
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3047914820
Short name T78
Test name
Test status
Simulation time 34078266 ps
CPU time 0.85 seconds
Started Mar 28 02:29:59 PM PDT 24
Finished Mar 28 02:30:00 PM PDT 24
Peak memory 195608 kb
Host smart-70b0e9c8-e213-48e8-af3a-f628a91857c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047914820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3047914820
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.901090277
Short name T184
Test name
Test status
Simulation time 148607481 ps
CPU time 1.66 seconds
Started Mar 28 02:30:01 PM PDT 24
Finished Mar 28 02:30:03 PM PDT 24
Peak memory 197924 kb
Host smart-27241438-04a1-44e1-9136-e08423975f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901090277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.901090277
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3391877457
Short name T487
Test name
Test status
Simulation time 94958735 ps
CPU time 1.1 seconds
Started Mar 28 02:29:59 PM PDT 24
Finished Mar 28 02:30:01 PM PDT 24
Peak memory 195764 kb
Host smart-4d706248-482f-4c1d-a67e-13e762dbb23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391877457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3391877457
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.157152150
Short name T181
Test name
Test status
Simulation time 60839897 ps
CPU time 1.26 seconds
Started Mar 28 02:30:04 PM PDT 24
Finished Mar 28 02:30:05 PM PDT 24
Peak memory 195816 kb
Host smart-58b1c7b6-6cc2-410e-8fe3-e6ca0c55184e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157152150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.157152150
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3844539127
Short name T635
Test name
Test status
Simulation time 7402073538 ps
CPU time 222.95 seconds
Started Mar 28 02:30:00 PM PDT 24
Finished Mar 28 02:33:43 PM PDT 24
Peak memory 198240 kb
Host smart-65c18885-ca66-4aab-93b9-bc3e27b3885e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844539127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3844539127
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2147012183
Short name T643
Test name
Test status
Simulation time 15157698 ps
CPU time 0.61 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 193876 kb
Host smart-109da1bc-d321-4c60-aeef-62787b45b295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147012183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2147012183
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.913191083
Short name T393
Test name
Test status
Simulation time 26771935 ps
CPU time 0.81 seconds
Started Mar 28 02:30:02 PM PDT 24
Finished Mar 28 02:30:03 PM PDT 24
Peak memory 196060 kb
Host smart-8211dc57-baad-491b-809c-ba16829ff1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913191083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.913191083
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2488455508
Short name T448
Test name
Test status
Simulation time 399874436 ps
CPU time 13.85 seconds
Started Mar 28 02:29:59 PM PDT 24
Finished Mar 28 02:30:13 PM PDT 24
Peak memory 196716 kb
Host smart-de02df24-4a69-4991-af75-9c1826950a0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488455508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2488455508
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3520786128
Short name T220
Test name
Test status
Simulation time 96946166 ps
CPU time 1.18 seconds
Started Mar 28 02:30:27 PM PDT 24
Finished Mar 28 02:30:29 PM PDT 24
Peak memory 196588 kb
Host smart-40a2b3d2-7ea0-4a91-b7f4-2b6ad9deb85e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520786128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3520786128
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2382091466
Short name T610
Test name
Test status
Simulation time 140645008 ps
CPU time 1.25 seconds
Started Mar 28 02:30:02 PM PDT 24
Finished Mar 28 02:30:03 PM PDT 24
Peak memory 195784 kb
Host smart-4a89852a-76c1-4e0b-940b-215ecfd328f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382091466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2382091466
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3140329025
Short name T442
Test name
Test status
Simulation time 79699157 ps
CPU time 0.91 seconds
Started Mar 28 02:29:58 PM PDT 24
Finished Mar 28 02:30:00 PM PDT 24
Peak memory 196120 kb
Host smart-0ae70192-7cae-421e-bfa9-8faa7d7327e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140329025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3140329025
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.780320772
Short name T385
Test name
Test status
Simulation time 160492257 ps
CPU time 3.81 seconds
Started Mar 28 02:29:58 PM PDT 24
Finished Mar 28 02:30:03 PM PDT 24
Peak memory 195664 kb
Host smart-d5957060-53ed-494d-8afa-8e61596a1a37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780320772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
780320772
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2333856131
Short name T658
Test name
Test status
Simulation time 120492079 ps
CPU time 1.29 seconds
Started Mar 28 02:29:59 PM PDT 24
Finished Mar 28 02:30:01 PM PDT 24
Peak memory 196540 kb
Host smart-4c3ed606-c0ca-46ea-a4cd-bed4f998ef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333856131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2333856131
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1753396997
Short name T218
Test name
Test status
Simulation time 103701005 ps
CPU time 0.92 seconds
Started Mar 28 02:30:00 PM PDT 24
Finished Mar 28 02:30:01 PM PDT 24
Peak memory 195824 kb
Host smart-7a4ef61f-ecfb-459f-a48b-336a487803fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753396997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1753396997
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2032164340
Short name T199
Test name
Test status
Simulation time 1007743924 ps
CPU time 5.66 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:36 PM PDT 24
Peak memory 197992 kb
Host smart-ddaa8102-2c02-4836-a2aa-c688a417f5fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032164340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2032164340
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.4013706670
Short name T236
Test name
Test status
Simulation time 339517141 ps
CPU time 1.5 seconds
Started Mar 28 02:30:03 PM PDT 24
Finished Mar 28 02:30:05 PM PDT 24
Peak memory 196624 kb
Host smart-dc3c6d1f-70a7-4124-a8c0-311c8ce0c2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013706670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.4013706670
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.296321265
Short name T157
Test name
Test status
Simulation time 187931449 ps
CPU time 1.58 seconds
Started Mar 28 02:29:58 PM PDT 24
Finished Mar 28 02:30:00 PM PDT 24
Peak memory 196284 kb
Host smart-d0a3293a-e5ca-4784-9cef-08348691fcbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296321265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.296321265
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3749389955
Short name T639
Test name
Test status
Simulation time 64879659500 ps
CPU time 140.01 seconds
Started Mar 28 02:30:27 PM PDT 24
Finished Mar 28 02:32:48 PM PDT 24
Peak memory 198200 kb
Host smart-ee2b9e58-7226-46cc-926d-f4e326199d90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749389955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3749389955
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3790515544
Short name T558
Test name
Test status
Simulation time 41040540182 ps
CPU time 684.21 seconds
Started Mar 28 02:30:27 PM PDT 24
Finished Mar 28 02:41:51 PM PDT 24
Peak memory 198268 kb
Host smart-ba8581fe-f169-45b6-a42b-b6cde4d3a705
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3790515544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3790515544
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3206507755
Short name T596
Test name
Test status
Simulation time 46176368 ps
CPU time 0.6 seconds
Started Mar 28 02:30:32 PM PDT 24
Finished Mar 28 02:30:33 PM PDT 24
Peak memory 194140 kb
Host smart-4a63d17f-10d5-408c-89ce-a3ccaa382c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206507755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3206507755
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1894855781
Short name T450
Test name
Test status
Simulation time 36755614 ps
CPU time 0.9 seconds
Started Mar 28 02:30:27 PM PDT 24
Finished Mar 28 02:30:28 PM PDT 24
Peak memory 196188 kb
Host smart-ef918b61-c9df-4f2f-a123-b8862245a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894855781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1894855781
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2403449158
Short name T163
Test name
Test status
Simulation time 380589821 ps
CPU time 13.07 seconds
Started Mar 28 02:30:33 PM PDT 24
Finished Mar 28 02:30:46 PM PDT 24
Peak memory 197104 kb
Host smart-cd113d72-d4af-4844-ad34-5811c9c059da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403449158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2403449158
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1980890685
Short name T24
Test name
Test status
Simulation time 178449252 ps
CPU time 0.94 seconds
Started Mar 28 02:30:32 PM PDT 24
Finished Mar 28 02:30:33 PM PDT 24
Peak memory 196580 kb
Host smart-12994bd4-44bf-4c59-a352-362ef87f6c62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980890685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1980890685
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1458331366
Short name T673
Test name
Test status
Simulation time 169937368 ps
CPU time 2.11 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:32 PM PDT 24
Peak memory 198020 kb
Host smart-2a2cb6f6-d322-4869-8fa7-af9eaaab2fcc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458331366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1458331366
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3650856294
Short name T685
Test name
Test status
Simulation time 212734941 ps
CPU time 1.05 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:30 PM PDT 24
Peak memory 195560 kb
Host smart-1b9bb25a-ecbc-45e4-b0de-8b6916d01aeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650856294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3650856294
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2749557064
Short name T288
Test name
Test status
Simulation time 23596766 ps
CPU time 0.73 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:30 PM PDT 24
Peak memory 194548 kb
Host smart-ca91cb21-e138-420e-a321-4792cc32538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749557064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2749557064
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3590589381
Short name T630
Test name
Test status
Simulation time 25418524 ps
CPU time 0.93 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 196704 kb
Host smart-be22a447-b585-4fa3-affa-a1fef93470b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590589381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3590589381
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1284350264
Short name T242
Test name
Test status
Simulation time 655727801 ps
CPU time 3.54 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:32 PM PDT 24
Peak memory 198000 kb
Host smart-d55a7994-806c-4fa6-96df-c1d4c7735b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284350264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1284350264
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1823098753
Short name T35
Test name
Test status
Simulation time 55506147 ps
CPU time 1.11 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 195480 kb
Host smart-e29e217c-c207-4655-9d6f-a101f1353915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823098753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1823098753
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3409426466
Short name T271
Test name
Test status
Simulation time 18701122 ps
CPU time 0.74 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 194212 kb
Host smart-63d4c83d-fbd1-4375-ae76-22edbb2c414b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409426466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3409426466
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1567832720
Short name T235
Test name
Test status
Simulation time 5169614025 ps
CPU time 119.66 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:32:29 PM PDT 24
Peak memory 198176 kb
Host smart-d28a2bf2-fadb-4587-8dda-0b8e760b2572
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567832720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1567832720
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1244052242
Short name T196
Test name
Test status
Simulation time 21268655 ps
CPU time 0.59 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 194972 kb
Host smart-52c5f507-6e78-46c1-8514-a5ce802f171a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244052242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1244052242
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.376769735
Short name T591
Test name
Test status
Simulation time 21937545 ps
CPU time 0.7 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:30 PM PDT 24
Peak memory 194132 kb
Host smart-5f63e407-6291-4221-9d11-a40210a00eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376769735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.376769735
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2229223400
Short name T617
Test name
Test status
Simulation time 795800741 ps
CPU time 17.87 seconds
Started Mar 28 02:30:32 PM PDT 24
Finished Mar 28 02:30:50 PM PDT 24
Peak memory 197884 kb
Host smart-a3e473ba-7d89-451a-b302-52d9ac821b68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229223400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2229223400
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.735557833
Short name T707
Test name
Test status
Simulation time 116872120 ps
CPU time 1.03 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:32 PM PDT 24
Peak memory 196748 kb
Host smart-5572b911-10c5-4bcc-85cf-947e8d7b6c9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735557833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.735557833
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.824789721
Short name T619
Test name
Test status
Simulation time 70054014 ps
CPU time 1.21 seconds
Started Mar 28 02:30:36 PM PDT 24
Finished Mar 28 02:30:38 PM PDT 24
Peak memory 196104 kb
Host smart-1936d7cb-9fb0-477a-b5d0-86b9b3863391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824789721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.824789721
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2863031520
Short name T317
Test name
Test status
Simulation time 66082715 ps
CPU time 1.47 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 196376 kb
Host smart-d6a922ed-a3c7-4f4b-bb1d-3f7fee309bf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863031520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2863031520
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1961394155
Short name T670
Test name
Test status
Simulation time 345662913 ps
CPU time 3.28 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:34 PM PDT 24
Peak memory 197240 kb
Host smart-ecf394ec-cd0d-43dc-aa6d-b051f92ae593
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961394155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1961394155
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2062853731
Short name T225
Test name
Test status
Simulation time 36829857 ps
CPU time 1.25 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 197032 kb
Host smart-1fbf37e8-0b8d-4a53-9d88-4beb55afa3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062853731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2062853731
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.693360659
Short name T182
Test name
Test status
Simulation time 17437132 ps
CPU time 0.69 seconds
Started Mar 28 02:30:53 PM PDT 24
Finished Mar 28 02:30:55 PM PDT 24
Peak memory 194344 kb
Host smart-4af17d2d-18b9-4ab8-a802-f2d183d1c485
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693360659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.693360659
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2728761604
Short name T528
Test name
Test status
Simulation time 166263523 ps
CPU time 1.64 seconds
Started Mar 28 02:30:32 PM PDT 24
Finished Mar 28 02:30:34 PM PDT 24
Peak memory 198040 kb
Host smart-2757b1d3-06dd-40c1-89e4-11318f5873a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728761604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2728761604
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1214033736
Short name T618
Test name
Test status
Simulation time 52654463 ps
CPU time 1.4 seconds
Started Mar 28 02:30:28 PM PDT 24
Finished Mar 28 02:30:30 PM PDT 24
Peak memory 197972 kb
Host smart-2dbbff38-325e-42f7-a6fc-bac094c77a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214033736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1214033736
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1026446848
Short name T380
Test name
Test status
Simulation time 313427238 ps
CPU time 1.11 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 195788 kb
Host smart-cc890f30-bbf9-4b56-a25e-c27130de3980
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026446848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1026446848
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2198028977
Short name T363
Test name
Test status
Simulation time 36923750054 ps
CPU time 159.57 seconds
Started Mar 28 02:30:34 PM PDT 24
Finished Mar 28 02:33:13 PM PDT 24
Peak memory 198204 kb
Host smart-aa4eeb17-5cbb-4a18-809d-fdc0198901fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198028977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2198028977
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2021831762
Short name T665
Test name
Test status
Simulation time 11381821 ps
CPU time 0.6 seconds
Started Mar 28 02:30:54 PM PDT 24
Finished Mar 28 02:30:55 PM PDT 24
Peak memory 194636 kb
Host smart-20eb6233-a12c-40fe-812a-86eb4d8236d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021831762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2021831762
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2603088519
Short name T588
Test name
Test status
Simulation time 311279296 ps
CPU time 0.96 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 195772 kb
Host smart-b7687180-7607-4dc1-acd9-8688cba412eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603088519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2603088519
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2096449653
Short name T446
Test name
Test status
Simulation time 542670916 ps
CPU time 10.45 seconds
Started Mar 28 02:30:28 PM PDT 24
Finished Mar 28 02:30:39 PM PDT 24
Peak memory 196720 kb
Host smart-fecf352b-05de-4b60-be28-dc74b4e90680
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096449653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2096449653
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1203887588
Short name T342
Test name
Test status
Simulation time 104876688 ps
CPU time 0.71 seconds
Started Mar 28 02:30:28 PM PDT 24
Finished Mar 28 02:30:29 PM PDT 24
Peak memory 195412 kb
Host smart-2fa97c8e-287f-402c-8b56-434fa0506ae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203887588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1203887588
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2757417779
Short name T520
Test name
Test status
Simulation time 204382202 ps
CPU time 0.93 seconds
Started Mar 28 02:30:28 PM PDT 24
Finished Mar 28 02:30:29 PM PDT 24
Peak memory 196880 kb
Host smart-5be2f800-64c5-4bef-a397-89c2cb24df74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757417779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2757417779
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3054159092
Short name T621
Test name
Test status
Simulation time 148075668 ps
CPU time 1.01 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:30 PM PDT 24
Peak memory 196320 kb
Host smart-7a97193d-1908-471b-a7c9-34f9f05ad820
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054159092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3054159092
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.919549901
Short name T281
Test name
Test status
Simulation time 574773091 ps
CPU time 2.5 seconds
Started Mar 28 02:30:27 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 197096 kb
Host smart-b2202b90-750d-4d70-813f-8189b531f21f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919549901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
919549901
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.678005471
Short name T359
Test name
Test status
Simulation time 30910682 ps
CPU time 0.9 seconds
Started Mar 28 02:30:28 PM PDT 24
Finished Mar 28 02:30:29 PM PDT 24
Peak memory 195860 kb
Host smart-ec0db705-2eb9-46f6-a05d-cb8d7e048258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678005471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.678005471
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1927982475
Short name T439
Test name
Test status
Simulation time 178234535 ps
CPU time 0.9 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 196652 kb
Host smart-36e3ef6d-d014-42a6-a40c-d601a84f0834
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927982475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1927982475
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1977412388
Short name T9
Test name
Test status
Simulation time 1417089827 ps
CPU time 4.13 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:34 PM PDT 24
Peak memory 197912 kb
Host smart-af218f53-c893-40cd-8d68-3d15a42b3e17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977412388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1977412388
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.608319499
Short name T406
Test name
Test status
Simulation time 59848993 ps
CPU time 1.09 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 196540 kb
Host smart-e182c191-e82b-47db-8f24-9d40c8739cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608319499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.608319499
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3421370637
Short name T660
Test name
Test status
Simulation time 65041002 ps
CPU time 1.19 seconds
Started Mar 28 02:30:29 PM PDT 24
Finished Mar 28 02:30:31 PM PDT 24
Peak memory 197124 kb
Host smart-62a364c6-eed7-4dd6-b329-a03c08091bf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421370637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3421370637
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2017991713
Short name T22
Test name
Test status
Simulation time 5213499760 ps
CPU time 31.72 seconds
Started Mar 28 02:30:30 PM PDT 24
Finished Mar 28 02:31:02 PM PDT 24
Peak memory 198248 kb
Host smart-fb389a05-7f20-49f8-a351-be5f33c8741c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017991713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2017991713
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3532436285
Short name T696
Test name
Test status
Simulation time 75374185 ps
CPU time 0.58 seconds
Started Mar 28 02:30:46 PM PDT 24
Finished Mar 28 02:30:47 PM PDT 24
Peak memory 194144 kb
Host smart-4b7427ae-28cf-48c4-b95e-de88c9e164a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532436285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3532436285
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3264384656
Short name T563
Test name
Test status
Simulation time 277471526 ps
CPU time 0.67 seconds
Started Mar 28 02:30:52 PM PDT 24
Finished Mar 28 02:30:53 PM PDT 24
Peak memory 194128 kb
Host smart-bf4d526e-c905-4c7b-9878-88e595e2ad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264384656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3264384656
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2892243209
Short name T240
Test name
Test status
Simulation time 443962080 ps
CPU time 14.75 seconds
Started Mar 28 02:30:53 PM PDT 24
Finished Mar 28 02:31:08 PM PDT 24
Peak memory 197024 kb
Host smart-8a49291a-375d-4c10-898d-6d364ea1c888
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892243209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2892243209
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2427217261
Short name T675
Test name
Test status
Simulation time 163315761 ps
CPU time 1.11 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 196388 kb
Host smart-c598c3af-2ac1-4075-9976-2b36d208f465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427217261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2427217261
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2944298496
Short name T573
Test name
Test status
Simulation time 190880755 ps
CPU time 0.97 seconds
Started Mar 28 02:30:48 PM PDT 24
Finished Mar 28 02:30:49 PM PDT 24
Peak memory 196512 kb
Host smart-addad250-c9aa-4aba-a9f3-0b08ea7647d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944298496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2944298496
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1186051810
Short name T581
Test name
Test status
Simulation time 27867118 ps
CPU time 1.22 seconds
Started Mar 28 02:30:47 PM PDT 24
Finished Mar 28 02:30:49 PM PDT 24
Peak memory 197800 kb
Host smart-82521ab0-26b0-4e96-b46e-500de099faad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186051810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1186051810
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.818771213
Short name T429
Test name
Test status
Simulation time 1137932061 ps
CPU time 2.48 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:52 PM PDT 24
Peak memory 197140 kb
Host smart-7c93b649-9e11-454a-baa4-b09cd925e3d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818771213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
818771213
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1446298906
Short name T453
Test name
Test status
Simulation time 106471721 ps
CPU time 0.9 seconds
Started Mar 28 02:30:52 PM PDT 24
Finished Mar 28 02:30:53 PM PDT 24
Peak memory 196240 kb
Host smart-3d2d2f4d-b218-4c09-876b-f15173c8208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446298906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1446298906
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2190593689
Short name T263
Test name
Test status
Simulation time 41997981 ps
CPU time 0.66 seconds
Started Mar 28 02:30:47 PM PDT 24
Finished Mar 28 02:30:48 PM PDT 24
Peak memory 194404 kb
Host smart-04ceab98-bc2f-426b-b076-ca1fae3b19b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190593689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2190593689
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3678441098
Short name T297
Test name
Test status
Simulation time 212483657 ps
CPU time 4.74 seconds
Started Mar 28 02:30:49 PM PDT 24
Finished Mar 28 02:30:54 PM PDT 24
Peak memory 198096 kb
Host smart-3e05cd47-6925-4033-afc4-0b4cdbe80ed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678441098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3678441098
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1996935973
Short name T293
Test name
Test status
Simulation time 253292825 ps
CPU time 0.86 seconds
Started Mar 28 02:30:49 PM PDT 24
Finished Mar 28 02:30:50 PM PDT 24
Peak memory 195908 kb
Host smart-13a9c812-7066-42bf-9c4a-c71ef7562387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996935973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1996935973
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1968250021
Short name T416
Test name
Test status
Simulation time 61214624 ps
CPU time 0.87 seconds
Started Mar 28 02:30:51 PM PDT 24
Finished Mar 28 02:30:52 PM PDT 24
Peak memory 195284 kb
Host smart-92a6396d-b32a-4068-9692-0e22492df114
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968250021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1968250021
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2657105566
Short name T593
Test name
Test status
Simulation time 32955832175 ps
CPU time 169.29 seconds
Started Mar 28 02:31:07 PM PDT 24
Finished Mar 28 02:33:58 PM PDT 24
Peak memory 198180 kb
Host smart-d44a4600-a556-4a6c-9402-5db112526563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657105566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2657105566
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2162828157
Short name T146
Test name
Test status
Simulation time 102770594 ps
CPU time 0.6 seconds
Started Mar 28 02:30:48 PM PDT 24
Finished Mar 28 02:30:49 PM PDT 24
Peak memory 193944 kb
Host smart-c7caffd9-3206-4308-ba80-d2e995ce1f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162828157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2162828157
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2860593714
Short name T303
Test name
Test status
Simulation time 29091105 ps
CPU time 0.86 seconds
Started Mar 28 02:30:48 PM PDT 24
Finished Mar 28 02:30:49 PM PDT 24
Peak memory 197056 kb
Host smart-1da08700-27c7-45e3-9732-8bf5c6219b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860593714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2860593714
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3559015125
Short name T16
Test name
Test status
Simulation time 1162053271 ps
CPU time 16.6 seconds
Started Mar 28 02:30:51 PM PDT 24
Finished Mar 28 02:31:08 PM PDT 24
Peak memory 195540 kb
Host smart-e89c4df7-de0c-4185-8276-92dd58aa2d17
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559015125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3559015125
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.326818305
Short name T5
Test name
Test status
Simulation time 58936387 ps
CPU time 0.81 seconds
Started Mar 28 02:30:51 PM PDT 24
Finished Mar 28 02:30:52 PM PDT 24
Peak memory 195992 kb
Host smart-88f74508-8923-46f2-a80a-893641b2dac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326818305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.326818305
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1227601861
Short name T158
Test name
Test status
Simulation time 25840643 ps
CPU time 0.86 seconds
Started Mar 28 02:30:48 PM PDT 24
Finished Mar 28 02:30:49 PM PDT 24
Peak memory 196792 kb
Host smart-8ea0df44-e7b2-4844-a74a-c1c4c9f002c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227601861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1227601861
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.157475723
Short name T108
Test name
Test status
Simulation time 1160721989 ps
CPU time 3.48 seconds
Started Mar 28 02:30:53 PM PDT 24
Finished Mar 28 02:30:58 PM PDT 24
Peak memory 198108 kb
Host smart-1a050096-46e7-4834-880d-4aef65ef5c13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157475723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.157475723
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.676112777
Short name T257
Test name
Test status
Simulation time 135346525 ps
CPU time 2.87 seconds
Started Mar 28 02:30:51 PM PDT 24
Finished Mar 28 02:30:54 PM PDT 24
Peak memory 196520 kb
Host smart-d81a6983-9fc7-465a-9664-d29786acd858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676112777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
676112777
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3849346827
Short name T574
Test name
Test status
Simulation time 27634151 ps
CPU time 1 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 195888 kb
Host smart-7f344513-a45e-45f0-b69e-beadc0d49293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849346827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3849346827
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3672895814
Short name T689
Test name
Test status
Simulation time 29224829 ps
CPU time 0.89 seconds
Started Mar 28 02:30:56 PM PDT 24
Finished Mar 28 02:30:57 PM PDT 24
Peak memory 195932 kb
Host smart-2dc53042-4238-4ce6-846c-cd190e0ea159
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672895814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3672895814
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3027309981
Short name T703
Test name
Test status
Simulation time 1178622738 ps
CPU time 4.79 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:55 PM PDT 24
Peak memory 197816 kb
Host smart-84da3f12-0075-46af-9e50-eb3cd68970b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027309981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3027309981
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3571713116
Short name T153
Test name
Test status
Simulation time 112305211 ps
CPU time 0.74 seconds
Started Mar 28 02:30:48 PM PDT 24
Finished Mar 28 02:30:48 PM PDT 24
Peak memory 195000 kb
Host smart-cdca45f6-f259-4f7e-a777-cdee88db422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571713116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3571713116
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1634906840
Short name T348
Test name
Test status
Simulation time 72811628 ps
CPU time 0.93 seconds
Started Mar 28 02:30:51 PM PDT 24
Finished Mar 28 02:30:52 PM PDT 24
Peak memory 196976 kb
Host smart-614dda8c-2d9f-4f92-b15c-1ea804f4f462
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634906840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1634906840
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3191603571
Short name T471
Test name
Test status
Simulation time 13826402953 ps
CPU time 102.56 seconds
Started Mar 28 02:30:52 PM PDT 24
Finished Mar 28 02:32:35 PM PDT 24
Peak memory 198204 kb
Host smart-515e68db-2843-457a-acb9-8457afea7558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191603571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3191603571
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1456535
Short name T644
Test name
Test status
Simulation time 12676660 ps
CPU time 0.56 seconds
Started Mar 28 02:30:51 PM PDT 24
Finished Mar 28 02:30:52 PM PDT 24
Peak memory 194100 kb
Host smart-5f52cdbf-83e4-4c74-8d05-74d96db31f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1456535
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1983224970
Short name T661
Test name
Test status
Simulation time 109016853 ps
CPU time 0.73 seconds
Started Mar 28 02:30:51 PM PDT 24
Finished Mar 28 02:30:52 PM PDT 24
Peak memory 195224 kb
Host smart-125986c9-7dfa-4259-8e3c-ce122b964280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983224970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1983224970
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2821362343
Short name T222
Test name
Test status
Simulation time 2259094192 ps
CPU time 12.27 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:31:02 PM PDT 24
Peak memory 197040 kb
Host smart-0ffa9d56-5c39-4b09-8d79-e28bac9ec4f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821362343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2821362343
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1376143692
Short name T142
Test name
Test status
Simulation time 94570888 ps
CPU time 0.83 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 195856 kb
Host smart-11d70c8b-644e-4802-ade7-2b8b60f974e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376143692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1376143692
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.124746826
Short name T326
Test name
Test status
Simulation time 71934652 ps
CPU time 1.17 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 196036 kb
Host smart-86ecab68-5567-4a29-a978-cb340702f77b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124746826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.124746826
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.301768470
Short name T652
Test name
Test status
Simulation time 67813430 ps
CPU time 2.68 seconds
Started Mar 28 02:30:48 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 196520 kb
Host smart-ead8da10-fba6-4b30-904d-1031616871c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301768470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.301768470
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.597514423
Short name T562
Test name
Test status
Simulation time 467881814 ps
CPU time 3.6 seconds
Started Mar 28 02:30:53 PM PDT 24
Finished Mar 28 02:30:57 PM PDT 24
Peak memory 196944 kb
Host smart-ec4e3695-80ed-449e-8808-29271cd1a36e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597514423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
597514423
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3308717712
Short name T256
Test name
Test status
Simulation time 35529917 ps
CPU time 1.17 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 196860 kb
Host smart-53dc34ef-b598-4821-b45c-85e14ce45311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308717712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3308717712
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1323119694
Short name T625
Test name
Test status
Simulation time 332046555 ps
CPU time 0.95 seconds
Started Mar 28 02:30:49 PM PDT 24
Finished Mar 28 02:30:50 PM PDT 24
Peak memory 195728 kb
Host smart-26f911ef-77c8-42b7-b0c7-0b93c6ce3293
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323119694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1323119694
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.86769161
Short name T151
Test name
Test status
Simulation time 85026547 ps
CPU time 3.94 seconds
Started Mar 28 02:31:06 PM PDT 24
Finished Mar 28 02:31:10 PM PDT 24
Peak memory 198036 kb
Host smart-2231d890-b7dc-4e8b-885c-1c716e1f3364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86769161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand
om_long_reg_writes_reg_reads.86769161
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3338227618
Short name T358
Test name
Test status
Simulation time 484441828 ps
CPU time 1.47 seconds
Started Mar 28 02:30:49 PM PDT 24
Finished Mar 28 02:30:50 PM PDT 24
Peak memory 196800 kb
Host smart-bd89186a-dd3a-4fba-a883-d57256492167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338227618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3338227618
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1202989824
Short name T284
Test name
Test status
Simulation time 86556509 ps
CPU time 1.36 seconds
Started Mar 28 02:30:51 PM PDT 24
Finished Mar 28 02:30:52 PM PDT 24
Peak memory 196408 kb
Host smart-9723f194-5dc8-456b-b65e-0f16da99deff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202989824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1202989824
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.715589403
Short name T432
Test name
Test status
Simulation time 25573403535 ps
CPU time 169.68 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:33:40 PM PDT 24
Peak memory 198232 kb
Host smart-3c6673ad-77ff-484b-ba4d-8c8feb34b59d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715589403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.715589403
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1968028546
Short name T474
Test name
Test status
Simulation time 20144315 ps
CPU time 0.57 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 193948 kb
Host smart-2a6bc72e-de7f-4ffb-b5e9-c692b3e9f2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968028546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1968028546
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.139325221
Short name T374
Test name
Test status
Simulation time 17848009 ps
CPU time 0.64 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 194704 kb
Host smart-d986f401-aa33-4226-b4d2-1902a199fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139325221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.139325221
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.792865346
Short name T538
Test name
Test status
Simulation time 999797621 ps
CPU time 27.17 seconds
Started Mar 28 02:30:52 PM PDT 24
Finished Mar 28 02:31:19 PM PDT 24
Peak memory 197068 kb
Host smart-d5295e32-5a14-40e8-b855-56673d96f677
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792865346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.792865346
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2302425840
Short name T278
Test name
Test status
Simulation time 66077565 ps
CPU time 0.94 seconds
Started Mar 28 02:30:48 PM PDT 24
Finished Mar 28 02:30:49 PM PDT 24
Peak memory 196544 kb
Host smart-a006f4dc-5b0a-416b-830a-9d784f975840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302425840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2302425840
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.230456250
Short name T386
Test name
Test status
Simulation time 28992438 ps
CPU time 0.69 seconds
Started Mar 28 02:30:52 PM PDT 24
Finished Mar 28 02:30:53 PM PDT 24
Peak memory 195088 kb
Host smart-5c5bcf00-53cf-42fd-b22b-9212bb23a8a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230456250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.230456250
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2278523841
Short name T229
Test name
Test status
Simulation time 23877972 ps
CPU time 0.9 seconds
Started Mar 28 02:30:53 PM PDT 24
Finished Mar 28 02:30:54 PM PDT 24
Peak memory 196208 kb
Host smart-89206f0a-c299-43ce-9d5c-4c3f18dfd2d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278523841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2278523841
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3503068610
Short name T585
Test name
Test status
Simulation time 564535886 ps
CPU time 2.61 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:53 PM PDT 24
Peak memory 197136 kb
Host smart-5f9738b6-873c-4c6f-baa7-7c5ad3385fe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503068610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3503068610
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1342553662
Short name T305
Test name
Test status
Simulation time 36088136 ps
CPU time 1.44 seconds
Started Mar 28 02:30:49 PM PDT 24
Finished Mar 28 02:30:50 PM PDT 24
Peak memory 197960 kb
Host smart-14d9467a-df3a-4e23-8a03-512d49958ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342553662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1342553662
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2792025275
Short name T251
Test name
Test status
Simulation time 72599926 ps
CPU time 1.44 seconds
Started Mar 28 02:30:50 PM PDT 24
Finished Mar 28 02:30:52 PM PDT 24
Peak memory 198108 kb
Host smart-28683574-9309-46bd-96f7-9a53d9f3e541
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792025275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2792025275
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.431918421
Short name T508
Test name
Test status
Simulation time 499585555 ps
CPU time 6 seconds
Started Mar 28 02:30:52 PM PDT 24
Finished Mar 28 02:30:58 PM PDT 24
Peak memory 198040 kb
Host smart-5c66dd74-3280-4bc4-ad1b-14add5ac8288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431918421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.431918421
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.818544704
Short name T556
Test name
Test status
Simulation time 217083273 ps
CPU time 1.15 seconds
Started Mar 28 02:30:49 PM PDT 24
Finished Mar 28 02:30:51 PM PDT 24
Peak memory 196564 kb
Host smart-63622d3b-5e3e-48e2-985f-658f5392fbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818544704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.818544704
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3532647416
Short name T243
Test name
Test status
Simulation time 75207206 ps
CPU time 0.76 seconds
Started Mar 28 02:30:48 PM PDT 24
Finished Mar 28 02:30:49 PM PDT 24
Peak memory 195292 kb
Host smart-eb7145d0-826c-4f05-b7c9-373cf6d043b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532647416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3532647416
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.269745379
Short name T289
Test name
Test status
Simulation time 1985606340 ps
CPU time 29.74 seconds
Started Mar 28 02:30:52 PM PDT 24
Finished Mar 28 02:31:22 PM PDT 24
Peak memory 198044 kb
Host smart-97b7fb8f-cc30-4e08-a373-6d937e4746a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269745379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.269745379
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3303807734
Short name T160
Test name
Test status
Simulation time 37306658 ps
CPU time 0.57 seconds
Started Mar 28 02:25:09 PM PDT 24
Finished Mar 28 02:25:09 PM PDT 24
Peak memory 193896 kb
Host smart-8f2b55f1-ac20-4c8e-8403-d41e1d97ed8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303807734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3303807734
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2283944963
Short name T167
Test name
Test status
Simulation time 221782705 ps
CPU time 0.97 seconds
Started Mar 28 02:24:51 PM PDT 24
Finished Mar 28 02:24:52 PM PDT 24
Peak memory 196716 kb
Host smart-882e89e1-3c26-43c6-94e4-27505e9ab1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283944963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2283944963
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.281000352
Short name T31
Test name
Test status
Simulation time 1178496240 ps
CPU time 18.7 seconds
Started Mar 28 02:25:09 PM PDT 24
Finished Mar 28 02:25:28 PM PDT 24
Peak memory 197988 kb
Host smart-d2d7d086-6c21-4211-b0e9-784c9f228384
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281000352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.281000352
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3805577147
Short name T367
Test name
Test status
Simulation time 166049275 ps
CPU time 0.79 seconds
Started Mar 28 02:25:07 PM PDT 24
Finished Mar 28 02:25:08 PM PDT 24
Peak memory 196108 kb
Host smart-f1dc3fbd-20d6-4a61-9239-5391094d3aca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805577147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3805577147
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1359234774
Short name T519
Test name
Test status
Simulation time 137519735 ps
CPU time 1.19 seconds
Started Mar 28 02:24:49 PM PDT 24
Finished Mar 28 02:24:51 PM PDT 24
Peak memory 195796 kb
Host smart-6c2c317d-0f61-420c-b3cc-28295e5f5c50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359234774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1359234774
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2343273877
Short name T219
Test name
Test status
Simulation time 178534663 ps
CPU time 3.84 seconds
Started Mar 28 02:25:08 PM PDT 24
Finished Mar 28 02:25:12 PM PDT 24
Peak memory 198108 kb
Host smart-e104365b-fad0-4ee7-b231-47523b3cf643
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343273877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2343273877
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3624064922
Short name T622
Test name
Test status
Simulation time 648584329 ps
CPU time 3.59 seconds
Started Mar 28 02:24:47 PM PDT 24
Finished Mar 28 02:24:50 PM PDT 24
Peak memory 196576 kb
Host smart-a24c2ec5-a316-40f8-8994-ead64b5d3c57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624064922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3624064922
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1206121447
Short name T334
Test name
Test status
Simulation time 56739781 ps
CPU time 1.16 seconds
Started Mar 28 02:24:50 PM PDT 24
Finished Mar 28 02:24:51 PM PDT 24
Peak memory 195812 kb
Host smart-17ec9871-6507-48bd-ad7f-8b7111fc9b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206121447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1206121447
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.398370803
Short name T131
Test name
Test status
Simulation time 30012170 ps
CPU time 1.16 seconds
Started Mar 28 02:24:48 PM PDT 24
Finished Mar 28 02:24:50 PM PDT 24
Peak memory 196544 kb
Host smart-907171de-0d8b-434e-aae0-ae406e788293
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398370803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.398370803
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1877398444
Short name T654
Test name
Test status
Simulation time 1844444491 ps
CPU time 5.3 seconds
Started Mar 28 02:25:09 PM PDT 24
Finished Mar 28 02:25:14 PM PDT 24
Peak memory 197876 kb
Host smart-ed90ecf0-984f-45c1-be2d-c08d07bc1f2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877398444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1877398444
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2352944190
Short name T609
Test name
Test status
Simulation time 82325652 ps
CPU time 0.8 seconds
Started Mar 28 02:24:49 PM PDT 24
Finished Mar 28 02:24:49 PM PDT 24
Peak memory 195216 kb
Host smart-c6a53ee2-be8d-44b0-af45-525ae8ff0cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352944190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2352944190
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3537757905
Short name T468
Test name
Test status
Simulation time 69286095 ps
CPU time 1.42 seconds
Started Mar 28 02:24:48 PM PDT 24
Finished Mar 28 02:24:50 PM PDT 24
Peak memory 197212 kb
Host smart-d546c46f-6962-4be8-8dda-a26bbe2111ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537757905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3537757905
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2190932334
Short name T693
Test name
Test status
Simulation time 17274734927 ps
CPU time 201.42 seconds
Started Mar 28 02:25:09 PM PDT 24
Finished Mar 28 02:28:30 PM PDT 24
Peak memory 198208 kb
Host smart-fc8f7bd1-35af-4c8b-80a2-bcd98ae8ec78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190932334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2190932334
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3810491767
Short name T394
Test name
Test status
Simulation time 41718470 ps
CPU time 0.59 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:26 PM PDT 24
Peak memory 194136 kb
Host smart-bc8a4638-e766-4fd6-a629-efaaf8f0a48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810491767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3810491767
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1087792974
Short name T602
Test name
Test status
Simulation time 29459079 ps
CPU time 1 seconds
Started Mar 28 02:25:08 PM PDT 24
Finished Mar 28 02:25:09 PM PDT 24
Peak memory 196400 kb
Host smart-8c6f6774-a6ff-477c-83b2-1b9d1214e17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087792974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1087792974
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.391801945
Short name T382
Test name
Test status
Simulation time 3484540711 ps
CPU time 7.8 seconds
Started Mar 28 02:25:09 PM PDT 24
Finished Mar 28 02:25:17 PM PDT 24
Peak memory 196716 kb
Host smart-9d16dcb7-bf65-4c40-b583-317af644098f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391801945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.391801945
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1059083131
Short name T372
Test name
Test status
Simulation time 158098561 ps
CPU time 1.22 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:28 PM PDT 24
Peak memory 198024 kb
Host smart-ff61a3bb-2838-43bf-ab2b-92a0dababe65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059083131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1059083131
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3234064443
Short name T604
Test name
Test status
Simulation time 162382788 ps
CPU time 1.21 seconds
Started Mar 28 02:25:07 PM PDT 24
Finished Mar 28 02:25:08 PM PDT 24
Peak memory 195792 kb
Host smart-821f6f7a-560a-4250-ba73-7325166571db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234064443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3234064443
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4176197908
Short name T349
Test name
Test status
Simulation time 254353854 ps
CPU time 2.71 seconds
Started Mar 28 02:25:08 PM PDT 24
Finished Mar 28 02:25:11 PM PDT 24
Peak memory 198132 kb
Host smart-7dbd8432-f528-4319-b35d-a18460259acf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176197908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.4176197908
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.508812474
Short name T127
Test name
Test status
Simulation time 88679561 ps
CPU time 2.51 seconds
Started Mar 28 02:25:10 PM PDT 24
Finished Mar 28 02:25:13 PM PDT 24
Peak memory 196452 kb
Host smart-8e6fe963-547c-4c84-a98b-b09c9f1b5a85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508812474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.508812474
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3345331
Short name T653
Test name
Test status
Simulation time 135768185 ps
CPU time 1.47 seconds
Started Mar 28 02:25:07 PM PDT 24
Finished Mar 28 02:25:09 PM PDT 24
Peak memory 198016 kb
Host smart-d3b4c8dc-7c9f-4a73-8c41-496a62d44c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3345331
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1625537854
Short name T323
Test name
Test status
Simulation time 72620614 ps
CPU time 1.37 seconds
Started Mar 28 02:25:09 PM PDT 24
Finished Mar 28 02:25:11 PM PDT 24
Peak memory 196956 kb
Host smart-54902577-177c-4e90-9578-ce217e4073ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625537854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1625537854
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.625797557
Short name T8
Test name
Test status
Simulation time 584432487 ps
CPU time 4 seconds
Started Mar 28 02:25:27 PM PDT 24
Finished Mar 28 02:25:32 PM PDT 24
Peak memory 198028 kb
Host smart-afce0a5d-3b26-452b-8fb2-16795abebced
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625797557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.625797557
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1926793758
Short name T246
Test name
Test status
Simulation time 711396650 ps
CPU time 1.44 seconds
Started Mar 28 02:25:08 PM PDT 24
Finished Mar 28 02:25:09 PM PDT 24
Peak memory 196556 kb
Host smart-2e41340d-ae63-4805-81b2-7807f4e488dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926793758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1926793758
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3913477523
Short name T633
Test name
Test status
Simulation time 46858040 ps
CPU time 1.49 seconds
Started Mar 28 02:25:08 PM PDT 24
Finished Mar 28 02:25:09 PM PDT 24
Peak memory 196696 kb
Host smart-8a505127-cad8-4c27-8457-55a460d95754
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913477523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3913477523
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2912993537
Short name T434
Test name
Test status
Simulation time 6706794233 ps
CPU time 183.81 seconds
Started Mar 28 02:25:28 PM PDT 24
Finished Mar 28 02:28:32 PM PDT 24
Peak memory 198168 kb
Host smart-9ecd9e52-b272-4107-8d71-8f8fd4c6cd8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912993537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2912993537
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.4137019537
Short name T67
Test name
Test status
Simulation time 70603385872 ps
CPU time 274.05 seconds
Started Mar 28 02:25:28 PM PDT 24
Finished Mar 28 02:30:02 PM PDT 24
Peak memory 206460 kb
Host smart-70eb3c9f-1600-4de6-8a40-2f4d5b8cb6ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4137019537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.4137019537
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.521968682
Short name T531
Test name
Test status
Simulation time 21173572 ps
CPU time 0.58 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:27 PM PDT 24
Peak memory 194644 kb
Host smart-c4025c6b-8392-49ad-a881-e1babb46c711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521968682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.521968682
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1961724959
Short name T55
Test name
Test status
Simulation time 162948439 ps
CPU time 0.92 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:27 PM PDT 24
Peak memory 196564 kb
Host smart-db1039b4-f40c-47d9-b064-c821b7eda057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961724959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1961724959
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.143937351
Short name T463
Test name
Test status
Simulation time 397718232 ps
CPU time 14.85 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:41 PM PDT 24
Peak memory 195460 kb
Host smart-0da48790-c8d7-4522-ad3c-99245fe8a3db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143937351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.143937351
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.971359031
Short name T683
Test name
Test status
Simulation time 137804285 ps
CPU time 1.08 seconds
Started Mar 28 02:25:25 PM PDT 24
Finished Mar 28 02:25:27 PM PDT 24
Peak memory 196608 kb
Host smart-41c0958b-8809-40b5-90b3-c237076950f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971359031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.971359031
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2834462
Short name T350
Test name
Test status
Simulation time 64098166 ps
CPU time 1.08 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:28 PM PDT 24
Peak memory 195836 kb
Host smart-10ff5c2c-1703-47d1-8134-11fa59c257ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2834462
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3624382090
Short name T586
Test name
Test status
Simulation time 44549109 ps
CPU time 2.02 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:28 PM PDT 24
Peak memory 198072 kb
Host smart-5137e9e1-01b4-4219-bb73-9b0bd23e5eed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624382090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3624382090
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1963372116
Short name T114
Test name
Test status
Simulation time 441127640 ps
CPU time 2.52 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:29 PM PDT 24
Peak memory 198036 kb
Host smart-4635037e-460b-4a66-84ae-da17a2709e03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963372116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1963372116
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1991875872
Short name T150
Test name
Test status
Simulation time 28192482 ps
CPU time 1.01 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:27 PM PDT 24
Peak memory 195812 kb
Host smart-8bdb43fc-93b9-4ed7-9e77-dce1d269de2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991875872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1991875872
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3472632452
Short name T328
Test name
Test status
Simulation time 64094645 ps
CPU time 1.38 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:28 PM PDT 24
Peak memory 196980 kb
Host smart-80c8ae9e-2b5d-4ed7-9e72-952022d07fe5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472632452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3472632452
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.743421313
Short name T529
Test name
Test status
Simulation time 2003134248 ps
CPU time 6.14 seconds
Started Mar 28 02:25:24 PM PDT 24
Finished Mar 28 02:25:31 PM PDT 24
Peak memory 197972 kb
Host smart-0b9077ea-61ca-4dd8-88fa-e414f987acd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743421313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.743421313
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1709338173
Short name T134
Test name
Test status
Simulation time 37917236 ps
CPU time 0.84 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:27 PM PDT 24
Peak memory 195380 kb
Host smart-70e8b52b-ded7-45c8-b2ff-791fa81ef658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709338173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1709338173
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.356655441
Short name T457
Test name
Test status
Simulation time 84420732 ps
CPU time 1.58 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:27 PM PDT 24
Peak memory 196824 kb
Host smart-044b0452-c4c1-4dc4-ae45-9c84d9ec487c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356655441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.356655441
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.786498149
Short name T570
Test name
Test status
Simulation time 13235889157 ps
CPU time 135.16 seconds
Started Mar 28 02:25:25 PM PDT 24
Finished Mar 28 02:27:41 PM PDT 24
Peak memory 198196 kb
Host smart-be4b15af-6a7f-4cb5-8253-a40abbb479c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786498149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.786498149
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.408867706
Short name T590
Test name
Test status
Simulation time 107047471059 ps
CPU time 2104.41 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 03:00:31 PM PDT 24
Peak memory 198240 kb
Host smart-5d8f6cc4-e5b7-4691-b44d-22f9bcec87d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=408867706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.408867706
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1203024177
Short name T672
Test name
Test status
Simulation time 14461311 ps
CPU time 0.57 seconds
Started Mar 28 02:25:51 PM PDT 24
Finished Mar 28 02:25:52 PM PDT 24
Peak memory 193916 kb
Host smart-686d2e46-e45b-431d-950d-38ec3e21c4c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203024177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1203024177
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3817337905
Short name T485
Test name
Test status
Simulation time 27567220 ps
CPU time 0.89 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:27 PM PDT 24
Peak memory 195684 kb
Host smart-78ffa8c3-3084-4863-874f-71477a16fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817337905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3817337905
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.764470969
Short name T32
Test name
Test status
Simulation time 885822174 ps
CPU time 22.67 seconds
Started Mar 28 02:25:27 PM PDT 24
Finished Mar 28 02:25:50 PM PDT 24
Peak memory 197996 kb
Host smart-4a5c2ef3-2f3b-4215-88d9-f4bc40e6dfa7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764470969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.764470969
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2343995233
Short name T226
Test name
Test status
Simulation time 406145809 ps
CPU time 0.7 seconds
Started Mar 28 02:25:52 PM PDT 24
Finished Mar 28 02:25:53 PM PDT 24
Peak memory 194680 kb
Host smart-640d6ead-7144-44f1-ada4-eba8358261d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343995233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2343995233
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1493898686
Short name T592
Test name
Test status
Simulation time 90809777 ps
CPU time 1.34 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:27 PM PDT 24
Peak memory 196700 kb
Host smart-3ef3b67a-fe63-403d-a5b6-b3116c2a5f48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493898686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1493898686
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.4119118102
Short name T632
Test name
Test status
Simulation time 323891958 ps
CPU time 3.48 seconds
Started Mar 28 02:25:27 PM PDT 24
Finished Mar 28 02:25:31 PM PDT 24
Peak memory 198136 kb
Host smart-d240433b-ffb8-4ad8-9611-aa5cd3201755
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119118102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.4119118102
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2699571675
Short name T110
Test name
Test status
Simulation time 200399603 ps
CPU time 1.11 seconds
Started Mar 28 02:25:26 PM PDT 24
Finished Mar 28 02:25:28 PM PDT 24
Peak memory 196284 kb
Host smart-b58fbe6a-43a1-47dd-9336-2173ef1617bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699571675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2699571675
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.690930582
Short name T500
Test name
Test status
Simulation time 23763580 ps
CPU time 0.82 seconds
Started Mar 28 02:25:27 PM PDT 24
Finished Mar 28 02:25:28 PM PDT 24
Peak memory 195496 kb
Host smart-ba1e6927-9e60-451d-97a0-1c1bc6cd103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690930582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.690930582
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3005682183
Short name T511
Test name
Test status
Simulation time 122194864 ps
CPU time 1.17 seconds
Started Mar 28 02:25:28 PM PDT 24
Finished Mar 28 02:25:29 PM PDT 24
Peak memory 196120 kb
Host smart-685de222-53a7-4be8-b3b7-85deace13143
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005682183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3005682183
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1604689633
Short name T141
Test name
Test status
Simulation time 1023417780 ps
CPU time 4.18 seconds
Started Mar 28 02:25:53 PM PDT 24
Finished Mar 28 02:25:57 PM PDT 24
Peak memory 197856 kb
Host smart-a3779f7f-5f5d-4482-b02a-88c64ecb1b1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604689633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1604689633
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.214824348
Short name T669
Test name
Test status
Simulation time 174123702 ps
CPU time 1.03 seconds
Started Mar 28 02:25:28 PM PDT 24
Finished Mar 28 02:25:29 PM PDT 24
Peak memory 196352 kb
Host smart-459a7796-4842-484d-9345-6f555024721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214824348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.214824348
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3431127024
Short name T324
Test name
Test status
Simulation time 41345481 ps
CPU time 1.18 seconds
Started Mar 28 02:25:27 PM PDT 24
Finished Mar 28 02:25:28 PM PDT 24
Peak memory 195820 kb
Host smart-5648eb54-581b-4fa3-9de5-64a1b49f74ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431127024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3431127024
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.4189237001
Short name T274
Test name
Test status
Simulation time 2175822891 ps
CPU time 52.47 seconds
Started Mar 28 02:25:52 PM PDT 24
Finished Mar 28 02:26:44 PM PDT 24
Peak memory 198120 kb
Host smart-cbdb99da-3166-49b3-8e71-eed5af43fb0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189237001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.4189237001
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3576453749
Short name T37
Test name
Test status
Simulation time 385105111028 ps
CPU time 1613.76 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:52:49 PM PDT 24
Peak memory 198324 kb
Host smart-8ad017db-55ec-412b-a200-4524f2002e43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3576453749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3576453749
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2193007329
Short name T462
Test name
Test status
Simulation time 42077673 ps
CPU time 0.55 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 192820 kb
Host smart-be2d83f8-f7ac-4c9e-a6d6-c6501c528041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193007329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2193007329
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.329010938
Short name T631
Test name
Test status
Simulation time 51590569 ps
CPU time 0.95 seconds
Started Mar 28 02:25:53 PM PDT 24
Finished Mar 28 02:25:54 PM PDT 24
Peak memory 196640 kb
Host smart-b4c364d6-3f4d-496a-b69b-cd46bb3bc23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329010938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.329010938
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2446121827
Short name T400
Test name
Test status
Simulation time 856361027 ps
CPU time 11.22 seconds
Started Mar 28 02:25:53 PM PDT 24
Finished Mar 28 02:26:04 PM PDT 24
Peak memory 196100 kb
Host smart-cbbb7f89-4d9a-4b36-80f3-999afaddb873
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446121827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2446121827
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.940687420
Short name T259
Test name
Test status
Simulation time 64084115 ps
CPU time 0.77 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 195464 kb
Host smart-5c4309f4-ac48-45ed-8fcc-b361110561e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940687420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.940687420
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2354424291
Short name T162
Test name
Test status
Simulation time 320904853 ps
CPU time 1.36 seconds
Started Mar 28 02:25:53 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 195784 kb
Host smart-ca8d6404-871d-4e58-ba30-a6e286147d75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354424291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2354424291
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1540910005
Short name T205
Test name
Test status
Simulation time 105613068 ps
CPU time 3.77 seconds
Started Mar 28 02:25:56 PM PDT 24
Finished Mar 28 02:26:00 PM PDT 24
Peak memory 198040 kb
Host smart-8cd0610c-0764-4524-b260-2c5148650ab9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540910005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1540910005
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1494032523
Short name T318
Test name
Test status
Simulation time 95088798 ps
CPU time 2.24 seconds
Started Mar 28 02:25:52 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 196740 kb
Host smart-fe6bd350-e89f-472e-bc37-7aae7867ea51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494032523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1494032523
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2391992702
Short name T201
Test name
Test status
Simulation time 73787156 ps
CPU time 0.98 seconds
Started Mar 28 02:25:53 PM PDT 24
Finished Mar 28 02:25:54 PM PDT 24
Peak memory 196696 kb
Host smart-a97d20a8-b30e-4607-8877-72891b379615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391992702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2391992702
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.4137173875
Short name T311
Test name
Test status
Simulation time 84695357 ps
CPU time 1.09 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 195976 kb
Host smart-9a77a9c0-029b-4cfa-baf1-cdc15dd39a16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137173875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.4137173875
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1845890616
Short name T514
Test name
Test status
Simulation time 98201279 ps
CPU time 1.94 seconds
Started Mar 28 02:25:56 PM PDT 24
Finished Mar 28 02:25:58 PM PDT 24
Peak memory 197980 kb
Host smart-1ea0b4e3-6a2e-4553-9516-ec9a791ccde1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845890616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1845890616
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1375397170
Short name T177
Test name
Test status
Simulation time 37951412 ps
CPU time 1.05 seconds
Started Mar 28 02:25:53 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 195696 kb
Host smart-31b05e9f-fb3f-4b5a-8518-f53b584ea12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375397170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1375397170
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.43751151
Short name T155
Test name
Test status
Simulation time 501429886 ps
CPU time 1.53 seconds
Started Mar 28 02:25:53 PM PDT 24
Finished Mar 28 02:25:55 PM PDT 24
Peak memory 196832 kb
Host smart-55fbac73-5a90-4d29-bf44-1290eb57805a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43751151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.43751151
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.602971151
Short name T648
Test name
Test status
Simulation time 44976040041 ps
CPU time 141.99 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:28:17 PM PDT 24
Peak memory 198172 kb
Host smart-ec72b3bd-6ed0-4d44-8bba-4993e5cc0b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602971151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.602971151
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.959181533
Short name T62
Test name
Test status
Simulation time 364478370416 ps
CPU time 1662.07 seconds
Started Mar 28 02:25:54 PM PDT 24
Finished Mar 28 02:53:36 PM PDT 24
Peak memory 198196 kb
Host smart-52650272-708c-4041-b1a7-6d81186ef21c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=959181533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.959181533
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3006486917
Short name T857
Test name
Test status
Simulation time 82105822 ps
CPU time 1.03 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:48:58 PM PDT 24
Peak memory 192304 kb
Host smart-fe591cd6-d052-4bcb-bd57-ffcba58dc479
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3006486917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3006486917
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1533644349
Short name T875
Test name
Test status
Simulation time 251581279 ps
CPU time 1.19 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192216 kb
Host smart-400418a8-01c2-4433-8fc3-6dffd62e86fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533644349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1533644349
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1579675563
Short name T932
Test name
Test status
Simulation time 121370441 ps
CPU time 1.05 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:48:58 PM PDT 24
Peak memory 198628 kb
Host smart-03f77166-8dee-4f52-8d01-222a99b3b46a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1579675563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1579675563
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3586430101
Short name T854
Test name
Test status
Simulation time 73849834 ps
CPU time 1.29 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:48:58 PM PDT 24
Peak memory 197304 kb
Host smart-6d63df21-6295-4ec4-be55-4e3e468ee3f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586430101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3586430101
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3625528518
Short name T868
Test name
Test status
Simulation time 60207456 ps
CPU time 1.3 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 192372 kb
Host smart-7efcbf1a-9d25-4bca-a177-8abc322eed25
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3625528518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3625528518
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1819124665
Short name T855
Test name
Test status
Simulation time 149894014 ps
CPU time 1.23 seconds
Started Mar 28 12:49:03 PM PDT 24
Finished Mar 28 12:49:04 PM PDT 24
Peak memory 192328 kb
Host smart-794285ec-c4ef-4c31-af8e-f7cb722b449b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819124665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1819124665
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.435309048
Short name T933
Test name
Test status
Simulation time 507245077 ps
CPU time 1.34 seconds
Started Mar 28 12:49:02 PM PDT 24
Finished Mar 28 12:49:04 PM PDT 24
Peak memory 192328 kb
Host smart-f2865681-0149-4bfe-96d1-b0d6722a8e24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=435309048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.435309048
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4198373595
Short name T893
Test name
Test status
Simulation time 133019325 ps
CPU time 0.9 seconds
Started Mar 28 12:49:02 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 192144 kb
Host smart-59ec5e07-c794-443f-8eab-ee6757244c96
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198373595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4198373595
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2049413321
Short name T861
Test name
Test status
Simulation time 36812499 ps
CPU time 0.89 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:49:00 PM PDT 24
Peak memory 196804 kb
Host smart-b9956942-641b-4db4-8ba7-4dccdf6b4ff2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2049413321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2049413321
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3837345678
Short name T894
Test name
Test status
Simulation time 136092381 ps
CPU time 1.53 seconds
Started Mar 28 12:49:03 PM PDT 24
Finished Mar 28 12:49:04 PM PDT 24
Peak memory 192280 kb
Host smart-db806994-8ebf-43ec-849f-9b8ecf4f7834
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837345678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3837345678
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.867370333
Short name T891
Test name
Test status
Simulation time 52269367 ps
CPU time 1.06 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192120 kb
Host smart-33aecaed-2fc4-4509-9b8d-2d1dfc2a6313
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=867370333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.867370333
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.5625399
Short name T870
Test name
Test status
Simulation time 60106449 ps
CPU time 1.17 seconds
Started Mar 28 12:49:02 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 192356 kb
Host smart-38ab68ba-8449-4fc5-8e2f-69260f447b63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5625399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.5625399
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.814617228
Short name T925
Test name
Test status
Simulation time 92657089 ps
CPU time 1.31 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192268 kb
Host smart-5d322003-b7c7-4f04-a576-fb50687dd273
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=814617228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.814617228
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1392446981
Short name T865
Test name
Test status
Simulation time 79611156 ps
CPU time 1.03 seconds
Started Mar 28 12:49:02 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 196908 kb
Host smart-0a722a6a-95ed-4786-b533-ca30eedc499e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392446981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1392446981
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3732512568
Short name T859
Test name
Test status
Simulation time 79655497 ps
CPU time 1.51 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192276 kb
Host smart-b2b33e5d-ba8c-45b1-be10-21d39c69197c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3732512568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3732512568
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1393259202
Short name T876
Test name
Test status
Simulation time 57785651 ps
CPU time 1.08 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 197264 kb
Host smart-e6987ddd-29af-4c24-a688-f6d5fda65b61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393259202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1393259202
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3605231953
Short name T886
Test name
Test status
Simulation time 288004205 ps
CPU time 1.12 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 198372 kb
Host smart-c94cf54d-cbe9-4902-a240-248e8bc7de9f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3605231953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3605231953
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.70419545
Short name T879
Test name
Test status
Simulation time 34981615 ps
CPU time 0.98 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:01 PM PDT 24
Peak memory 192284 kb
Host smart-dd87c003-0609-4c55-8dbf-6e81e62f5958
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70419545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.70419545
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1613419527
Short name T909
Test name
Test status
Simulation time 25456085 ps
CPU time 0.83 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:01 PM PDT 24
Peak memory 192088 kb
Host smart-ba331858-0e3c-4cb3-8217-eb5fd58b1b22
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1613419527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1613419527
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2975341391
Short name T892
Test name
Test status
Simulation time 37443163 ps
CPU time 0.99 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 198608 kb
Host smart-eba94f28-7ed9-42a5-ac0a-74fd5da07abe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975341391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2975341391
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2338754384
Short name T863
Test name
Test status
Simulation time 328729093 ps
CPU time 0.92 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192168 kb
Host smart-bf5305b5-a034-4cf4-bd50-36228bd5fcc9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2338754384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2338754384
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3616733235
Short name T908
Test name
Test status
Simulation time 114207043 ps
CPU time 1.36 seconds
Started Mar 28 12:49:02 PM PDT 24
Finished Mar 28 12:49:04 PM PDT 24
Peak memory 192284 kb
Host smart-ef2fa4db-402a-4f2b-8b73-340bf5cacdca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616733235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3616733235
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.545812475
Short name T882
Test name
Test status
Simulation time 26140583 ps
CPU time 1.03 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192300 kb
Host smart-77474dbd-38a3-4dd3-8637-c83c57803270
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=545812475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.545812475
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1921693875
Short name T877
Test name
Test status
Simulation time 132413057 ps
CPU time 1.36 seconds
Started Mar 28 12:49:04 PM PDT 24
Finished Mar 28 12:49:05 PM PDT 24
Peak memory 192272 kb
Host smart-a217351d-19d0-4aaa-b12a-90fe26f350e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921693875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1921693875
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.463785504
Short name T924
Test name
Test status
Simulation time 56523131 ps
CPU time 1.16 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:49:00 PM PDT 24
Peak memory 192316 kb
Host smart-b3abbec4-d5e9-421b-9631-cf3da92b7aec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=463785504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.463785504
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1711504369
Short name T922
Test name
Test status
Simulation time 39678003 ps
CPU time 1.13 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:49:01 PM PDT 24
Peak memory 192192 kb
Host smart-c727a281-5045-4622-8f24-8d6e10b8791d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711504369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1711504369
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1548411454
Short name T939
Test name
Test status
Simulation time 138779395 ps
CPU time 1.1 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192220 kb
Host smart-b9046da9-b789-4975-b0d8-5a84a2ed9cb9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1548411454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1548411454
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.218030388
Short name T935
Test name
Test status
Simulation time 739259838 ps
CPU time 1.13 seconds
Started Mar 28 12:49:04 PM PDT 24
Finished Mar 28 12:49:06 PM PDT 24
Peak memory 192284 kb
Host smart-38e19abb-69ac-4050-be14-04694dc416a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218030388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.218030388
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1749825369
Short name T881
Test name
Test status
Simulation time 157570500 ps
CPU time 1.22 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:01 PM PDT 24
Peak memory 192284 kb
Host smart-9cf7e972-b904-4fbc-b019-429aa6460dcd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1749825369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1749825369
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.772830333
Short name T887
Test name
Test status
Simulation time 66872045 ps
CPU time 0.76 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 196748 kb
Host smart-41504d9b-5c0f-44a1-abbc-a1f2f03269cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772830333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.772830333
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3166610201
Short name T926
Test name
Test status
Simulation time 195007427 ps
CPU time 1.55 seconds
Started Mar 28 12:49:03 PM PDT 24
Finished Mar 28 12:49:05 PM PDT 24
Peak memory 198540 kb
Host smart-0b6a3b7d-6244-4f71-9018-6abf10649a7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3166610201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3166610201
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2458365615
Short name T923
Test name
Test status
Simulation time 139264078 ps
CPU time 0.88 seconds
Started Mar 28 12:49:03 PM PDT 24
Finished Mar 28 12:49:04 PM PDT 24
Peak memory 196632 kb
Host smart-2caa6b78-6c0c-43b5-8de5-d275861829c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458365615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2458365615
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.264042322
Short name T929
Test name
Test status
Simulation time 67376658 ps
CPU time 0.9 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:49:00 PM PDT 24
Peak memory 192152 kb
Host smart-be89de53-6c1a-4c80-a5e2-dfbe507db375
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=264042322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.264042322
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3105335679
Short name T911
Test name
Test status
Simulation time 461688567 ps
CPU time 1.24 seconds
Started Mar 28 12:49:02 PM PDT 24
Finished Mar 28 12:49:04 PM PDT 24
Peak memory 192244 kb
Host smart-23b7da40-1287-4812-aad6-a74be3f722e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105335679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3105335679
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1339852919
Short name T841
Test name
Test status
Simulation time 57927280 ps
CPU time 0.96 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:01 PM PDT 24
Peak memory 192268 kb
Host smart-3ecf0b60-7024-4b2f-83d8-ba8b9a8d27d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1339852919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1339852919
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2835323552
Short name T889
Test name
Test status
Simulation time 573089660 ps
CPU time 1.31 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192388 kb
Host smart-81003a1f-0744-49df-9d3d-c01ff68d56a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835323552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2835323552
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.992767931
Short name T852
Test name
Test status
Simulation time 382063019 ps
CPU time 1.2 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 198544 kb
Host smart-f4ed441c-730d-46b3-9dc0-7ef34b40b6b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=992767931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.992767931
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1803441276
Short name T883
Test name
Test status
Simulation time 179475040 ps
CPU time 0.97 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 197920 kb
Host smart-ff503522-a1de-4ab2-ad9e-28e3684c01a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803441276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1803441276
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3877720874
Short name T910
Test name
Test status
Simulation time 47310888 ps
CPU time 1.4 seconds
Started Mar 28 12:49:05 PM PDT 24
Finished Mar 28 12:49:06 PM PDT 24
Peak memory 192328 kb
Host smart-ecd66a15-cc98-48e0-ba6e-684e6b4a07db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3877720874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3877720874
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.975977900
Short name T895
Test name
Test status
Simulation time 36083642 ps
CPU time 1.08 seconds
Started Mar 28 12:49:06 PM PDT 24
Finished Mar 28 12:49:07 PM PDT 24
Peak memory 198648 kb
Host smart-876e62f3-6661-4dda-87bd-76f42685a21d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975977900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.975977900
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.44730477
Short name T938
Test name
Test status
Simulation time 161068541 ps
CPU time 1 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192316 kb
Host smart-9bb6e105-bd8f-4a44-8e32-807ebf44d1ed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=44730477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.44730477
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2896203090
Short name T905
Test name
Test status
Simulation time 231045325 ps
CPU time 1.12 seconds
Started Mar 28 12:49:03 PM PDT 24
Finished Mar 28 12:49:05 PM PDT 24
Peak memory 192296 kb
Host smart-c6c4d3f0-7bb4-4d39-9d26-135be93b138b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896203090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2896203090
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.460395174
Short name T915
Test name
Test status
Simulation time 56275384 ps
CPU time 1.14 seconds
Started Mar 28 12:49:06 PM PDT 24
Finished Mar 28 12:49:07 PM PDT 24
Peak memory 192320 kb
Host smart-3a71de17-4dbf-47dd-bc0e-7743f084479d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=460395174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.460395174
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4241230977
Short name T874
Test name
Test status
Simulation time 19109166 ps
CPU time 0.78 seconds
Started Mar 28 12:49:15 PM PDT 24
Finished Mar 28 12:49:16 PM PDT 24
Peak memory 192176 kb
Host smart-fbcdace4-8bed-4ecf-acf7-f0e8205f4955
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241230977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4241230977
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3000118279
Short name T873
Test name
Test status
Simulation time 132272758 ps
CPU time 0.8 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 191980 kb
Host smart-768dd8b8-514e-49e9-8ff4-a07bf041edd8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3000118279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3000118279
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1548222999
Short name T900
Test name
Test status
Simulation time 56052795 ps
CPU time 1.13 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 192256 kb
Host smart-9cc89d4a-d878-47d2-838a-aa0738ea7aaa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548222999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1548222999
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3353623850
Short name T871
Test name
Test status
Simulation time 35787002 ps
CPU time 0.86 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 196604 kb
Host smart-c2a25928-d453-4b4b-ac82-beca19cdae51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3353623850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3353623850
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2078785334
Short name T866
Test name
Test status
Simulation time 92467648 ps
CPU time 0.89 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 198008 kb
Host smart-641bf337-8bb6-4c01-8bde-238848bd5acc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078785334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2078785334
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2880372356
Short name T907
Test name
Test status
Simulation time 295987965 ps
CPU time 1.09 seconds
Started Mar 28 12:49:20 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 192112 kb
Host smart-8e1f977d-f347-43d8-b248-bff6aa33fe2f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2880372356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2880372356
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.782794116
Short name T849
Test name
Test status
Simulation time 47413228 ps
CPU time 0.94 seconds
Started Mar 28 12:49:22 PM PDT 24
Finished Mar 28 12:49:23 PM PDT 24
Peak memory 192184 kb
Host smart-7ec24f87-cfa9-4293-adac-5d214eba0791
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782794116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.782794116
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1018191341
Short name T917
Test name
Test status
Simulation time 150784642 ps
CPU time 1.35 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 192216 kb
Host smart-67c09326-aee2-40a2-ac93-204766e325d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1018191341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1018191341
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4097934405
Short name T913
Test name
Test status
Simulation time 267067509 ps
CPU time 1.14 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 192320 kb
Host smart-7ffddeef-1472-40d4-8541-6322cae1bd85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097934405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4097934405
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4218573699
Short name T906
Test name
Test status
Simulation time 79361095 ps
CPU time 1.42 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 197092 kb
Host smart-755d43d3-f84e-4519-8850-a1d36b2c1253
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4218573699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4218573699
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2122838443
Short name T847
Test name
Test status
Simulation time 68780309 ps
CPU time 1.27 seconds
Started Mar 28 12:49:23 PM PDT 24
Finished Mar 28 12:49:24 PM PDT 24
Peak memory 192276 kb
Host smart-ea9558fe-1696-46b9-a8c7-5552d14590af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122838443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2122838443
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3927396652
Short name T890
Test name
Test status
Simulation time 130188310 ps
CPU time 1.01 seconds
Started Mar 28 12:49:23 PM PDT 24
Finished Mar 28 12:49:24 PM PDT 24
Peak memory 198536 kb
Host smart-2ff6e9f0-745d-45f2-9c5f-b1537bbc9f8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3927396652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3927396652
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2117393561
Short name T899
Test name
Test status
Simulation time 46512477 ps
CPU time 1.08 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 197124 kb
Host smart-ff455484-6795-426e-8a5d-c8adaf18ea24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117393561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2117393561
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2122533844
Short name T920
Test name
Test status
Simulation time 64159872 ps
CPU time 0.99 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 192124 kb
Host smart-27d59f77-b7af-4a6f-946e-6a609b8aacc9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2122533844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2122533844
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1943227023
Short name T869
Test name
Test status
Simulation time 41853635 ps
CPU time 0.72 seconds
Started Mar 28 12:49:22 PM PDT 24
Finished Mar 28 12:49:23 PM PDT 24
Peak memory 191964 kb
Host smart-248c7991-9a82-4113-a7a4-b101cbccc995
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943227023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1943227023
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4021713788
Short name T901
Test name
Test status
Simulation time 37627032 ps
CPU time 0.97 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 192136 kb
Host smart-433c886a-171f-4da2-b144-2172b39cb3a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4021713788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4021713788
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2557542422
Short name T878
Test name
Test status
Simulation time 140405394 ps
CPU time 1.13 seconds
Started Mar 28 12:49:20 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 197016 kb
Host smart-199e9242-2759-41fb-aee9-dd085ef1183f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557542422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2557542422
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1389073250
Short name T885
Test name
Test status
Simulation time 103642325 ps
CPU time 0.89 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 192152 kb
Host smart-ec50c046-150c-4c56-80ad-4c04ef2405f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1389073250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1389073250
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.855817098
Short name T918
Test name
Test status
Simulation time 61100630 ps
CPU time 1.22 seconds
Started Mar 28 12:49:20 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 192328 kb
Host smart-9a659622-01a5-4cfe-9662-f73bddfc404d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855817098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.855817098
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2960311897
Short name T862
Test name
Test status
Simulation time 88553087 ps
CPU time 1.13 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 192308 kb
Host smart-c751c971-284d-43ec-82d1-9614b66cc7f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2960311897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2960311897
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4187169295
Short name T864
Test name
Test status
Simulation time 66559029 ps
CPU time 0.84 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 196824 kb
Host smart-19b5de9d-f6a8-4f5d-ba2a-fd8e5d565ba2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187169295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4187169295
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4000214082
Short name T902
Test name
Test status
Simulation time 30636091 ps
CPU time 0.96 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 192140 kb
Host smart-273aa1a0-e934-485b-aae1-895ba74da0c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4000214082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.4000214082
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3103211544
Short name T919
Test name
Test status
Simulation time 83830494 ps
CPU time 0.69 seconds
Started Mar 28 12:49:14 PM PDT 24
Finished Mar 28 12:49:15 PM PDT 24
Peak memory 192044 kb
Host smart-c8879f09-77b3-47c8-a410-a0e28f28400c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103211544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3103211544
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2643076506
Short name T884
Test name
Test status
Simulation time 65503376 ps
CPU time 1.28 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 192240 kb
Host smart-f24854b4-4655-4ec7-b120-f26fdc19867f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2643076506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2643076506
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1551545821
Short name T904
Test name
Test status
Simulation time 253020530 ps
CPU time 1.13 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:19 PM PDT 24
Peak memory 192248 kb
Host smart-1ee6f239-cb94-44b1-a924-2538c94f854c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551545821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1551545821
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.989546620
Short name T912
Test name
Test status
Simulation time 169704706 ps
CPU time 0.99 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 192296 kb
Host smart-159e3b57-8a5e-4357-8664-af40b9a8e6e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=989546620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.989546620
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1210359843
Short name T916
Test name
Test status
Simulation time 75977385 ps
CPU time 1.14 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:01 PM PDT 24
Peak memory 192292 kb
Host smart-6e21210b-a9e7-4ed9-80d8-524d42330d22
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210359843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1210359843
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1377097591
Short name T927
Test name
Test status
Simulation time 378838767 ps
CPU time 1.18 seconds
Started Mar 28 12:49:14 PM PDT 24
Finished Mar 28 12:49:15 PM PDT 24
Peak memory 198536 kb
Host smart-7b8e4992-2997-46a6-b11d-3ce76233af8b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1377097591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1377097591
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1368883935
Short name T846
Test name
Test status
Simulation time 46532054 ps
CPU time 0.99 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 192384 kb
Host smart-667e7f24-3370-48f2-a59a-140da8196344
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368883935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1368883935
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2441330185
Short name T936
Test name
Test status
Simulation time 23292416 ps
CPU time 0.87 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:19 PM PDT 24
Peak memory 191972 kb
Host smart-9de7c997-97a3-47d3-b7d4-36281fe7b9cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2441330185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2441330185
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1881210193
Short name T872
Test name
Test status
Simulation time 55644080 ps
CPU time 1.42 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:19 PM PDT 24
Peak memory 192260 kb
Host smart-4aeed41c-7b06-4ecb-9abe-ae0b8521052b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881210193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1881210193
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1580229065
Short name T931
Test name
Test status
Simulation time 56921038 ps
CPU time 1.04 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 192124 kb
Host smart-535ad518-f21d-4cad-ac2b-de57fe9329b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1580229065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1580229065
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.365191438
Short name T842
Test name
Test status
Simulation time 68310113 ps
CPU time 1.16 seconds
Started Mar 28 12:49:15 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 192364 kb
Host smart-d773042d-36ec-470e-b9e7-bdf4f85cb0c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365191438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.365191438
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2774436385
Short name T937
Test name
Test status
Simulation time 58484910 ps
CPU time 1.21 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 198508 kb
Host smart-d361b967-b4cb-420d-8065-c05bad468337
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2774436385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2774436385
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1353174181
Short name T860
Test name
Test status
Simulation time 127547109 ps
CPU time 1.14 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:19 PM PDT 24
Peak memory 198288 kb
Host smart-60346a22-d092-44ba-864e-296493549210
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353174181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1353174181
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3947926895
Short name T903
Test name
Test status
Simulation time 243716448 ps
CPU time 1.31 seconds
Started Mar 28 12:49:13 PM PDT 24
Finished Mar 28 12:49:14 PM PDT 24
Peak memory 192316 kb
Host smart-93001c8e-4e76-47fa-a7d5-d22d03f0226e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3947926895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3947926895
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3706087739
Short name T897
Test name
Test status
Simulation time 360572843 ps
CPU time 1.25 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 192204 kb
Host smart-f7a3b106-0bc3-4c29-ad01-3b0f3aa53e32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706087739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3706087739
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.317609332
Short name T845
Test name
Test status
Simulation time 427411696 ps
CPU time 1.19 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 192300 kb
Host smart-6b9bec7e-3f5e-4550-9b35-9cdf1f1cce0d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=317609332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.317609332
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.10731713
Short name T856
Test name
Test status
Simulation time 55647561 ps
CPU time 1.1 seconds
Started Mar 28 12:49:15 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 192288 kb
Host smart-466220f7-ca48-470d-b11c-a3d3c8a81f6a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10731713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.10731713
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1277059672
Short name T914
Test name
Test status
Simulation time 264288491 ps
CPU time 1.12 seconds
Started Mar 28 12:49:22 PM PDT 24
Finished Mar 28 12:49:23 PM PDT 24
Peak memory 192188 kb
Host smart-9762ba4a-4ed9-4345-bc35-c7fc11ba7559
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1277059672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1277059672
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2001192706
Short name T898
Test name
Test status
Simulation time 96807261 ps
CPU time 1.1 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:19 PM PDT 24
Peak memory 192216 kb
Host smart-b4b7f638-0594-429a-bc87-a96bb1e16ee6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001192706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2001192706
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2938613209
Short name T848
Test name
Test status
Simulation time 215830276 ps
CPU time 1.03 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 192244 kb
Host smart-a58603eb-435d-4db1-8a7f-bf545dd327d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2938613209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2938613209
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2700523408
Short name T853
Test name
Test status
Simulation time 40019367 ps
CPU time 1.08 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 196816 kb
Host smart-0651ae56-1d54-4317-bde2-927a6db5a0db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700523408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2700523408
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.590682085
Short name T928
Test name
Test status
Simulation time 88379185 ps
CPU time 0.88 seconds
Started Mar 28 12:49:15 PM PDT 24
Finished Mar 28 12:49:16 PM PDT 24
Peak memory 192016 kb
Host smart-3f0c6e61-0465-4fc9-af61-e795326ff1dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=590682085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.590682085
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4189054349
Short name T851
Test name
Test status
Simulation time 142741173 ps
CPU time 1.17 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 197208 kb
Host smart-1ed76105-1f09-4721-ae6c-e847c786b294
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189054349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4189054349
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2538517202
Short name T843
Test name
Test status
Simulation time 183418090 ps
CPU time 0.99 seconds
Started Mar 28 12:49:15 PM PDT 24
Finished Mar 28 12:49:16 PM PDT 24
Peak memory 192332 kb
Host smart-36483b6b-e455-4ffd-bedf-49327f9b47e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2538517202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2538517202
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3932880834
Short name T888
Test name
Test status
Simulation time 318665525 ps
CPU time 1.54 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 198616 kb
Host smart-d657b7a7-dccc-4721-a73d-6f87a32b8e2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932880834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3932880834
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1179655248
Short name T858
Test name
Test status
Simulation time 87718130 ps
CPU time 0.95 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 197876 kb
Host smart-182c1a17-8be7-4676-86dd-c553ae5d5b9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1179655248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1179655248
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539288857
Short name T850
Test name
Test status
Simulation time 89666637 ps
CPU time 1.63 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 192288 kb
Host smart-ffc12058-1f9e-4c46-a048-241a04f5dcd6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539288857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2539288857
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3900547308
Short name T934
Test name
Test status
Simulation time 276410474 ps
CPU time 1.3 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 197180 kb
Host smart-121edb84-f7f7-4fc6-8bab-3fb41de85def
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3900547308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3900547308
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1246087491
Short name T867
Test name
Test status
Simulation time 296037934 ps
CPU time 1.45 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 198588 kb
Host smart-bdccd5cf-99f8-45c0-9f2f-a2d23a4b69c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246087491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1246087491
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2404650621
Short name T896
Test name
Test status
Simulation time 207052283 ps
CPU time 1.21 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:01 PM PDT 24
Peak memory 192288 kb
Host smart-738dbb7e-137b-4bb4-84bc-682f2f1cf43e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2404650621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2404650621
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3675639890
Short name T840
Test name
Test status
Simulation time 29511144 ps
CPU time 1 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 192176 kb
Host smart-be4b217e-f7ad-456f-ba65-d3dea7b4fc15
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675639890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3675639890
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.379112357
Short name T921
Test name
Test status
Simulation time 110589525 ps
CPU time 0.85 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 196764 kb
Host smart-e66409fd-807e-4edd-ba35-8aaa3e5a42a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=379112357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.379112357
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2754332053
Short name T930
Test name
Test status
Simulation time 60933906 ps
CPU time 1.24 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 198176 kb
Host smart-927621df-cfc1-478d-8d6a-54179c5fa12c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754332053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2754332053
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1568455265
Short name T844
Test name
Test status
Simulation time 36995637 ps
CPU time 1.05 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 192300 kb
Host smart-60be0cb1-0f23-4436-aa29-4ca16e1a03bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1568455265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1568455265
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999394854
Short name T880
Test name
Test status
Simulation time 186549337 ps
CPU time 0.9 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:49:00 PM PDT 24
Peak memory 192076 kb
Host smart-e1704e71-1d32-4f8a-a94a-2df62f0b01a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999394854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2999394854
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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