Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3753201	1			T20	1		T21	55		T22	64
all_pins[1]	3753201	1			T20	1		T21	55		T22	64
all_pins[2]	3753201	1			T20	1		T21	55		T22	64
all_pins[3]	3753201	1			T20	1		T21	55		T22	64
all_pins[4]	3753201	1			T20	1		T21	55		T22	64
all_pins[5]	3753201	1			T20	1		T21	55		T22	64
all_pins[6]	3753201	1			T20	1		T21	55		T22	64
all_pins[7]	3753201	1			T20	1		T21	55		T22	64
all_pins[8]	3753201	1			T20	1		T21	55		T22	64
all_pins[9]	3753201	1			T20	1		T21	55		T22	64
all_pins[10]	3753201	1			T20	1		T21	55		T22	64
all_pins[11]	3753201	1			T20	1		T21	55		T22	64
all_pins[12]	3753201	1			T20	1		T21	55		T22	64
all_pins[13]	3753201	1			T20	1		T21	55		T22	64
all_pins[14]	3753201	1			T20	1		T21	55		T22	64
all_pins[15]	3753201	1			T20	1		T21	55		T22	64
all_pins[16]	3753201	1			T20	1		T21	55		T22	64
all_pins[17]	3753201	1			T20	1		T21	55		T22	64
all_pins[18]	3753201	1			T20	1		T21	55		T22	64
all_pins[19]	3753201	1			T20	1		T21	55		T22	64
all_pins[20]	3753201	1			T20	1		T21	55		T22	64
all_pins[21]	3753201	1			T20	1		T21	55		T22	64
all_pins[22]	3753201	1			T20	1		T21	55		T22	64
all_pins[23]	3753201	1			T20	1		T21	55		T22	64
all_pins[24]	3753201	1			T20	1		T21	55		T22	64
all_pins[25]	3753201	1			T20	1		T21	55		T22	64
all_pins[26]	3753201	1			T20	1		T21	55		T22	64
all_pins[27]	3753201	1			T20	1		T21	55		T22	64
all_pins[28]	3753201	1			T20	1		T21	55		T22	64
all_pins[29]	3753201	1			T20	1		T21	55		T22	64
all_pins[30]	3753201	1			T20	1		T21	55		T22	64
all_pins[31]	3753201	1			T20	1		T21	55		T22	64

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	74587049	1			T20	32		T21	1402		T22	1135
values[0x1]	45515383	1			T21	358		T22	913		T24	5292
transitions[0x0=>0x1]	27274575	1			T21	240		T22	497		T24	3060
transitions[0x1=>0x0]	27274413	1			T21	240		T22	496		T24	3059

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2330867	1			T20	1		T21	48		T22	40
all_pins[0]	values[0x1]	1422334	1			T21	7		T22	24		T24	151
all_pins[0]	transitions[0x0=>0x1]	879279	1			T21	5		T22	16		T24	80
all_pins[0]	transitions[0x1=>0x0]	878944	1			T21	14		T22	14		T24	63
all_pins[1]	values[0x0]	2328305	1			T20	1		T21	37		T22	43
all_pins[1]	values[0x1]	1424896	1			T21	18		T22	21		T24	139
all_pins[1]	transitions[0x0=>0x1]	854184	1			T21	16		T22	13		T24	67
all_pins[1]	transitions[0x1=>0x0]	851622	1			T21	5		T22	16		T24	79
all_pins[2]	values[0x0]	2327961	1			T20	1		T21	44		T22	28
all_pins[2]	values[0x1]	1425240	1			T21	11		T22	36		T24	142
all_pins[2]	transitions[0x0=>0x1]	850962	1			T21	6		T22	29		T24	75
all_pins[2]	transitions[0x1=>0x0]	850618	1			T21	13		T22	14		T24	72
all_pins[3]	values[0x0]	2333662	1			T20	1		T21	39		T22	36
all_pins[3]	values[0x1]	1419539	1			T21	16		T22	28		T24	184
all_pins[3]	transitions[0x0=>0x1]	849193	1			T21	9		T22	10		T24	154
all_pins[3]	transitions[0x1=>0x0]	854894	1			T21	4		T22	18		T24	112
all_pins[4]	values[0x0]	2328324	1			T20	1		T21	47		T22	41
all_pins[4]	values[0x1]	1424877	1			T21	8		T22	23		T24	195
all_pins[4]	transitions[0x0=>0x1]	852566	1			T21	5		T22	11		T24	89
all_pins[4]	transitions[0x1=>0x0]	847228	1			T21	13		T22	16		T24	78
all_pins[5]	values[0x0]	2331350	1			T20	1		T21	44		T22	39
all_pins[5]	values[0x1]	1421851	1			T21	11		T22	25		T24	181
all_pins[5]	transitions[0x0=>0x1]	850278	1			T21	6		T22	14		T24	125
all_pins[5]	transitions[0x1=>0x0]	853304	1			T21	3		T22	12		T24	139
all_pins[6]	values[0x0]	2329822	1			T20	1		T21	44		T22	36
all_pins[6]	values[0x1]	1423379	1			T21	11		T22	28		T24	112
all_pins[6]	transitions[0x0=>0x1]	852541	1			T21	4		T22	13		T24	78
all_pins[6]	transitions[0x1=>0x0]	851013	1			T21	4		T22	10		T24	147
all_pins[7]	values[0x0]	2336192	1			T20	1		T21	46		T22	31
all_pins[7]	values[0x1]	1417009	1			T21	9		T22	33		T24	175
all_pins[7]	transitions[0x0=>0x1]	848817	1			T21	5		T22	18		T24	128
all_pins[7]	transitions[0x1=>0x0]	855187	1			T21	7		T22	13		T24	65
all_pins[8]	values[0x0]	2331402	1			T20	1		T21	39		T22	33
all_pins[8]	values[0x1]	1421799	1			T21	16		T22	31		T24	203
all_pins[8]	transitions[0x0=>0x1]	853048	1			T21	10		T22	16		T24	112
all_pins[8]	transitions[0x1=>0x0]	848258	1			T21	3		T22	18		T24	84
all_pins[9]	values[0x0]	2328153	1			T20	1		T21	45		T22	36
all_pins[9]	values[0x1]	1425048	1			T21	10		T22	28		T24	167
all_pins[9]	transitions[0x0=>0x1]	852858	1			T21	5		T22	18		T24	70
all_pins[9]	transitions[0x1=>0x0]	849609	1			T21	11		T22	21		T24	106
all_pins[10]	values[0x0]	2333158	1			T20	1		T21	42		T22	28
all_pins[10]	values[0x1]	1420043	1			T21	13		T22	36		T24	219
all_pins[10]	transitions[0x0=>0x1]	847453	1			T21	9		T22	18		T24	142
all_pins[10]	transitions[0x1=>0x0]	852458	1			T21	6		T22	10		T24	90
all_pins[11]	values[0x0]	2336997	1			T20	1		T21	35		T22	40
all_pins[11]	values[0x1]	1416204	1			T21	20		T22	24		T24	185
all_pins[11]	transitions[0x0=>0x1]	848871	1			T21	11		T22	9		T24	78
all_pins[11]	transitions[0x1=>0x0]	852710	1			T21	4		T22	21		T24	112
all_pins[12]	values[0x0]	2323372	1			T20	1		T21	54		T22	37
all_pins[12]	values[0x1]	1429829	1			T21	1		T22	27		T24	191
all_pins[12]	transitions[0x0=>0x1]	859018	1			T21	1		T22	14		T24	55
all_pins[12]	transitions[0x1=>0x0]	845393	1			T21	20		T22	11		T24	49
all_pins[13]	values[0x0]	2335489	1			T20	1		T21	45		T22	33
all_pins[13]	values[0x1]	1417712	1			T21	10		T22	31		T24	138
all_pins[13]	transitions[0x0=>0x1]	844152	1			T21	10		T22	18		T24	80
all_pins[13]	transitions[0x1=>0x0]	856269	1			T21	1		T22	14		T24	133
all_pins[14]	values[0x0]	2330072	1			T20	1		T21	47		T22	42
all_pins[14]	values[0x1]	1423129	1			T21	8		T22	22		T24	239
all_pins[14]	transitions[0x0=>0x1]	854611	1			T21	5		T22	12		T24	152
all_pins[14]	transitions[0x1=>0x0]	849194	1			T21	7		T22	21		T24	51
all_pins[15]	values[0x0]	2331257	1			T20	1		T21	43		T22	34
all_pins[15]	values[0x1]	1421944	1			T21	12		T22	30		T24	160
all_pins[15]	transitions[0x0=>0x1]	850288	1			T21	10		T22	20		T24	61
all_pins[15]	transitions[0x1=>0x0]	851473	1			T21	6		T22	12		T24	140
all_pins[16]	values[0x0]	2335282	1			T20	1		T21	43		T22	37
all_pins[16]	values[0x1]	1417919	1			T21	12		T22	27		T24	112
all_pins[16]	transitions[0x0=>0x1]	848364	1			T21	7		T22	12		T24	76
all_pins[16]	transitions[0x1=>0x0]	852389	1			T21	7		T22	15		T24	124
all_pins[17]	values[0x0]	2330345	1			T20	1		T21	44		T22	29
all_pins[17]	values[0x1]	1422856	1			T21	11		T22	35		T24	171
all_pins[17]	transitions[0x0=>0x1]	854414	1			T21	7		T22	22		T24	170
all_pins[17]	transitions[0x1=>0x0]	849477	1			T21	8		T22	14		T24	111
all_pins[18]	values[0x0]	2331618	1			T20	1		T21	47		T22	34
all_pins[18]	values[0x1]	1421583	1			T21	8		T22	30		T24	180
all_pins[18]	transitions[0x0=>0x1]	850910	1			T21	4		T22	10		T24	128
all_pins[18]	transitions[0x1=>0x0]	852183	1			T21	7		T22	15		T24	119
all_pins[19]	values[0x0]	2333865	1			T20	1		T21	38		T22	34
all_pins[19]	values[0x1]	1419336	1			T21	17		T22	30		T24	190
all_pins[19]	transitions[0x0=>0x1]	848865	1			T21	16		T22	17		T24	92
all_pins[19]	transitions[0x1=>0x0]	851112	1			T21	7		T22	17		T24	82
all_pins[20]	values[0x0]	2329972	1			T20	1		T21	31		T22	29
all_pins[20]	values[0x1]	1423229	1			T21	24		T22	35		T24	199
all_pins[20]	transitions[0x0=>0x1]	852065	1			T21	17		T22	20		T24	93
all_pins[20]	transitions[0x1=>0x0]	848172	1			T21	10		T22	15		T24	84
all_pins[21]	values[0x0]	2327113	1			T20	1		T21	40		T22	30
all_pins[21]	values[0x1]	1426088	1			T21	15		T22	34		T24	184
all_pins[21]	transitions[0x0=>0x1]	853957	1			T21	3		T22	14		T24	90
all_pins[21]	transitions[0x1=>0x0]	851098	1			T21	12		T22	15		T24	105
all_pins[22]	values[0x0]	2334440	1			T20	1		T21	41		T22	38
all_pins[22]	values[0x1]	1418761	1			T21	14		T22	26		T24	125
all_pins[22]	transitions[0x0=>0x1]	851796	1			T21	11		T22	12		T24	96
all_pins[22]	transitions[0x1=>0x0]	859123	1			T21	12		T22	20		T24	155
all_pins[23]	values[0x0]	2327387	1			T20	1		T21	54		T22	39
all_pins[23]	values[0x1]	1425814	1			T21	1		T22	25		T24	163
all_pins[23]	transitions[0x0=>0x1]	855114	1			T21	1		T22	16		T24	99
all_pins[23]	transitions[0x1=>0x0]	848061	1			T21	14		T22	17		T24	61
all_pins[24]	values[0x0]	2332396	1			T20	1		T21	52		T22	38
all_pins[24]	values[0x1]	1420805	1			T21	3		T22	26		T24	103
all_pins[24]	transitions[0x0=>0x1]	849731	1			T21	3		T22	18		T24	38
all_pins[24]	transitions[0x1=>0x0]	854740	1			T21	1		T22	17		T24	98
all_pins[25]	values[0x0]	2331766	1			T20	1		T21	39		T22	33
all_pins[25]	values[0x1]	1421435	1			T21	16		T22	31		T24	185
all_pins[25]	transitions[0x0=>0x1]	851559	1			T21	16		T22	18		T24	121
all_pins[25]	transitions[0x1=>0x0]	850929	1			T21	3		T22	13		T24	39
all_pins[26]	values[0x0]	2328390	1			T20	1		T21	41		T22	35
all_pins[26]	values[0x1]	1424811	1			T21	14		T22	29		T24	176
all_pins[26]	transitions[0x0=>0x1]	852727	1			T21	7		T22	18		T24	84
all_pins[26]	transitions[0x1=>0x0]	849351	1			T21	9		T22	20		T24	93
all_pins[27]	values[0x0]	2331712	1			T20	1		T21	44		T22	31
all_pins[27]	values[0x1]	1421489	1			T21	11		T22	33		T24	182
all_pins[27]	transitions[0x0=>0x1]	852336	1			T21	3		T22	21		T24	96
all_pins[27]	transitions[0x1=>0x0]	855658	1			T21	6		T22	17		T24	90
all_pins[28]	values[0x0]	2326994	1			T20	1		T21	46		T22	38
all_pins[28]	values[0x1]	1426207	1			T21	9		T22	26		T24	181
all_pins[28]	transitions[0x0=>0x1]	855313	1			T21	7		T22	11		T24	103
all_pins[28]	transitions[0x1=>0x0]	850595	1			T21	9		T22	18		T24	104
all_pins[29]	values[0x0]	2326126	1			T20	1		T21	52		T22	30
all_pins[29]	values[0x1]	1427075	1			T21	3		T22	34		T24	101
all_pins[29]	transitions[0x0=>0x1]	850708	1			T21	3		T22	19		T24	58
all_pins[29]	transitions[0x1=>0x0]	849840	1			T21	9		T22	11		T24	138
all_pins[30]	values[0x0]	2332220	1			T20	1		T21	52		T22	42
all_pins[30]	values[0x1]	1420981	1			T21	3		T22	22		T24	124
all_pins[30]	transitions[0x0=>0x1]	849521	1			T21	3		T22	8		T24	90
all_pins[30]	transitions[0x1=>0x0]	855615	1			T21	3		T22	20		T24	67
all_pins[31]	values[0x0]	2331040	1			T20	1		T21	39		T22	41
all_pins[31]	values[0x1]	1422161	1			T21	16		T22	23		T24	135
all_pins[31]	transitions[0x0=>0x1]	849076	1			T21	15		T22	12		T24	80
all_pins[31]	transitions[0x1=>0x0]	847896	1			T21	2		T22	11		T24	69