Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[1]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[2]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[3]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[4]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[5]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[6]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[7]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[8]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[9]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[10]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[11]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[12]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[13]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[14]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[15]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[16]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[17]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[18]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[19]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[20]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[21]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[22]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[23]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[24]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[25]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[26]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[27]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[28]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[29]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[30]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[31]	12538991	1			T20	237		T21	81		T22	31297

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237807173

1

T20

5410

T21

1125

T22

497454

auto[1]

163440539

1

T20

2174

T21

1467

T22

504050

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323041535

1

T20

4467

T21

2412

T22

100150

auto[1]

78206177

1

T20

3117

T21

180

T23

11253

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300161699

1

T20

4267

T21

2186

T22

100150

auto[1]

101086013

1

T20

3317

T21

406

T23

11012

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4660014	1			T20	64		T21	46		T22	14048
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3488880	1			T20	16		T21	30		T22	17249
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1231305	1			T20	42		T23	165		T25	20
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1540300	1			T20	65		T21	5		T25	84
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	398926	1			T23	216		T25	10		T26	9
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1219566	1			T20	50		T23	148		T25	11
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4661724	1			T20	77		T21	29		T22	15445
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3488579	1			T20	15		T21	32		T22	15852
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1229262	1			T20	54		T21	4		T23	199
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1542985	1			T20	48		T21	5		T25	76
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	399666	1			T21	3		T23	174		T25	5
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1216775	1			T20	43		T21	8		T23	162
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4661713	1			T20	76		T21	20		T22	15589
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3490270	1			T20	16		T21	50		T22	15708
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1231618	1			T20	34		T23	184		T25	10
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1540647	1			T20	49		T21	6		T25	63
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	398681	1			T21	2		T23	186		T25	9
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1216062	1			T20	62		T21	3		T23	185
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4654037	1			T20	86		T21	17		T22	16640
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3493980	1			T20	16		T21	37		T22	14657
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1227116	1			T20	35		T21	6		T23	142
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1545027	1			T20	54		T21	1		T25	66
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	399577	1			T21	8		T23	212		T25	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1219254	1			T20	46		T21	12		T23	147
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4654062	1			T20	65		T21	37		T22	15536
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3496300	1			T20	19		T21	30		T22	15761
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1228861	1			T20	50		T21	4		T23	186
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1538370	1			T20	68		T21	5		T25	82
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	398694	1			T21	3		T23	148		T25	10
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1222704	1			T20	35		T21	2		T23	187
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4653940	1			T20	76		T21	19		T22	16511
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3496906	1			T20	22		T21	52		T22	14786
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1228837	1			T20	52		T23	204		T25	40
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1542163	1			T20	51		T21	5		T25	69
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	399262	1			T21	2		T23	164		T25	7
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1217883	1			T20	36		T21	3		T23	144
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4655258	1			T20	49		T21	29		T22	15389
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3493914	1			T20	23		T21	36		T22	15908
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1227077	1			T20	50		T23	174		T25	26
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1543901	1			T20	53		T21	1		T25	96
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	400159	1			T21	5		T23	197		T25	19
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1218682	1			T20	62		T21	10		T23	154
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4656198	1			T20	61		T21	24		T22	14930
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3499109	1			T20	20		T21	30		T22	16367
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1230154	1			T20	52		T21	6		T23	213
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1540442	1			T20	32		T21	10		T25	57
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	397333	1			T21	3		T23	160		T25	7
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1215755	1			T20	72		T21	8		T23	192
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4667112	1			T20	75		T21	46		T22	16213
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3486470	1			T20	16		T21	30		T22	15084
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1232804	1			T20	42		T23	174		T25	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1534118	1			T20	54		T21	5		T25	100
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	398508	1			T23	172		T25	17		T26	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1219979	1			T20	50		T23	167		T25	10
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4656959	1			T20	53		T21	22		T22	14470
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3492614	1			T20	19		T21	45		T22	16827
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1232170	1			T20	34		T21	4		T23	196
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1537387	1			T20	64		T21	10		T25	84
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	399175	1			T23	163		T25	11		T26	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1220686	1			T20	67		T23	156		T25	36
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4675879	1			T20	44		T21	14		T22	16270
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3480131	1			T20	24		T21	52		T22	15027
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1226946	1			T20	50		T21	4		T23	192
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1539579	1			T20	57		T21	6		T25	91
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	397496	1			T21	3		T23	156		T25	19
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1218960	1			T20	62		T21	2		T23	228
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4671325	1			T20	78		T21	39		T22	16782
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3482583	1			T20	14		T21	26		T22	14515
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1227708	1			T20	65		T23	180		T25	50
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1539653	1			T20	32		T21	11		T25	23
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	401100	1			T21	3		T23	163		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1216622	1			T20	48		T21	2		T23	132
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4670417	1			T20	64		T21	24		T22	14746
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3482640	1			T20	17		T21	41		T22	16551
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1230803	1			T20	52		T23	174		T25	48
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1538436	1			T20	64		T21	11		T25	60
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	399702	1			T21	5		T23	172		T25	7
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1216993	1			T20	40		T23	175		T25	9
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4651177	1			T20	61		T21	26		T22	16044
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3494285	1			T20	21		T21	39		T22	15253
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1229826	1			T20	39		T21	6		T23	184
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1542583	1			T20	66		T25	97		T26	92
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	400546	1			T21	5		T23	164		T25	20
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1220574	1			T20	50		T21	5		T23	172
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4655050	1			T20	64		T21	31		T22	16142
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3498166	1			T20	22		T21	34		T22	15155
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1227041	1			T20	51		T23	182		T25	8
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1539564	1			T20	46		T21	10		T25	98
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	398510	1			T21	3		T23	197		T25	8
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1220660	1			T20	54		T21	3		T23	134
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4661437	1			T20	87		T21	29		T22	15636
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3496621	1			T20	13		T21	38		T22	15661
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1230497	1			T20	50		T21	4		T23	144
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1535074	1			T20	36		T25	84		T26	87
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	397330	1			T21	2		T23	163		T25	10
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1218032	1			T20	51		T21	8		T23	224
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4653122	1			T20	69		T21	34		T22	13832
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3502102	1			T20	19		T21	40		T22	17465
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1223829	1			T20	49		T23	178		T25	16
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1543957	1			T20	64		T21	2		T25	96
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	399408	1			T21	3		T23	181		T25	8
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1216573	1			T20	36		T21	2		T23	210
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4661514	1			T20	64		T21	29		T22	15823
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3496178	1			T20	18		T21	38		T22	15474
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1224817	1			T20	52		T23	182		T25	12
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1539938	1			T20	59		T21	8		T25	68
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	401363	1			T21	2		T23	130		T25	14
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1215181	1			T20	44		T21	4		T23	214
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4662402	1			T20	81		T21	33		T22	15919
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3486758	1			T20	19		T21	31		T22	15378
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1224721	1			T20	30		T21	5		T23	158
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1547428	1			T20	65		T21	11		T25	99
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	401190	1			T21	1		T23	165		T25	15
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1216492	1			T20	42		T23	166		T25	34
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4666660	1			T20	63		T21	21		T22	16022
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3485001	1			T20	19		T21	35		T22	15275
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1225936	1			T20	36		T23	163		T25	20
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1543795	1			T20	71		T21	5		T25	97
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	400354	1			T21	10		T23	158		T25	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1217245	1			T20	48		T21	10		T23	198
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4670556	1			T20	66		T21	29		T22	15786
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3480567	1			T20	18		T21	37		T22	15511
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1223253	1			T20	46		T23	194		T25	38
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1543628	1			T20	64		T21	5		T25	40
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	403008	1			T21	6		T23	173		T25	6
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1217979	1			T20	43		T21	4		T23	162
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4665473	1			T20	70		T21	27		T22	14954
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3491518	1			T20	22		T21	45		T22	16343
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1225610	1			T20	62		T21	4		T23	126
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1540712	1			T20	44		T25	98		T26	84
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	402294	1			T21	2		T23	232		T25	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1213384	1			T20	39		T21	3		T23	127
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4665937	1			T20	55		T21	33		T22	15344
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3491317	1			T20	19		T21	38		T22	15953
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1225688	1			T20	39		T21	3		T23	169
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1538668	1			T20	58		T21	2		T25	43
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	401182	1			T21	2		T23	168		T25	10
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1216199	1			T20	66		T21	3		T23	192
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4664297	1			T20	63		T21	40		T22	16137
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3487825	1			T20	13		T21	27		T22	15160
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1225185	1			T20	66		T23	161		T25	40
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1542884	1			T20	45		T21	14		T25	70
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	403815	1			T23	164		T25	13		T26	9
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1214985	1			T20	50		T23	192		T25	20
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4669824	1			T20	63		T21	23		T22	16177
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3485772	1			T20	18		T21	37		T22	15120
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1221506	1			T20	64		T23	178		T25	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1546019	1			T20	40		T21	2		T25	99
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	401268	1			T21	11		T23	136		T25	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1214602	1			T20	52		T21	8		T23	219
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4675993	1			T20	82		T21	23		T22	15444
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3487049	1			T20	18		T21	43		T22	15853
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1220610	1			T20	34		T23	196		T25	28
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1543435	1			T20	69		T21	2		T25	64
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	400357	1			T21	8		T23	150		T25	7
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1211547	1			T20	34		T21	5		T23	141
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4667804	1			T20	39		T21	13		T22	16162
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3488088	1			T20	27		T21	62		T22	15135
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1223288	1			T20	72		T23	166		T25	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1544156	1			T20	35		T25	110		T26	65
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	401727	1			T21	2		T23	128		T25	8
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1213928	1			T20	64		T21	4		T23	183
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4661482	1			T20	70		T21	26		T22	14074
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3498494	1			T20	18		T21	38		T22	17223
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1221690	1			T20	50		T23	161		T25	48
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1543687	1			T20	64		T25	53		T26	83
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	403657	1			T21	11		T23	168		T25	14
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1209981	1			T20	35		T21	6		T23	184
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4671127	1			T20	82		T21	52		T22	15986
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3486447	1			T20	14		T21	23		T22	15311
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1226063	1			T20	33		T23	160		T25	26
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1538156	1			T20	60		T25	50		T26	112
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	399910	1			T21	2		T23	175		T25	14
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1217288	1			T20	48		T21	4		T23	164
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4663904	1			T20	74		T21	22		T22	16249
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3488292	1			T20	16		T21	39		T22	15048
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1222173	1			T20	47		T23	192		T25	26
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1549299	1			T20	46		T21	14		T25	60
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	400582	1			T21	2		T23	175		T25	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1214741	1			T20	54		T21	4		T23	164
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4660795	1			T20	77		T21	30		T22	13975
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3488631	1			T20	13		T21	37		T22	17322
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1223668	1			T20	51		T21	3		T23	198
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1546197	1			T20	46		T21	5		T25	130
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	398762	1			T21	6		T23	169		T25	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1220938	1			T20	50		T23	162		T25	20
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4667394	1			T20	58		T21	21		T22	15179
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3482583	1			T20	20		T21	52		T22	16118
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1228981	1			T20	44		T21	1		T23	193
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1541356	1			T20	58		T21	2		T25	84
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	401793	1			T21	2		T23	148		T25	8
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1216884	1			T20	57		T21	3		T23	200

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal