Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[1]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[2]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[3]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[4]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[5]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[6]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[7]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[8]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[9]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[10]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[11]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[12]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[13]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[14]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[15]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[16]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[17]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[18]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[19]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[20]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[21]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[22]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[23]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[24]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[25]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[26]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[27]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[28]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[29]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[30]	12538991	1			T20	237		T21	81		T22	31297
bins_for_gpio_bits[31]	12538991	1			T20	237		T21	81		T22	31297

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237807173

1

T20

5410

T21

1125

T22

497454

auto[1]

163440539

1

T20

2174

T21

1467

T22

504050

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237798887

1

T20

5402

T21

1133

T22

497454

auto[1]

163448825

1

T20

2182

T21

1459

T22

504050

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7212396	1			T20	159		T21	51		T22	14048
bins_for_gpio_bits[0]	auto[0]	auto[1]	218971	1			T20	12		T23	42		T25	3
bins_for_gpio_bits[0]	auto[1]	auto[0]	219223	1			T20	12		T23	41		T25	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	4888401	1			T20	54		T21	30		T22	17249
bins_for_gpio_bits[1]	auto[0]	auto[0]	7215750	1			T20	166		T21	38		T22	15445
bins_for_gpio_bits[1]	auto[0]	auto[1]	217915	1			T20	12		T21	1		T23	52
bins_for_gpio_bits[1]	auto[1]	auto[0]	218221	1			T20	13		T23	51		T25	3
bins_for_gpio_bits[1]	auto[1]	auto[1]	4887105	1			T20	46		T21	42		T22	15852
bins_for_gpio_bits[2]	auto[0]	auto[0]	7215106	1			T20	147		T21	26		T22	15589
bins_for_gpio_bits[2]	auto[0]	auto[1]	218623	1			T20	12		T23	43		T25	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	218872	1			T20	12		T23	43		T25	3
bins_for_gpio_bits[2]	auto[1]	auto[1]	4886390	1			T20	66		T21	55		T22	15708
bins_for_gpio_bits[3]	auto[0]	auto[0]	7207135	1			T20	163		T21	24		T22	16640
bins_for_gpio_bits[3]	auto[0]	auto[1]	218804	1			T20	12		T21	1		T23	42
bins_for_gpio_bits[3]	auto[1]	auto[0]	219045	1			T20	12		T23	42		T25	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	4894007	1			T20	50		T21	56		T22	14657
bins_for_gpio_bits[4]	auto[0]	auto[0]	7202113	1			T20	171		T21	46		T22	15536
bins_for_gpio_bits[4]	auto[0]	auto[1]	218913	1			T20	11		T21	1		T23	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	219180	1			T20	12		T23	46		T25	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	4898785	1			T20	43		T21	34		T22	15761
bins_for_gpio_bits[5]	auto[0]	auto[0]	7205657	1			T20	166		T21	24		T22	16511
bins_for_gpio_bits[5]	auto[0]	auto[1]	218998	1			T20	13		T23	48		T25	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	219283	1			T20	13		T23	48		T25	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	4895053	1			T20	45		T21	57		T22	14786
bins_for_gpio_bits[6]	auto[0]	auto[0]	7207531	1			T20	135		T21	30		T22	15389
bins_for_gpio_bits[6]	auto[0]	auto[1]	218454	1			T20	17		T23	42		T25	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	218705	1			T20	17		T23	42		T25	6
bins_for_gpio_bits[6]	auto[1]	auto[1]	4894301	1			T20	68		T21	51		T22	15908
bins_for_gpio_bits[7]	auto[0]	auto[0]	7207702	1			T20	133		T21	40		T22	14930
bins_for_gpio_bits[7]	auto[0]	auto[1]	218847	1			T20	12		T21	1		T23	42
bins_for_gpio_bits[7]	auto[1]	auto[0]	219092	1			T20	12		T23	41		T25	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	4893350	1			T20	80		T21	40		T22	16367
bins_for_gpio_bits[8]	auto[0]	auto[0]	7214977	1			T20	158		T21	51		T22	16213
bins_for_gpio_bits[8]	auto[0]	auto[1]	218830	1			T20	13		T23	49		T25	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	219057	1			T20	13		T23	49		T25	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	4886127	1			T20	53		T21	30		T22	15084
bins_for_gpio_bits[9]	auto[0]	auto[0]	7207036	1			T20	137		T21	36		T22	14470
bins_for_gpio_bits[9]	auto[0]	auto[1]	219215	1			T20	13		T21	1		T23	44
bins_for_gpio_bits[9]	auto[1]	auto[0]	219480	1			T20	14		T23	44		T25	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	4893260	1			T20	73		T21	44		T22	16827
bins_for_gpio_bits[10]	auto[0]	auto[0]	7223257	1			T20	139		T21	24		T22	16270
bins_for_gpio_bits[10]	auto[0]	auto[1]	218883	1			T20	12		T21	1		T23	48
bins_for_gpio_bits[10]	auto[1]	auto[0]	219147	1			T20	12		T23	48		T25	8
bins_for_gpio_bits[10]	auto[1]	auto[1]	4877704	1			T20	74		T21	56		T22	15027
bins_for_gpio_bits[11]	auto[0]	auto[0]	7220212	1			T20	164		T21	50		T22	16782
bins_for_gpio_bits[11]	auto[0]	auto[1]	218200	1			T20	11		T23	48		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	218474	1			T20	11		T23	48		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	4882105	1			T20	51		T21	31		T22	14515
bins_for_gpio_bits[12]	auto[0]	auto[0]	7221159	1			T20	167		T21	35		T22	14746
bins_for_gpio_bits[12]	auto[0]	auto[1]	218198	1			T20	13		T23	45		T25	3
bins_for_gpio_bits[12]	auto[1]	auto[0]	218497	1			T20	13		T23	45		T25	3
bins_for_gpio_bits[12]	auto[1]	auto[1]	4881137	1			T20	44		T21	46		T22	16551
bins_for_gpio_bits[13]	auto[0]	auto[0]	7204190	1			T20	157		T21	32		T22	16044
bins_for_gpio_bits[13]	auto[0]	auto[1]	219122	1			T20	9		T21	1		T23	48
bins_for_gpio_bits[13]	auto[1]	auto[0]	219396	1			T20	9		T23	48		T25	6
bins_for_gpio_bits[13]	auto[1]	auto[1]	4896283	1			T20	62		T21	48		T22	15253
bins_for_gpio_bits[14]	auto[0]	auto[0]	7202714	1			T20	149		T21	41		T22	16142
bins_for_gpio_bits[14]	auto[0]	auto[1]	218684	1			T20	12		T23	38		T25	5
bins_for_gpio_bits[14]	auto[1]	auto[0]	218941	1			T20	12		T23	38		T25	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	4898652	1			T20	64		T21	40		T22	15155
bins_for_gpio_bits[15]	auto[0]	auto[0]	7208665	1			T20	160		T21	33		T22	15636
bins_for_gpio_bits[15]	auto[0]	auto[1]	218112	1			T20	12		T21	1		T23	47
bins_for_gpio_bits[15]	auto[1]	auto[0]	218343	1			T20	13		T23	47		T25	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	4893871	1			T20	52		T21	47		T22	15661
bins_for_gpio_bits[16]	auto[0]	auto[0]	7201767	1			T20	172		T21	36		T22	13832
bins_for_gpio_bits[16]	auto[0]	auto[1]	218889	1			T20	10		T23	45		T25	3
bins_for_gpio_bits[16]	auto[1]	auto[0]	219141	1			T20	10		T23	45		T25	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	4899194	1			T20	45		T21	45		T22	17465
bins_for_gpio_bits[17]	auto[0]	auto[0]	7207609	1			T20	162		T21	37		T22	15823
bins_for_gpio_bits[17]	auto[0]	auto[1]	218434	1			T20	13		T23	47		T25	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	218660	1			T20	13		T23	47		T25	2
bins_for_gpio_bits[17]	auto[1]	auto[1]	4894288	1			T20	49		T21	44		T22	15474
bins_for_gpio_bits[18]	auto[0]	auto[0]	7215563	1			T20	165		T21	48		T22	15919
bins_for_gpio_bits[18]	auto[0]	auto[1]	218713	1			T20	11		T21	1		T23	41
bins_for_gpio_bits[18]	auto[1]	auto[0]	218988	1			T20	11		T21	1		T23	41
bins_for_gpio_bits[18]	auto[1]	auto[1]	4885727	1			T20	50		T21	31		T22	15378
bins_for_gpio_bits[19]	auto[0]	auto[0]	7216870	1			T20	154		T21	26		T22	16022
bins_for_gpio_bits[19]	auto[0]	auto[1]	219264	1			T20	16		T23	48		T25	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	219521	1			T20	16		T23	47		T25	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	4883336	1			T20	51		T21	55		T22	15275
bins_for_gpio_bits[20]	auto[0]	auto[0]	7218627	1			T20	164		T21	34		T22	15786
bins_for_gpio_bits[20]	auto[0]	auto[1]	218527	1			T20	11		T23	49		T25	3
bins_for_gpio_bits[20]	auto[1]	auto[0]	218810	1			T20	12		T23	49		T25	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	4883027	1			T20	50		T21	47		T22	15511
bins_for_gpio_bits[21]	auto[0]	auto[0]	7213213	1			T20	167		T21	30		T22	14954
bins_for_gpio_bits[21]	auto[0]	auto[1]	218370	1			T20	8		T21	1		T23	34
bins_for_gpio_bits[21]	auto[1]	auto[0]	218582	1			T20	9		T21	1		T23	34
bins_for_gpio_bits[21]	auto[1]	auto[1]	4888826	1			T20	53		T21	49		T22	16343
bins_for_gpio_bits[22]	auto[0]	auto[0]	7210923	1			T20	141		T21	37		T22	15344
bins_for_gpio_bits[22]	auto[0]	auto[1]	219134	1			T20	11		T21	1		T23	48
bins_for_gpio_bits[22]	auto[1]	auto[0]	219370	1			T20	11		T21	1		T23	47
bins_for_gpio_bits[22]	auto[1]	auto[1]	4889564	1			T20	74		T21	42		T22	15953
bins_for_gpio_bits[23]	auto[0]	auto[0]	7213539	1			T20	161		T21	54		T22	16137
bins_for_gpio_bits[23]	auto[0]	auto[1]	218603	1			T20	13		T23	44		T25	5
bins_for_gpio_bits[23]	auto[1]	auto[0]	218827	1			T20	13		T23	43		T25	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	4888022	1			T20	50		T21	27		T22	15160
bins_for_gpio_bits[24]	auto[0]	auto[0]	7218739	1			T20	156		T21	25		T22	16177
bins_for_gpio_bits[24]	auto[0]	auto[1]	218339	1			T20	11		T23	49		T25	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	218610	1			T20	11		T23	49		T25	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	4883303	1			T20	59		T21	56		T22	15120
bins_for_gpio_bits[25]	auto[0]	auto[0]	7221409	1			T20	173		T21	25		T22	15444
bins_for_gpio_bits[25]	auto[0]	auto[1]	218340	1			T20	12		T23	52		T25	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	218629	1			T20	12		T23	52		T25	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	4880613	1			T20	40		T21	56		T22	15853
bins_for_gpio_bits[26]	auto[0]	auto[0]	7217119	1			T20	130		T21	13		T22	16162
bins_for_gpio_bits[26]	auto[0]	auto[1]	217916	1			T20	16		T23	44		T25	5
bins_for_gpio_bits[26]	auto[1]	auto[0]	218129	1			T20	16		T23	44		T25	5
bins_for_gpio_bits[26]	auto[1]	auto[1]	4885827	1			T20	75		T21	68		T22	15135
bins_for_gpio_bits[27]	auto[0]	auto[0]	7208811	1			T20	174		T21	26		T22	14074
bins_for_gpio_bits[27]	auto[0]	auto[1]	217767	1			T20	9		T23	44		T25	3
bins_for_gpio_bits[27]	auto[1]	auto[0]	218048	1			T20	10		T23	43		T25	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	4894365	1			T20	44		T21	55		T22	17223
bins_for_gpio_bits[28]	auto[0]	auto[0]	7216043	1			T20	166		T21	52		T22	15986
bins_for_gpio_bits[28]	auto[0]	auto[1]	219058	1			T20	9		T23	40		T25	4
bins_for_gpio_bits[28]	auto[1]	auto[0]	219303	1			T20	9		T23	40		T25	4
bins_for_gpio_bits[28]	auto[1]	auto[1]	4884587	1			T20	53		T21	29		T22	15311
bins_for_gpio_bits[29]	auto[0]	auto[0]	7216522	1			T20	155		T21	36		T22	16249
bins_for_gpio_bits[29]	auto[0]	auto[1]	218599	1			T20	12		T23	45		T25	4
bins_for_gpio_bits[29]	auto[1]	auto[0]	218854	1			T20	12		T23	45		T25	4
bins_for_gpio_bits[29]	auto[1]	auto[1]	4885016	1			T20	58		T21	45		T22	15048
bins_for_gpio_bits[30]	auto[0]	auto[0]	7210750	1			T20	159		T21	37		T22	13975
bins_for_gpio_bits[30]	auto[0]	auto[1]	219627	1			T20	15		T21	1		T23	51
bins_for_gpio_bits[30]	auto[1]	auto[0]	219910	1			T20	15		T21	1		T23	51
bins_for_gpio_bits[30]	auto[1]	auto[1]	4888704	1			T20	48		T21	42		T22	17322
bins_for_gpio_bits[31]	auto[0]	auto[0]	7218835	1			T20	147		T21	24		T22	15179
bins_for_gpio_bits[31]	auto[0]	auto[1]	218599	1			T20	12		T23	44		T25	3
bins_for_gpio_bits[31]	auto[1]	auto[0]	218896	1			T20	13		T23	43		T25	3
bins_for_gpio_bits[31]	auto[1]	auto[1]	4882661	1			T20	65		T21	57		T22	16118