Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431336 |
1 |
|
|
T20 |
137 |
|
T21 |
55 |
|
T22 |
31297 |
| auto[1] |
5307210 |
1 |
|
|
T21 |
25 |
|
T24 |
422 |
|
T28 |
1367 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12060800 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
677746 |
1 |
|
|
T21 |
1 |
|
T24 |
69 |
|
T28 |
294 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447416 |
1 |
|
|
T20 |
137 |
|
T21 |
63 |
|
T22 |
31297 |
| auto[1] |
5291130 |
1 |
|
|
T21 |
17 |
|
T24 |
346 |
|
T28 |
1548 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2312353 |
1 |
|
|
T21 |
12 |
|
T24 |
157 |
|
T28 |
722 |
| auto[1] |
auto[0] |
auto[1] |
339411 |
1 |
|
|
T24 |
36 |
|
T28 |
169 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2301031 |
1 |
|
|
T21 |
4 |
|
T24 |
120 |
|
T28 |
532 |
| auto[1] |
auto[1] |
auto[1] |
338335 |
1 |
|
|
T21 |
1 |
|
T24 |
33 |
|
T28 |
125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7420435 |
1 |
|
|
T20 |
137 |
|
T21 |
50 |
|
T22 |
31297 |
| auto[1] |
5318111 |
1 |
|
|
T21 |
30 |
|
T24 |
366 |
|
T28 |
1665 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12063296 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
675250 |
1 |
|
|
T24 |
112 |
|
T28 |
297 |
|
T36 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7451268 |
1 |
|
|
T20 |
137 |
|
T21 |
38 |
|
T22 |
31297 |
| auto[1] |
5287278 |
1 |
|
|
T21 |
42 |
|
T24 |
546 |
|
T28 |
1468 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2304702 |
1 |
|
|
T21 |
28 |
|
T24 |
322 |
|
T28 |
525 |
| auto[1] |
auto[0] |
auto[1] |
337278 |
1 |
|
|
T24 |
83 |
|
T28 |
129 |
|
T1 |
3327 |
| auto[1] |
auto[1] |
auto[0] |
2307326 |
1 |
|
|
T21 |
14 |
|
T24 |
112 |
|
T28 |
646 |
| auto[1] |
auto[1] |
auto[1] |
337972 |
1 |
|
|
T24 |
29 |
|
T28 |
168 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449507 |
1 |
|
|
T20 |
137 |
|
T21 |
32 |
|
T22 |
31297 |
| auto[1] |
5289039 |
1 |
|
|
T21 |
48 |
|
T24 |
693 |
|
T28 |
1064 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12065672 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
672874 |
1 |
|
|
T24 |
81 |
|
T28 |
282 |
|
T36 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469549 |
1 |
|
|
T20 |
137 |
|
T21 |
50 |
|
T22 |
31297 |
| auto[1] |
5268997 |
1 |
|
|
T21 |
30 |
|
T24 |
450 |
|
T28 |
1439 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2297801 |
1 |
|
|
T24 |
125 |
|
T28 |
693 |
|
T36 |
30 |
| auto[1] |
auto[0] |
auto[1] |
336867 |
1 |
|
|
T24 |
27 |
|
T28 |
171 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2298322 |
1 |
|
|
T21 |
30 |
|
T24 |
244 |
|
T28 |
464 |
| auto[1] |
auto[1] |
auto[1] |
336007 |
1 |
|
|
T24 |
54 |
|
T28 |
111 |
|
T1 |
3066 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7462538 |
1 |
|
|
T20 |
137 |
|
T21 |
41 |
|
T22 |
31297 |
| auto[1] |
5276008 |
1 |
|
|
T21 |
39 |
|
T24 |
582 |
|
T28 |
1595 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12064098 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
674448 |
1 |
|
|
T21 |
1 |
|
T24 |
54 |
|
T28 |
255 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7467990 |
1 |
|
|
T20 |
137 |
|
T21 |
48 |
|
T22 |
31297 |
| auto[1] |
5270556 |
1 |
|
|
T21 |
32 |
|
T24 |
268 |
|
T28 |
1301 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2305834 |
1 |
|
|
T21 |
10 |
|
T24 |
94 |
|
T28 |
536 |
| auto[1] |
auto[0] |
auto[1] |
339143 |
1 |
|
|
T24 |
25 |
|
T28 |
127 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2290274 |
1 |
|
|
T21 |
21 |
|
T24 |
120 |
|
T28 |
510 |
| auto[1] |
auto[1] |
auto[1] |
335305 |
1 |
|
|
T21 |
1 |
|
T24 |
29 |
|
T28 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447171 |
1 |
|
|
T20 |
137 |
|
T21 |
63 |
|
T22 |
31297 |
| auto[1] |
5291375 |
1 |
|
|
T21 |
17 |
|
T24 |
540 |
|
T28 |
1438 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12059427 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
679119 |
1 |
|
|
T24 |
106 |
|
T28 |
359 |
|
T36 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431388 |
1 |
|
|
T20 |
137 |
|
T21 |
49 |
|
T22 |
31297 |
| auto[1] |
5307158 |
1 |
|
|
T21 |
31 |
|
T24 |
549 |
|
T28 |
1794 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2311145 |
1 |
|
|
T21 |
25 |
|
T24 |
269 |
|
T28 |
766 |
| auto[1] |
auto[0] |
auto[1] |
338854 |
1 |
|
|
T24 |
62 |
|
T28 |
196 |
|
T1 |
3709 |
| auto[1] |
auto[1] |
auto[0] |
2316894 |
1 |
|
|
T21 |
6 |
|
T24 |
174 |
|
T28 |
669 |
| auto[1] |
auto[1] |
auto[1] |
340265 |
1 |
|
|
T24 |
44 |
|
T28 |
163 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459740 |
1 |
|
|
T20 |
137 |
|
T21 |
39 |
|
T22 |
31297 |
| auto[1] |
5278806 |
1 |
|
|
T21 |
41 |
|
T24 |
456 |
|
T28 |
1119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12057925 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
680621 |
1 |
|
|
T21 |
1 |
|
T24 |
135 |
|
T28 |
286 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7422538 |
1 |
|
|
T20 |
137 |
|
T21 |
54 |
|
T22 |
31297 |
| auto[1] |
5316008 |
1 |
|
|
T21 |
26 |
|
T24 |
648 |
|
T28 |
1476 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2324378 |
1 |
|
|
T21 |
11 |
|
T24 |
326 |
|
T28 |
716 |
| auto[1] |
auto[0] |
auto[1] |
341976 |
1 |
|
|
T24 |
88 |
|
T28 |
173 |
|
T1 |
3369 |
| auto[1] |
auto[1] |
auto[0] |
2311009 |
1 |
|
|
T21 |
14 |
|
T24 |
187 |
|
T28 |
474 |
| auto[1] |
auto[1] |
auto[1] |
338645 |
1 |
|
|
T21 |
1 |
|
T24 |
47 |
|
T28 |
113 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426198 |
1 |
|
|
T20 |
137 |
|
T21 |
46 |
|
T22 |
31297 |
| auto[1] |
5312348 |
1 |
|
|
T21 |
34 |
|
T24 |
678 |
|
T28 |
1359 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12061571 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
676975 |
1 |
|
|
T24 |
32 |
|
T28 |
282 |
|
T36 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452093 |
1 |
|
|
T20 |
137 |
|
T21 |
49 |
|
T22 |
31297 |
| auto[1] |
5286453 |
1 |
|
|
T21 |
31 |
|
T24 |
186 |
|
T28 |
1486 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2291783 |
1 |
|
|
T21 |
17 |
|
T24 |
89 |
|
T28 |
556 |
| auto[1] |
auto[0] |
auto[1] |
335824 |
1 |
|
|
T24 |
20 |
|
T28 |
138 |
|
T1 |
3391 |
| auto[1] |
auto[1] |
auto[0] |
2317695 |
1 |
|
|
T21 |
14 |
|
T24 |
65 |
|
T28 |
648 |
| auto[1] |
auto[1] |
auto[1] |
341151 |
1 |
|
|
T24 |
12 |
|
T28 |
144 |
|
T36 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443437 |
1 |
|
|
T20 |
137 |
|
T21 |
40 |
|
T22 |
31297 |
| auto[1] |
5295109 |
1 |
|
|
T21 |
40 |
|
T24 |
667 |
|
T28 |
1490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12062144 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
676402 |
1 |
|
|
T24 |
126 |
|
T28 |
306 |
|
T36 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7454164 |
1 |
|
|
T20 |
137 |
|
T21 |
73 |
|
T22 |
31297 |
| auto[1] |
5284382 |
1 |
|
|
T21 |
7 |
|
T24 |
632 |
|
T28 |
1531 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2302113 |
1 |
|
|
T21 |
3 |
|
T24 |
211 |
|
T28 |
610 |
| auto[1] |
auto[0] |
auto[1] |
336571 |
1 |
|
|
T24 |
50 |
|
T28 |
152 |
|
T36 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2305867 |
1 |
|
|
T21 |
4 |
|
T24 |
295 |
|
T28 |
615 |
| auto[1] |
auto[1] |
auto[1] |
339831 |
1 |
|
|
T24 |
76 |
|
T28 |
154 |
|
T36 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470601 |
1 |
|
|
T20 |
137 |
|
T21 |
47 |
|
T22 |
31297 |
| auto[1] |
5267945 |
1 |
|
|
T21 |
33 |
|
T24 |
367 |
|
T28 |
1398 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12062938 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
675608 |
1 |
|
|
T21 |
1 |
|
T24 |
139 |
|
T28 |
256 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7451172 |
1 |
|
|
T20 |
137 |
|
T21 |
48 |
|
T22 |
31297 |
| auto[1] |
5287374 |
1 |
|
|
T21 |
32 |
|
T24 |
737 |
|
T28 |
1274 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2317669 |
1 |
|
|
T21 |
15 |
|
T24 |
475 |
|
T28 |
556 |
| auto[1] |
auto[0] |
auto[1] |
339788 |
1 |
|
|
T24 |
108 |
|
T28 |
147 |
|
T36 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2294097 |
1 |
|
|
T21 |
16 |
|
T24 |
123 |
|
T28 |
462 |
| auto[1] |
auto[1] |
auto[1] |
335820 |
1 |
|
|
T21 |
1 |
|
T24 |
31 |
|
T28 |
109 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7424419 |
1 |
|
|
T20 |
137 |
|
T21 |
57 |
|
T22 |
31297 |
| auto[1] |
5314127 |
1 |
|
|
T21 |
23 |
|
T24 |
599 |
|
T28 |
1099 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12060845 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
677701 |
1 |
|
|
T24 |
107 |
|
T28 |
307 |
|
T36 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7438584 |
1 |
|
|
T20 |
137 |
|
T21 |
76 |
|
T22 |
31297 |
| auto[1] |
5299962 |
1 |
|
|
T21 |
4 |
|
T24 |
571 |
|
T28 |
1558 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2308386 |
1 |
|
|
T21 |
4 |
|
T24 |
166 |
|
T28 |
864 |
| auto[1] |
auto[0] |
auto[1] |
338339 |
1 |
|
|
T24 |
38 |
|
T28 |
215 |
|
T1 |
3765 |
| auto[1] |
auto[1] |
auto[0] |
2313875 |
1 |
|
|
T24 |
298 |
|
T28 |
387 |
|
T36 |
32 |
| auto[1] |
auto[1] |
auto[1] |
339362 |
1 |
|
|
T24 |
69 |
|
T28 |
92 |
|
T36 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425529 |
1 |
|
|
T20 |
137 |
|
T21 |
64 |
|
T22 |
31297 |
| auto[1] |
5313017 |
1 |
|
|
T21 |
16 |
|
T24 |
673 |
|
T28 |
1612 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12062849 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
675697 |
1 |
|
|
T21 |
1 |
|
T24 |
83 |
|
T28 |
374 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7457143 |
1 |
|
|
T20 |
137 |
|
T21 |
54 |
|
T22 |
31297 |
| auto[1] |
5281403 |
1 |
|
|
T21 |
26 |
|
T24 |
437 |
|
T28 |
1896 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2298002 |
1 |
|
|
T21 |
19 |
|
T24 |
169 |
|
T28 |
704 |
| auto[1] |
auto[0] |
auto[1] |
335673 |
1 |
|
|
T21 |
1 |
|
T24 |
44 |
|
T28 |
175 |
| auto[1] |
auto[1] |
auto[0] |
2307704 |
1 |
|
|
T21 |
6 |
|
T24 |
185 |
|
T28 |
818 |
| auto[1] |
auto[1] |
auto[1] |
340024 |
1 |
|
|
T24 |
39 |
|
T28 |
199 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449606 |
1 |
|
|
T20 |
137 |
|
T21 |
51 |
|
T22 |
31297 |
| auto[1] |
5288940 |
1 |
|
|
T21 |
29 |
|
T24 |
597 |
|
T28 |
1887 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12066184 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
672362 |
1 |
|
|
T24 |
169 |
|
T28 |
295 |
|
T36 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7474507 |
1 |
|
|
T20 |
137 |
|
T21 |
64 |
|
T22 |
31297 |
| auto[1] |
5264039 |
1 |
|
|
T21 |
16 |
|
T24 |
792 |
|
T28 |
1538 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2287745 |
1 |
|
|
T21 |
7 |
|
T24 |
334 |
|
T28 |
403 |
| auto[1] |
auto[0] |
auto[1] |
334966 |
1 |
|
|
T24 |
89 |
|
T28 |
91 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2303932 |
1 |
|
|
T21 |
9 |
|
T24 |
289 |
|
T28 |
840 |
| auto[1] |
auto[1] |
auto[1] |
337396 |
1 |
|
|
T24 |
80 |
|
T28 |
204 |
|
T1 |
3227 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7414061 |
1 |
|
|
T20 |
137 |
|
T21 |
46 |
|
T22 |
31297 |
| auto[1] |
5324485 |
1 |
|
|
T21 |
34 |
|
T24 |
438 |
|
T28 |
1629 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12061244 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
677302 |
1 |
|
|
T24 |
101 |
|
T28 |
273 |
|
T36 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7438494 |
1 |
|
|
T20 |
137 |
|
T21 |
61 |
|
T22 |
31297 |
| auto[1] |
5300052 |
1 |
|
|
T21 |
19 |
|
T24 |
568 |
|
T28 |
1455 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2308134 |
1 |
|
|
T21 |
13 |
|
T24 |
322 |
|
T28 |
605 |
| auto[1] |
auto[0] |
auto[1] |
338010 |
1 |
|
|
T24 |
67 |
|
T28 |
133 |
|
T36 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2314616 |
1 |
|
|
T21 |
6 |
|
T24 |
145 |
|
T28 |
577 |
| auto[1] |
auto[1] |
auto[1] |
339292 |
1 |
|
|
T24 |
34 |
|
T28 |
140 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7420398 |
1 |
|
|
T20 |
137 |
|
T21 |
40 |
|
T22 |
31297 |
| auto[1] |
5318148 |
1 |
|
|
T21 |
40 |
|
T24 |
727 |
|
T28 |
1530 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12061827 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
676719 |
1 |
|
|
T24 |
129 |
|
T28 |
250 |
|
T36 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450490 |
1 |
|
|
T20 |
137 |
|
T21 |
36 |
|
T22 |
31297 |
| auto[1] |
5288056 |
1 |
|
|
T21 |
44 |
|
T24 |
645 |
|
T28 |
1308 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2288834 |
1 |
|
|
T21 |
14 |
|
T24 |
177 |
|
T28 |
499 |
| auto[1] |
auto[0] |
auto[1] |
334916 |
1 |
|
|
T24 |
43 |
|
T28 |
121 |
|
T36 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2322503 |
1 |
|
|
T21 |
30 |
|
T24 |
339 |
|
T28 |
559 |
| auto[1] |
auto[1] |
auto[1] |
341803 |
1 |
|
|
T24 |
86 |
|
T28 |
129 |
|
T36 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443062 |
1 |
|
|
T20 |
137 |
|
T21 |
44 |
|
T22 |
31297 |
| auto[1] |
5295484 |
1 |
|
|
T21 |
36 |
|
T24 |
604 |
|
T28 |
1825 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12057789 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
680757 |
1 |
|
|
T24 |
144 |
|
T28 |
272 |
|
T1 |
6450 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7427441 |
1 |
|
|
T20 |
137 |
|
T21 |
66 |
|
T22 |
31297 |
| auto[1] |
5311105 |
1 |
|
|
T21 |
14 |
|
T24 |
777 |
|
T28 |
1438 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2327408 |
1 |
|
|
T21 |
5 |
|
T24 |
307 |
|
T28 |
453 |
| auto[1] |
auto[0] |
auto[1] |
342372 |
1 |
|
|
T24 |
70 |
|
T28 |
102 |
|
T1 |
3172 |
| auto[1] |
auto[1] |
auto[0] |
2302940 |
1 |
|
|
T21 |
9 |
|
T24 |
326 |
|
T28 |
713 |
| auto[1] |
auto[1] |
auto[1] |
338385 |
1 |
|
|
T24 |
74 |
|
T28 |
170 |
|
T1 |
3278 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469461 |
1 |
|
|
T20 |
137 |
|
T21 |
59 |
|
T22 |
31297 |
| auto[1] |
5269085 |
1 |
|
|
T21 |
21 |
|
T24 |
431 |
|
T28 |
1439 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12063537 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
675009 |
1 |
|
|
T24 |
78 |
|
T28 |
333 |
|
T36 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468610 |
1 |
|
|
T20 |
137 |
|
T21 |
60 |
|
T22 |
31297 |
| auto[1] |
5269936 |
1 |
|
|
T21 |
20 |
|
T24 |
423 |
|
T28 |
1687 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2299841 |
1 |
|
|
T21 |
16 |
|
T24 |
207 |
|
T28 |
555 |
| auto[1] |
auto[0] |
auto[1] |
338644 |
1 |
|
|
T24 |
49 |
|
T28 |
132 |
|
T36 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2295086 |
1 |
|
|
T21 |
4 |
|
T24 |
138 |
|
T28 |
799 |
| auto[1] |
auto[1] |
auto[1] |
336365 |
1 |
|
|
T24 |
29 |
|
T28 |
201 |
|
T1 |
3123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460240 |
1 |
|
|
T20 |
137 |
|
T21 |
58 |
|
T22 |
31297 |
| auto[1] |
5278306 |
1 |
|
|
T21 |
22 |
|
T24 |
586 |
|
T28 |
1644 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12065274 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
673272 |
1 |
|
|
T21 |
1 |
|
T24 |
66 |
|
T28 |
351 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7474078 |
1 |
|
|
T20 |
137 |
|
T21 |
50 |
|
T22 |
31297 |
| auto[1] |
5264468 |
1 |
|
|
T21 |
30 |
|
T24 |
369 |
|
T28 |
1776 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2288334 |
1 |
|
|
T21 |
9 |
|
T24 |
97 |
|
T28 |
625 |
| auto[1] |
auto[0] |
auto[1] |
334562 |
1 |
|
|
T24 |
23 |
|
T28 |
149 |
|
T36 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2302862 |
1 |
|
|
T21 |
20 |
|
T24 |
206 |
|
T28 |
800 |
| auto[1] |
auto[1] |
auto[1] |
338710 |
1 |
|
|
T21 |
1 |
|
T24 |
43 |
|
T28 |
202 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447707 |
1 |
|
|
T20 |
137 |
|
T21 |
68 |
|
T22 |
31297 |
| auto[1] |
5290839 |
1 |
|
|
T21 |
12 |
|
T24 |
330 |
|
T28 |
1383 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12063254 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
675292 |
1 |
|
|
T21 |
1 |
|
T24 |
110 |
|
T28 |
203 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7454997 |
1 |
|
|
T20 |
137 |
|
T21 |
44 |
|
T22 |
31297 |
| auto[1] |
5283549 |
1 |
|
|
T21 |
36 |
|
T24 |
608 |
|
T28 |
1123 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2298959 |
1 |
|
|
T21 |
28 |
|
T24 |
421 |
|
T28 |
483 |
| auto[1] |
auto[0] |
auto[1] |
336325 |
1 |
|
|
T21 |
1 |
|
T24 |
94 |
|
T28 |
106 |
| auto[1] |
auto[1] |
auto[0] |
2309298 |
1 |
|
|
T21 |
7 |
|
T24 |
77 |
|
T28 |
437 |
| auto[1] |
auto[1] |
auto[1] |
338967 |
1 |
|
|
T24 |
16 |
|
T28 |
97 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7444257 |
1 |
|
|
T20 |
137 |
|
T21 |
52 |
|
T22 |
31297 |
| auto[1] |
5294289 |
1 |
|
|
T21 |
28 |
|
T24 |
572 |
|
T28 |
1589 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12055599 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
682947 |
1 |
|
|
T24 |
169 |
|
T28 |
281 |
|
T36 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7409239 |
1 |
|
|
T20 |
137 |
|
T21 |
63 |
|
T22 |
31297 |
| auto[1] |
5329307 |
1 |
|
|
T21 |
17 |
|
T24 |
839 |
|
T28 |
1421 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2325184 |
1 |
|
|
T21 |
5 |
|
T24 |
355 |
|
T28 |
624 |
| auto[1] |
auto[0] |
auto[1] |
342058 |
1 |
|
|
T24 |
84 |
|
T28 |
146 |
|
T36 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2321176 |
1 |
|
|
T21 |
12 |
|
T24 |
315 |
|
T28 |
516 |
| auto[1] |
auto[1] |
auto[1] |
340889 |
1 |
|
|
T24 |
85 |
|
T28 |
135 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7400823 |
1 |
|
|
T20 |
137 |
|
T21 |
40 |
|
T22 |
31297 |
| auto[1] |
5337723 |
1 |
|
|
T21 |
40 |
|
T24 |
494 |
|
T28 |
1229 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12059185 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
679361 |
1 |
|
|
T24 |
133 |
|
T28 |
283 |
|
T36 |
1 |