Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450094 |
1 |
|
|
T20 |
137 |
|
T21 |
60 |
|
T22 |
31297 |
| auto[1] |
5288452 |
1 |
|
|
T21 |
20 |
|
T24 |
592 |
|
T28 |
1178 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12064737 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
673809 |
1 |
|
|
T21 |
1 |
|
T24 |
96 |
|
T28 |
269 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470145 |
1 |
|
|
T20 |
137 |
|
T21 |
65 |
|
T22 |
31297 |
| auto[1] |
5268401 |
1 |
|
|
T21 |
15 |
|
T24 |
484 |
|
T28 |
1424 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2300423 |
1 |
|
|
T21 |
8 |
|
T24 |
187 |
|
T28 |
713 |
| auto[1] |
auto[0] |
auto[1] |
337833 |
1 |
|
|
T24 |
47 |
|
T28 |
163 |
|
T36 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2294169 |
1 |
|
|
T21 |
6 |
|
T24 |
201 |
|
T28 |
442 |
| auto[1] |
auto[1] |
auto[1] |
335976 |
1 |
|
|
T21 |
1 |
|
T24 |
49 |
|
T28 |
106 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |