Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434727 |
1 |
|
|
T20 |
137 |
|
T21 |
52 |
|
T22 |
31297 |
| auto[1] |
5303819 |
1 |
|
|
T21 |
28 |
|
T24 |
441 |
|
T28 |
1437 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12062603 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
675943 |
1 |
|
|
T21 |
1 |
|
T24 |
119 |
|
T28 |
327 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7444286 |
1 |
|
|
T20 |
137 |
|
T21 |
60 |
|
T22 |
31297 |
| auto[1] |
5294260 |
1 |
|
|
T21 |
20 |
|
T24 |
592 |
|
T28 |
1616 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2316652 |
1 |
|
|
T21 |
15 |
|
T24 |
264 |
|
T28 |
678 |
| auto[1] |
auto[0] |
auto[1] |
339746 |
1 |
|
|
T21 |
1 |
|
T24 |
65 |
|
T28 |
170 |
| auto[1] |
auto[1] |
auto[0] |
2301665 |
1 |
|
|
T21 |
4 |
|
T24 |
209 |
|
T28 |
611 |
| auto[1] |
auto[1] |
auto[1] |
336197 |
1 |
|
|
T24 |
54 |
|
T28 |
157 |
|
T1 |
3532 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |