Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448298 |
1 |
|
|
T20 |
137 |
|
T21 |
61 |
|
T22 |
31297 |
| auto[1] |
5290248 |
1 |
|
|
T21 |
19 |
|
T24 |
485 |
|
T28 |
1585 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12058394 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
680152 |
1 |
|
|
T21 |
1 |
|
T24 |
81 |
|
T28 |
247 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434385 |
1 |
|
|
T20 |
137 |
|
T21 |
59 |
|
T22 |
31297 |
| auto[1] |
5304161 |
1 |
|
|
T21 |
21 |
|
T24 |
447 |
|
T28 |
1285 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2315329 |
1 |
|
|
T21 |
16 |
|
T24 |
247 |
|
T28 |
538 |
| auto[1] |
auto[0] |
auto[1] |
339927 |
1 |
|
|
T21 |
1 |
|
T24 |
55 |
|
T28 |
128 |
| auto[1] |
auto[1] |
auto[0] |
2308680 |
1 |
|
|
T21 |
4 |
|
T24 |
119 |
|
T28 |
500 |
| auto[1] |
auto[1] |
auto[1] |
340225 |
1 |
|
|
T24 |
26 |
|
T28 |
119 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |