Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445477 |
1 |
|
|
T20 |
137 |
|
T21 |
44 |
|
T22 |
31297 |
| auto[1] |
5293069 |
1 |
|
|
T21 |
36 |
|
T24 |
662 |
|
T28 |
1497 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12058426 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
680120 |
1 |
|
|
T21 |
1 |
|
T24 |
115 |
|
T28 |
228 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7427454 |
1 |
|
|
T20 |
137 |
|
T21 |
54 |
|
T22 |
31297 |
| auto[1] |
5311092 |
1 |
|
|
T21 |
26 |
|
T24 |
576 |
|
T28 |
1165 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2313072 |
1 |
|
|
T21 |
8 |
|
T24 |
173 |
|
T28 |
478 |
| auto[1] |
auto[0] |
auto[1] |
338898 |
1 |
|
|
T24 |
45 |
|
T28 |
113 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2317900 |
1 |
|
|
T21 |
17 |
|
T24 |
288 |
|
T28 |
459 |
| auto[1] |
auto[1] |
auto[1] |
341222 |
1 |
|
|
T21 |
1 |
|
T24 |
70 |
|
T28 |
115 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |