Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447904 |
1 |
|
|
T20 |
137 |
|
T21 |
40 |
|
T22 |
31297 |
| auto[1] |
5290642 |
1 |
|
|
T21 |
40 |
|
T24 |
501 |
|
T28 |
1532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12064254 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
674292 |
1 |
|
|
T21 |
1 |
|
T24 |
103 |
|
T28 |
279 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7465008 |
1 |
|
|
T20 |
137 |
|
T21 |
45 |
|
T22 |
31297 |
| auto[1] |
5273538 |
1 |
|
|
T21 |
35 |
|
T24 |
524 |
|
T28 |
1493 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2304753 |
1 |
|
|
T21 |
13 |
|
T24 |
262 |
|
T28 |
516 |
| auto[1] |
auto[0] |
auto[1] |
337562 |
1 |
|
|
T21 |
1 |
|
T24 |
69 |
|
T28 |
117 |
| auto[1] |
auto[1] |
auto[0] |
2294493 |
1 |
|
|
T21 |
21 |
|
T24 |
159 |
|
T28 |
698 |
| auto[1] |
auto[1] |
auto[1] |
336730 |
1 |
|
|
T24 |
34 |
|
T28 |
162 |
|
T36 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |