Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431336 |
1 |
|
|
T20 |
137 |
|
T21 |
55 |
|
T22 |
31297 |
| auto[1] |
5307210 |
1 |
|
|
T21 |
25 |
|
T24 |
422 |
|
T28 |
1367 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10533685 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
2204861 |
1 |
|
|
T24 |
384 |
|
T28 |
876 |
|
T36 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7424108 |
1 |
|
|
T20 |
137 |
|
T21 |
69 |
|
T22 |
31297 |
| auto[1] |
5314438 |
1 |
|
|
T21 |
11 |
|
T24 |
783 |
|
T28 |
1759 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1551100 |
1 |
|
|
T21 |
7 |
|
T24 |
252 |
|
T28 |
450 |
| auto[1] |
auto[0] |
auto[1] |
1102586 |
1 |
|
|
T24 |
254 |
|
T28 |
474 |
|
T36 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1558477 |
1 |
|
|
T21 |
4 |
|
T24 |
147 |
|
T28 |
433 |
| auto[1] |
auto[1] |
auto[1] |
1102275 |
1 |
|
|
T24 |
130 |
|
T28 |
402 |
|
T1 |
15083 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |