Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7420435 |
1 |
|
|
T20 |
137 |
|
T21 |
50 |
|
T22 |
31297 |
| auto[1] |
5318111 |
1 |
|
|
T21 |
30 |
|
T24 |
366 |
|
T28 |
1665 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10543086 |
1 |
|
|
T20 |
137 |
|
T21 |
77 |
|
T22 |
31297 |
| auto[1] |
2195460 |
1 |
|
|
T21 |
3 |
|
T24 |
372 |
|
T28 |
844 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7433368 |
1 |
|
|
T20 |
137 |
|
T21 |
66 |
|
T22 |
31297 |
| auto[1] |
5305178 |
1 |
|
|
T21 |
14 |
|
T24 |
714 |
|
T28 |
1764 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1550356 |
1 |
|
|
T21 |
7 |
|
T24 |
200 |
|
T28 |
414 |
| auto[1] |
auto[0] |
auto[1] |
1092788 |
1 |
|
|
T21 |
3 |
|
T24 |
221 |
|
T28 |
366 |
| auto[1] |
auto[1] |
auto[0] |
1559362 |
1 |
|
|
T21 |
4 |
|
T24 |
142 |
|
T28 |
506 |
| auto[1] |
auto[1] |
auto[1] |
1102672 |
1 |
|
|
T24 |
151 |
|
T28 |
478 |
|
T36 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |