Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7462538 |
1 |
|
|
T20 |
137 |
|
T21 |
41 |
|
T22 |
31297 |
| auto[1] |
5276008 |
1 |
|
|
T21 |
39 |
|
T24 |
582 |
|
T28 |
1595 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10548584 |
1 |
|
|
T20 |
137 |
|
T21 |
72 |
|
T22 |
31297 |
| auto[1] |
2189962 |
1 |
|
|
T21 |
8 |
|
T24 |
221 |
|
T28 |
895 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460293 |
1 |
|
|
T20 |
137 |
|
T21 |
44 |
|
T22 |
31297 |
| auto[1] |
5278253 |
1 |
|
|
T21 |
36 |
|
T24 |
489 |
|
T28 |
1687 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1556612 |
1 |
|
|
T21 |
10 |
|
T24 |
100 |
|
T28 |
302 |
| auto[1] |
auto[0] |
auto[1] |
1104243 |
1 |
|
|
T21 |
4 |
|
T24 |
85 |
|
T28 |
386 |
| auto[1] |
auto[1] |
auto[0] |
1531679 |
1 |
|
|
T21 |
18 |
|
T24 |
168 |
|
T28 |
490 |
| auto[1] |
auto[1] |
auto[1] |
1085719 |
1 |
|
|
T21 |
4 |
|
T24 |
136 |
|
T28 |
509 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |