Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447171 |
1 |
|
|
T20 |
137 |
|
T21 |
63 |
|
T22 |
31297 |
| auto[1] |
5291375 |
1 |
|
|
T21 |
17 |
|
T24 |
540 |
|
T28 |
1438 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10556178 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
2182368 |
1 |
|
|
T24 |
325 |
|
T28 |
749 |
|
T36 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7461117 |
1 |
|
|
T20 |
137 |
|
T21 |
77 |
|
T22 |
31297 |
| auto[1] |
5277429 |
1 |
|
|
T21 |
3 |
|
T24 |
650 |
|
T28 |
1533 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1552339 |
1 |
|
|
T21 |
3 |
|
T24 |
174 |
|
T28 |
407 |
| auto[1] |
auto[0] |
auto[1] |
1095016 |
1 |
|
|
T24 |
172 |
|
T28 |
377 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1542722 |
1 |
|
|
T24 |
151 |
|
T28 |
377 |
|
T36 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1087352 |
1 |
|
|
T24 |
153 |
|
T28 |
372 |
|
T36 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |