Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426436 |
1 |
|
|
T20 |
137 |
|
T21 |
52 |
|
T22 |
31297 |
| auto[1] |
5312110 |
1 |
|
|
T21 |
28 |
|
T24 |
657 |
|
T28 |
1410 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2297603 |
1 |
|
|
T21 |
5 |
|
T24 |
259 |
|
T28 |
601 |
| auto[1] |
auto[0] |
auto[1] |
336521 |
1 |
|
|
T24 |
63 |
|
T28 |
148 |
|
T1 |
3237 |
| auto[1] |
auto[1] |
auto[0] |
2335146 |
1 |
|
|
T21 |
23 |
|
T24 |
265 |
|
T28 |
526 |
| auto[1] |
auto[1] |
auto[1] |
342840 |
1 |
|
|
T24 |
70 |
|
T28 |
135 |
|
T36 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |